RELATED APPLICATIONS

[0001] This application claims benefit of priority of U.S. Provisional Patent Application

Serial No. 62/449,351 filed on January 23, 2017, and U.S. Non-Provisional Application

Serial No. 15/637,357, filed on June 29, 2017, the entire contents of which are incorporated herein by reference.

FIELD

[0002] The present disclosure relates generally to the field of semiconductor devices and specifically to resistive memory devices employing nanoparticles, and methods of manufacturing the same.

BACKGROUND

[0003] Resistive random access memory (ReRAM) devices refer to non-volatile memory (NVM) devices that employ multiple resistive states of a material. ReRAM devices have the potential to provide high memory density at low cost with fast read/write access time and high endurance.

SUMMARY

[0004] According to one embodiment of the present disclosure, a method of fabricating a memory cell comprises forming a first electrode, providing polymer-grafted memory material nanoparticles which form a polymer matrix made of polymeric ligand that embeds the memory material nanoparticles, and forming a second electrode.

[0005] According to another embodiment of the present disclosure, a barrier modulated memory cell, comprises a first electrode, a variable resistance region comprising metal oxide nanoparticles and a barrier material in contact with the metal oxide nanoparticles, and a second electrode.

[0006] According to another embodiment of the present disclosure, a projected memory cell comprises a first electrode, a second electrode, and a variable resistance region located between the first and the second electrodes. The variable resistance region comprises chalcogenide phase change memory material nanoparticles and a projection material liner that connects the first electrode to the second electrode. The projection material liner has a resistivity which is between low and high resistance states of the chalcogenide phase change memory material.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1A illustrates a polymer-grafted nanoparticles. Polymeric chains (ligands) are grafted to nanoparticle cores according to a first embodiment of the present disclosure.

[0008] FIG. IB illustrates polymer grafted nanoparticles that are deposited onto a substrate by spin coating. Individual polymeric chains are not shown for clarity, and are represented by a uniform matrix formed by the polymer chains according to the first embodiment of the present disclosure.

[0009] FIG. 1C illustrates dried polymer grafted nanoparticles, which form a dense array with the ligands interpenetrating and forming a uniform matrix. The ligands keep the particles at a uniform distance and form an embedding polymer matrix according to the first embodiment of the present disclosure.

[0010] FIG. ID illustrates a solvent annealing step, which is used to facilitate self- assembly and rearrange the nanoparticles according to the first embodiment of the present disclosure.

[0011] FIGS. 2A, 2B, and 2C schematically illustrate a process flow for fabrication of a first exemplary resistive memory cell including an opening through an insulating layer over a first electrode according to the first embodiment of the present disclosure.

[0012] FIGS. 3 A, 3B, and 3C schematically illustrate polymer- grafted nanoparticles assembled inside different configurations of the first exemplary resistive memory cell, each including an opening having different sizes and aspect ratios according to the first embodiment of the present disclosure.

[0013] FIGS. 4A, 4B, and 4C illustrate various configurations of the first exemplary resistive memory cell after removal of the polymer matrix by a heat treatment and/or exposing the sample to an acid or solvent vapor that detaches the ligands, and deposition of a second electrode according to the first embodiment of the present disclosure.

[0014] FIGS. 5 A, 5B, and 5C illustrate a manufacturing process for first, second, and third configurations of a second exemplary resistive memory cell in which the ligands are removed prior to formation of a second electrode according to a second embodiment of the present disclosure.

[0015] FIG. 6 illustrates the processing steps of ALD infiltration synthesis, polymer removal, matrix hardening, liftoff, and second electrode deposition for manufacture of a third exemplary resistive memory cell according to a third embodiment of the present disclosure.

[0016] FIGS. 7 A and 7B illustrate fourth exemplary memory cells having a "projection material" along the walls of the cell according to a fourth embodiment of the present disclosure. Nanoparticles may be deposited and treated in the same manner as in the first or second embodiments.

[0017] FIGS. 8 A and 8B illustrate fifth exemplary memory cells having a "projection material" along the walls of the cell according to a fifth embodiment of the present disclosure. Nanoparticles may be deposited and the cell is filled with ALD infiltration synthesis according to the third embodiment.

[0018] FIGS. 9A - 9C illustrate sixth exemplary memory cells with a constriction zone between the second electrode and the first electrode according to a sixth embodiment of the present disclosure. Nanoparticles may be formed according to any of the first through third embodiments.

[0019] FIGS. 10A and 10B illustrate seventh exemplary memory cells of the barrier memory cell type according to a seventh embodiment of the present disclosure.

[0020] FIG. 11 illustrates a seventh exemplary memory cell including nanoparticle cores each having an inner core and an outer shell according to an eighth embodiment of the present disclosure.

[0021] FIG. 12A is a perspective view of a first configuration of a ninth exemplary memory cell including planar layers according to an eighth embodiment of the present disclosure.

[0022] FIG. 12B is a schematic vertical cross-sectional view of the first configuration of the ninth exemplary memory cell of FIG. 12A.

[0023] FIG. 12C is a perspective view of a second configuration of the ninth exemplary memory cell including planar layers according to an eighth embodiment of the present disclosure.

[0024] FIG. 12D is a schematic vertical cross-sectional view of the second configuration of the ninth exemplary memory cell of FIG. 12C.

[0025] FIG. 13 is vertical cross- sectional view of a tenth exemplary memory cell according to a tenth embodiment of the present disclosure. [0026] FIGS. 14A - 14E illustrates a sequence of processing steps that can be employed to form any of the third through twelfth exemplary structures of the present disclosure.

[0027] FIGS. 15A - 15F illustrates another sequence of processing steps that can be employed to form any of the third through twelfth exemplary structures of the present disclosure.

DETAILED DESCRIPTION

[0028] As discussed above, the present disclosure is directed to resistive memory devices employing nanoparticles, and methods of manufacturing the same, the various aspects of which are described below. The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as "first," "second," and "third" are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. As used herein, a first element located "on" a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located "directly on" a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, an "in-process" structure or a "transient" structure refers to a structure that is subsequently modified.

[0029] As used herein, a "nanoparticle" is a particle having a maximum dimension (such as a diameter) less than 100 microns, such as less than 1 micron, for example 1 to 900 nm, such as 2 to 500 nm, including 5 to 100 nm. A plurality of nanoparticles comprises particles with an average maximum dimension in the above range(s). Nanoparticles may be single crystalline (i.e., nanocrystals), polycrystalline or amorphous.

[0030] As used herein, a "polymer" refers to a compound or mixture of compounds formed by polymerization and comprising (e.g., consisting essentially) of repeating structural units. For example, in one embodiment, a polymer can be a substance consisting of molecules characterized by the sequence of one or more types of monomer units and comprising a simple weight majority of molecules containing at least three monomer units which are covalently bound to at least one other monomer unit or other reactant and consists of less than a simple weight majority of molecules of the same molecular weight. The degree of polymerization, i.e., the number of monomer units in the polymer, may be in a range from 1,000 to 100,000, although lesser and greater numbers can also be employed. A monomer unit is the reacted form of a monomer in a polymer.

[0031] As used herein, a "layer" refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and/or may have one or more layer thereupon, thereabove, and/or therebelow.

[0032] As used herein, a "semiconducting material" refers to a material having electrical conductivity in the range from 1.0 x 10 ^"6 S/cm to 1.0 x 10 ⁵ S/cm. As used herein, a

"semiconductor material" refers to a material having electrical conductivity in the range from 1.0 x 10 ^~6 S/cm to 1.0 x 10 ⁵ S/cm in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/cm to 1.0 x 10 ⁵ S/cm upon suitable doping with an electrical dopant. As used herein, an "electrical dopant" refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a "conductive material" refers to a material having electrical conductivity greater than 1.0 x 10 ⁵ S/cm. As used herein, an "insulating material", "insulator material" or a "dielectric material" refers to a material having electrical conductivity less than 1.0 x 10 ^"6 S/cm. As used herein, a "heavily doped semiconductor material" refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material, i.e., to have electrical conductivity greater than 1.0 x 10 ⁵ S/cm. A "doped semiconductor material" may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0 x 10 ^"6 S/cm to 1.0 x 10 ⁵ S/cm. An "intrinsic semiconductor material" refers to a

semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a "metallic material" refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.

[0033] As used herein, a "resistive memory material" or a "reversibly resistance- switching material" is a material of which the resistivity can be altered by application of a voltage across the material. As used herein, a "resistive memory material layer" refers to a layer including a resistive memory material. As used herein, a "resistive memory material nanoparticle" refers to a nanoparticle including a resistive memory material. As used herein, a "resistive memory element" refers to an element that includes a portion of a resistive memory material in a configuration that enables programming of the resistive memory material into at least two states having different values of electrical resistance.

[0034] According to an aspect of the present disclosure, a structure employing nanoparticles including a resistive memory material is provided, which can be employed to provide a design in the area of the device on a surface of a substrate does not limit the amount of active interface for memory switching. By embedding nanoparticles inside the memory cell, the amount of active interface is dictated by the amount of surface area of the

nanoparticles in contact with the embedding medium, or the amount of nanoparticles between two electrodes. The total amount of active interface may be tuned by the size and the density of the nanoparticles, and not limited by the cell area (the footprint) on the substrate. Further, blends or superlattices of two or more types of nanoparticles can be embedded in a memory cell. This feature provides flexibility in interface engineering and a potential path for multilevel and/or neuromorphic memory cells.

[0035] The present disclosure provides a nanoparticle-based resistive memory device that can be employed to facilitate control and reproducibility of the switching volume and stability of the resistance levels. Various embodiments of nanoparticle-based resistive memory cells are provided. The nanoparticles of the present disclosure can be ligand-grafted conductive metal oxide nanoparticles, or ligand-grafted chalcogenide nanoparticles. [0036] The switching volume for a phase change memory material or the active interface for a barrier modulated memory material is limited and controlled by the size of the nanoparticles, and is not significantly affected by the programming voltage. Ligand-grafted nanoparticles of the present disclosure offer a path to nanocomposite memory cells where the properties of the matrix material can be tuned for better reliability and performance.

[0037] In some embodiments, the organic ligands comprise polymer ligands or monomer ligands which are subsequently polymerized to form polymer ligands, In some embodiments, polymer coated resistive memory nanoparticles may provide one or more of the following advantages: (a) uniform coating over a wafer scale using standard spin coating (which is not believed to be not possible with alkyl chain ligands as known in the art); (b) uniformly filling small, deep cavities in the range of 10 nm - 100 nm; (c) composite memory cell in which the space between particles is filled by ALD infiltration synthesis and choice of a material for tuning resistivity; (d) control of the switching volume by selection of the nanoparticle size and tuning of the resistivity by selection of the filling material; and (e) a design for a multilevel memory cell.

[0038] According to a first embodiment of the present disclosure, a uniform and conformal coating or filling can be achieved by using polymer coated nanoparticles.

Additional space filling or an additional material is not required in the first embodiment.

[0039] Referring to FIG. 1A, ligand-grafted nanoparticles (51, 53) according to embodiments of the present disclosure are shown. Each of the ligand-grafted nanoparticles (51, 53) includes a nanoparticle core (i.e., nanoparticle) 52 and ligands 51 that are grafted to the nanoparticle core 52. The nanoparticle core 52 includes a resistive memory material. Each ligand-grafted nanoparticle including a nanoparticle core 52 and attached ligands 51 is a nanoparticle having a maximum dimension (such as a diameter) less than 1 micron, less than 300 nm, less than 100 nm, and/or less than 30 nm, and greater than 1 nm. In one

embodiment, each of the ligand-grafted nanoparticles (51, 52) can comprise a nanoparticle core 52 that comprises a first material selected from a conductive metal oxide, a

semiconducting metal oxide, and a chalcogenide material, and further comprises ligands 51 that are grafted to the nanoparticle core 52.

[0040] In one embodiment, the nanoparticles 52 can include ay chalcogenide resistive memory material known in the art. In one embodiment, the nanoparticles (e.g., nanoparticle cores) 52 include chalcogenide nanoparticles such as GeTe, GeSbTe, AglnSbTe, etc., preferably with diameters in the range of 2 nm - 100 nm.

[0041] The nanoparticles can be capped with polymeric ligands, such as polystyrene (PS), polyvinyl 2 vinylpyridine (P2VP), polyvinyl 4 vinylpyridine (P4VP),

polydimethylsiloxane (PDMS), polymethyl methacrylate (PMMA), etc. The polymeric ligands may have molecular weights in the range of 0.5 kg/mol to 50 kg/mol. The nanoparticles are dispersed in a suitable solvent for the polymeric ligand (e.g., toluene, methyl isobutyl ketone (MIBK), methyl ethyl ketone (MEK), acetone, dimethylformamide (DMF), chlorobenzene, etc). Polymeric chains (ligands) are grafted to nanoparticle cores at the processing step of FIG. 1A to form a polymer-grafted nanoparticle.

[0042] In another embodiment, the nanoparticles 52 can include a metal oxide material that provides at least two resistive states having different resistivity. The nanoparticles 52 may be semiconducting or conductive in each of the at least two resistive states. In other words, the nanoparticles 52 can have a conductivity in a range from 1.0 x 10 ^"6 S/cm to 1.0 x 10 ¹⁰ S/cm in each of the at least two resistive states. [0043] In one embodiment, the nanoparticles 52 comprise a metal oxide material selected from titanium oxide, hafnium oxide, zinc oxide, vanadium oxide, niobium oxide, tantalum oxide, strontium titanate and tin oxide for use in a barrier modulated cell (BMC). Examples of metal oxide materials include a slightly sub-stoichiometric metal oxide such as Ti0 ₂ _g, SrTi0 ₃ _ s, Nb0 ₂ _ g, or Nb:SrTi0 ₃ _ g where value of δ can be independently selected from a range from 0 to 0.5, such as greater than zero to 0.15 (i.e., to form a sub-stoichiometric, oxygen deficient metal oxide). For example, the metal oxide material may be titanium oxide, such as sub-stoichiometric titanium oxide having less than two oxygen atoms for each titanium atom. In one embodiment, the metal oxide may have a high concentration of free electrons in thermodynamic equilibrium in a range from 1.0 x 10 20 /cm 3 to 1.0 x 1021 /cm 3.

[0044] A barrier modulated cell is a non-filamentary memory cell (i.e., where no conductive filaments are formed) in which an energy barrier is formed at the interface between the nanoparticles 52 and an adjacent material. The energy width and energy height of the barrier may be modulated by the diffusion of oxygen vacancies and/or interstitial oxygen ions in and out of the interface. The modulation of the energy band structure at the interface can provide a change to the overall resistivity of the variable resistance region. The vacancies and/or interstitial oxygen ions may be rearranged by applying a voltage to the resistive memory cell. The adjacent material may comprise amorphous silicon, germanium, silicon oxide, aluminum oxide, tantalum oxide, etc.

[0045] In one embodiment, the ligands 51 comprise an organic material, such as at least one of functionalized alkyl chains or polymeric ligands. In case polymeric ligands are employed, the polymeric ligands can provide the following attributes either alone or in combination depending on embodiments. The polymeric ligands of the embodiments of present disclosure may facilitate uniform deposition and uniform filling of cell cavities from spin coating and solvent annealing. The polymeric ligands of the present disclosure may provide a uniform spacing and a regular assembly of the nanoparticles during solvent annealing. The spacing provided between particles and the presence of the polymeric matrix made by the ligands may be exploited to fabricate multilevel cells. The spacing provided between particles and the presence of the polymeric matrix may enable infiltration synthesis within the polymeric matrix using atomic layer deposition precursors. This, in turn, may enable the fabrication of cells similar to "projected memory cells" but with better control of the switching volume of the phase change material.

[0046] In some embodiments, ligand-grafted nanoparticles can fill deep trenches conformally and uniformly because they are solution processed. The composition and stoichiometry is not affected by the depth of the cell to be filled, whereas ALD or PECVD deposition methods suffer from uniformity issues when trenches are too deep.

[0047] Ligand-grafted nanoparticles (51, 52) include nanoparticle cores 52 (which can include a chalcogenide or metal oxide material) that are tethered by ligand chains 51 as shown in the FIG. 1A. Ligand-grafted nanoparticles can be dissolved in organic solvents and then deposited over a substrate. Once the solvent evaporates, the nanoparticles (51, 52) assemble closely together. The polymeric chains interpenetrate each other but also prevent the particles from touching.

[0048] Referring to FIG. IB, a first exemplary resistive memory cell is illustrated during manufacture before drying the liquid dispersion 250. A first electrode 20 comprising a conductive material is formed on a substrate 10. Nanoparticles 52 capped with organic or polymeric ligands 51 are dissolved in a solvent 54 to provide a liquid dispersion 250. The liquid dispersion 250 including the ligand-grafted nanoparticles (51, 52) is dispensed from a container 150 onto a top surface of the first electrode 20 employing an applicator 920. The method of application may be selected from, but is not limited to, spin-coating, dip-coating, drop-casting, spraying, ink-jet printing and print-transfer. As used herein, a "liquid dispersion" refers to a liquid solution in which particles are suspended.

[0049] In an illustrative example, the ligand-grafted nanoparticles (51, 52) are deposited onto the substrate 10 by spin coating. For example, the liquid dispersion 250 of the ligand- grafted nanoparticles (51, 52) can be spin-coated onto the substrate 10 to form a film with uniform coverage over the wafer. Film coverage can be tuned to range from sub-monolayer to several tens of layers.

[0050] Referring to FIG. 1C, a drying process can be performed. When dried, the ligand- grafted nanoparticles (51 , 52) form a dense array with the ligands interpenetrating and forming a uniform matrix 53. Thus, the assembled material forms a composite of

nanoparticles 52 embedded in a polymeric matrix 53 formed by the ligands 51 as shown in FIG. 1C. It is understood that evaporation of the carrier solvent from the liquid dispersion 250 results in conversion of the liquid dispersion into a film, which is no longer a liquid. The film contains the combination of the matrix 53 and the nanoparticle cores 52. If polymer- grafted nanoparticles are provided in the liquid dispersion, the film can be a film of polymer- grafted nanoparticles. The ligands 51 keep the particles at a uniform distance and form an embedding polymer matrix 53. In subsequent drawings, the individual polymeric chains are omitted for clarity and are replaced by the uniform matrix 53 formed by them. While the individual polymeric chains are not expressly shown in subsequent drawings, it is understood that polymeric chains are present in a continuous embedding matrix formed by the polymers. [0051] Referring to FIG. ID, a solvent annealing step can be optionally used to facilitate self-assembly that rearranges the nanoparticles 52. For example, the substrate 10 can be taken into a solvent annealing chamber 930 where the film is exposed to a controlled vapor pressure of a suitable solvent (Toluene, MIBK, MEK, Acetone, DMF, etc). The polymers in the soft coronas of the particles swell and facilitate rearrangement of the particle assembly into a uniform, ordered structure.

[0052] The combination of the nanoparticles 52 and the matrix 53 constitute a variable resistance region including the nanoparticle cores 52. A second electrode (not shown) can be formed on the variable resistance region to form a resistive memory cell.

[0053] Recesses, openings, trenches, cavities or other geometries can be formed over the substrate 10 prior to application of the liquid dispersion 250. For example, an insulating layer can be formed over the first electrode 20, and an opening can be formed through the insulating layer, and can be filled by the nanoparticles 52 and the matrix 53 to define a memory cell.

[0054] Referring to FIGS. 2A - 2C, a fabrication process is illustrated for forming an opening 39 in an insulating layer 40 over a first electrode 20. The first electrode 20 can be deposited on the substrate 10, for example, by sputtering, vapor deposition, ion beam deposition, ALD, etc. as illustrated in FIG. 2A. An insulating layer 40 including a dielectric material (e.g., silicon oxide) can be deposited on the first electrode 20. A resist material layer 47 can be formed on the insulating layer, which may be a photoresist, an e-beam resist, a nanoimprint resist or a block copolymer.

[0055] Referring to FIG. 2B, an opening can be patterned in the resist material layer 47, for example, by lithographic exposure and development, or by imprinting. The maximum lateral dimension L of the opening can be, for example, in a range from 1.2 times the maximum lateral dimension of the ligand-grafted nanoparticles (51, 52) to 100,000 times the maximum lateral dimension of the ligand-grafted nanoparticles (51, 52).

[0056] Referring to FIG. 2C, an opening 39 extending through the insulating layer 40 can be formed by an etch process that employs the patterned resist material layer 47 as an etch mask. The etch process can be an anisotropic etch process or an isotropic etch process. The depth d of the opening can be the same as the thickness of the insulating layer 40, which may be in a range from 1 nm to 10 microns. A top surface of the first electrode 20 is physically exposed at a bottom of the opening 39. The patterned resist material layer 47 can be removed at this time (e.g., by ashing) or left over the insulating layer 40 to serve as a lift-off layer in a subsequent step shown in FIGS. 3 A to 4C.

[0057] FIGS. 3 A - 3C show a subsequent processing step in which a liquid dispersion 250 is applied and dried to form a combination of a matrix 53 (which may be a polymerized matrix) and nanoparticle cores 52. It is understood that evaporation of the carrier solvent from the liquid dispersion 250 results in conversion of the liquid dispersion into a film, which is no longer a liquid. The film contains the combination of the matrix 53 and the nanoparticle cores 52. If polymer-grafted nanoparticles are provided in the liquid dispersion, the film can be a film of polymer- grafted nanoparticles.

[0058] FIGS. 3 A - 3C illustrate different configurations of openings having different sizes and aspect ratios. For example, the thickness of the insulating layer 40 can be within a range from the maximum thickness of the ligand-grafted nanoparticles (51, 52) to twice the maximum thickness of the ligand-grafted nanoparticles (51, 52) as illustrated in FIG. 3 A. Alternatively, the thickness of the insulating layer 40 and the maximum lateral dimension of the opening 39 in the insulating layer 40 can be more than twice the maximum thickness of the ligand-grafted nanoparticles (51, 52) as illustrated in FIG. 3B. Yet alternatively, the maximum lateral dimension of the opening 39 through the insulating layer 40 can be less than twice the maximum lateral dimension of the ligand-grafted nanoparticles (51, 52) and the opening 39 can be configured to accommodate a vertical stack of multiple ligand-grafted nanoparticles (51, 52) as illustrated in FIG. 3C. Any intermediate configuration among FIGS. 3 A - 3C can also be employed. Application of the liquid dispersion 250 and formation of the combination of the matrix 53 and nanoparticle cores (i.e., nanoparticles) 52 may be performed employing the methods described above, or employing any of the methods to be described below.

[0059] FIGS. 4A - 4C, the resist material layer 47 can be removed, for example, by dissolution in a solvent, by lift-off, or by ashing to lift off the portion of the matrix 53 located over layer 47 and to leave another portion of the matrix 53 in the opening 39.

[0060] A second electrode 80 is formed on a top surface of the insulating layer 40 by deposition of a conductive material, which may be a metallic material (e.g., TiN, TaN, W, Al, Cu, Pt, Ti, etc.) or a heavily doped semiconductor material (such as doped silicon including p-type dopants or n-type dopants at an atomic concentration greater than 1.0 x 10 20 /cm 3 ). Additional memory device levels can be formed over the devices of FIGS. 4A, 4B and 4C to form a three dimensional ReRAM device. In one embodiment, at least 50 % (which may be more than 80 % and/or more than 90 %) of all nanoparticle cores 52 in the matrix 53 do not physically contact any other nanoparticle core 52 within the matrix 53.

[0061] The first exemplary memory cells illustrated in FIGS. 4A - 4C are examples of a fully enclosed memory cell with a single type of nanoparticle core 52. A cavity (i.e., an opening) in the form of a trench or a well is fabricated in an insulating layer 40. The cavity is filled with nanoparticle cores 52 including a first resistive memory material and embedded in a matrix 53 including a matrix material. One of the first electrode 20 and the second electrode 80 can be a bottom electrode having a planar top surface contacting the matrix 50, and another of the first electrode 20 and the second electrode 80 can be a top electrode having a planar bottom surface contacting the matrix 50. The various dimensions of the first exemplary memory cells can vary to contain anywhere from one to hundreds, thousands, or millions, of nanoparticle cores 52 in a mono-layer arrangement (such as the configuration of FIG. 4A), in a multilayer arrangement (such as the configuration of FIG. 4B), or in a columnar arrangement (such as the configuration of FIG. 4C).

[0062] According to another aspect of the present disclosure, the ligands 51 or the matrix 53 can be removed prior to formation of the second electrode 80. FIGS. 5 A, 5B, and 5C illustrate a manufacturing process for first, second, and third configurations of a second exemplary resistive memory cell in which the ligands 51 are removed, or the matrix 53 is removed, prior to formation of a second electrode 80 according to a second embodiment of the present disclosure. After application of the liquid dispersion 250 into the openings 39, the ligands 51 or the matrix 53 derived from the liquid dispersion 250 can be removed employing at least one process selected from thermal decomposition, plasma treatment or exposure to a solvent or acid vapor that detaches the polymeric ligand from the nanoparticle cores 52. For example, the ligands 51 can be removed by thermal decomposition and/or by exposing the sample to a solvent or acid vapor that detaches the polymer from the

nanoparticle cores 52.

[0063] Upon removal of the ligands 51, the nanoparticles 52 collapse, and optionally may be sintered, as depicted in FIGS. 5 A, 5B, and 5C. In this case, the nanoparticles 52 can contact other nanoparticles 52 to provide a continuous path consisting of a subset of the nanoparticles 52 between the first electrode 20 and the second electrode 80 after removal of the ligands 51. In this embodiment, there is no matrix material in the final memory device. In one embodiment, at least 50 % (such as more than 80 % and/or more than 90 %) of all nanoparticles 52 can contact another nanoparticle 52 after removal of the ligands 51. The assembly of the nanoparticles 52 constitutes a matrix free variable resistance region in this embodiment.

[0064] Subsequently, a second electrode 80 is deposited on top of the assembly of the nanoparticle cores 52 as illustrated in the right-side drawings of FIGS. 5A, 5B, and 5C. Additional memory device levels can be formed over the devices of FIGS. 5 A, 5B and 5C to form a three dimensional ReRAM device.

[0065] Referring to FIG. 6, a third exemplary resistive memory device according to a third embodiment of the present disclosure is illustrated. In the third embodiment, the matrix 53 (which may be an organic matrix, such as a polymer matrix) provided at the processing steps of FIGS. 3 A - 3C can be backfilled (i.e., replaced) by infiltration atomic layer deposition (ALD) synthesis. In this embodiment, the organic matrix may be replaced by an inorganic matrix. The fabrication can be the same as in the first embodiment up to deposition and optional annealing of the ligand-grafted nanoparticles (51, 52) in the openings 39 as shown in FIGS. 3 A - 3C. Subsequently, the exemplary resistive memory device can be placed in an ALD chamber where the matrix 53 is exposed to molecules of the precursor material 155 of an ALD process that are supplied in a vapor phase. Molecules of the precursor material 155 infiltrate the matrix 53 and either grow material around the nanoparticle cores 52 or along the polymer chains of the matrix 53 depending on the functionality of the polymer chains. This process is referred to as an atomic layer deposition infiltration process, and induces infiltration of the precursor material 155 into the matrix 53. In one embodiment, the precursor material 155 forms a modified matrix 156 (i.e., a new matrix) upon reaction with, or substitution of, the material in the ligand-grafted nanoparticles 51 (which can be in the form of the matrix 53).

[0066] In one embodiment, the precursor material 155 can react with the ligands 51 (as incorporated into the matrix 53) to form a semi-insulating material. If the precursor material 155 binds to the polymeric chains of the matrix 53, then the ALD synthesis occurs along the chains in the matrix 53. This forms a permanent matrix, such as an inorganic matrix, which is herein referred to as a modified matrix 156. Optionally, unreacted portions of the initial matrix 53 may be subsequently removed selective to the modified matrix 156.

[0067] Alternatively, if the polymer chains are inert to the precursors, the ALD synthesis can occur around the nanoparticle cores 52. In this case, the ligand-grafted nanoparticles (51, 52) can comprise nanoparticle shells (located between nanoparticle cores 52 and the ligands 51; not expressly shown) that enclose a respective one of the nanoparticle cores 52 and are directly attached to the ligands 51, and the ligands can be inert to the precursor material. In this case, the precursor material can react with the nanoparticles shells to form the semi- insulating or insulating material of the modified matrix 156.

[0068] After the ALD infiltration synthesis, any remaining portion of the initial polymer matrix 53 may be optionally removed by plasma treatment (0 ₂ , C0 ₂ , H ₂ -Ar, CHF ₃ , and/or CF ₄ ), or by a heat treatment. The polymer removal step can be followed by the permanent matrix hardening step to harden the modified matrix 156 (i.e., the permanent matrix) formed by ALD. If an optional resist material layer 47 (such as a liftoff layer) is employed, such a resist material layer 47 can be removed thereafter. Next, a second electrode 80 is deposited to form a resistive memory cell.

[0069] In one embodiment, at least 50 % (which may be more than 80 % and/or more than 90 %) of all nanoparticle cores 52 in the matrix 156 do not physically contact any other nanoparticle core 52 within the matrix 156. The inorganic matrix 156 can prevent direct contact among a predominant portion (i.e., at least 50 %) of neighboring pairs of nanoparticle cores 52.

[0070] In one embodiment, the combination of metal oxide nanoparticles 52 and inorganic matrix 156 constitute a variable resistance region 50 of barrier modulated cell (BMC). The inorganic matrix 156 forms the barrier of the BMC and acts as an oxygen scavenger or reservoir for interstitial oxygen ion diffusion into and out of the metal oxide nanoparticles 52.

[0071] For example, the inorganic matrix material 156 may be, but is not limited to, amorphous silicon, silicon oxide, tantalum oxide, and germanium. The metal oxide nanoparticles 52 comprise a metal oxide material selected from titanium oxide, hafnium oxide, zinc oxide, vanadium oxide, niobium oxide, tantalum oxide, strontium titanate and tin oxide for use in a barrier modulated cell (BMC). Examples of metal oxide materials include a slightly sub-stoichiometric metal oxide such as Τί0 ₂ -δ, SrTi03_ g, Nb0 ₂ _ g, or Nb:SrTi03_ g where value of δ can be independently selected from a range from 0 to 0.5, such as greater than zero to 0.15 (i.e., to form a sub-stoichiometric, oxygen deficient metal oxide). For example, the metal oxide material may be titanium oxide, such as sub-stoichiometric titanium oxide having less than two oxygen atoms for each titanium atom. [0072] The variable resistance region 50 provides different resistance between the first electrode 20 and the second electrode 80 depending on the state of the metal oxide nanoparticles 52 and the inorganic matrix 156. For example, an energy barrier is formed at the interface between the inorganic matrix 156 and the nanoparticles 52. The energy width and energy height of the barrier may be modulated by the diffusion of oxygen vacancies and/or interstitial oxygen ions in and out of the interface. The modulation of the energy band structure at the interface between the inorganic matrix 156 and the nanoparticles 52 can provide a change to the overall resistivity of the variable resistance region. The vacancies and/or interstitial oxygen ions may be rearranged by applying a voltage to the resistive memory cell.

[0073] In another embodiment, the resistive memory cell comprises a projected memory cell, such as the cell described in Koelmans, W. W.; Sebastian, A.; Jonnalagadda, V. P.; Krebs, D.; Dellmann, L.; Eleftheriou, E., Projected Phase-Change Memory Devices. Nature communications 2015, 6, incorporated herein by reference in its entirety. In a projected memory cell, the physical mechanism of resistance storage in a phase change memory material is decoupled from the information-retrieval process by providing a projection material between the two cell electrodes having a resistivity p _m which is between the low and high resistance states of the phase change memory material (i.e., pi < p _m < P _h where pi and p _h represent the resistivity of low resistance (i.e., crystalline state) and high resistance (e.g., amorphous state) states, respectively, of the phase change memory material). During the reading operation, the current flows through the projection material between the electrodes rather than through the phase change memory material in the high resistance state (e.g., in the amorphous state). [0074] Referring to FIGS. 7 A and 7B, a fourth exemplary resistive memory cell according to a fourth embodiment of the present disclosure is illustrated. The memory cell is a projected memory cell, includes a "projection material", i.e., a thin conformal layer of a different material with an electrical resistivity p _m . This material can be conformally coated on the sidewalls of the opening through the insulating layer 40 and on the physically exposed portion of the top surface of the first electrode 20 to form a projection material liner 254. For example, the projection material liner 254 may comprise a TiN liner for chalcogenide phase change material nanoparticles 52. The projection material liner 254 can be formed by ALD or PECVD. The projection material liner 254 deposited at the top of the first electrode 20 and on the top surface may remain as illustrated in FIG. 7A, or may be etched back by an anisotropic etch to form a cylindrical projection material liner 256 as illustrated in FIG. 7B. Then, the processing steps of the first or second embodiment can be followed to produce a nanoparticle -based resistive memory cell. The resistivity of the projection material is tuned so that the cell is more stable during reading.

[0075] Referring to FIGS. 8 A and 8B, a fifth embodiment of the present disclosure is illustrated. The projected memory cell with projection material of the fourth embodiment is used followed by the steps of the third embodiment as to produce a cell with nanoparticle cores 52 surrounded by a modified matrix 156 formed by the ALD infiltrated material.

[0076] Referring to FIGS. 9A - 9C, a sixth exemplary resistive memory cell according to a sixth embodiment of the present disclosure is illustrated. An opening is formed through an insulating layer 40 as in the first embodiment with a modification that induces formation of a constriction zone. For example, a sacrificial frustum including a sacrificial material such as polysilicon or carbon can be formed over the first electrode 20 with a thickness that is greater than the height of the sacrificial frustum. The patterning of the sacrificial frustum can be performed with a lithographic patterning of a photoresist layer and a taper- inducing etch (that includes a combination of an isotropic etch and an anisotropic etch) that employs the patterned photoresist layer as an etch mask. Another taper-inducing etch can be performed through an upper portion of the insulating layer 40 to expose a top surface of the sacrificial frustum, which is subsequently removed selective to the insulating layer 40.

[0077] The region having the smallest horizontal cross-sectional area within the opening through the insulating layer 40 is a constriction zone. Thus, the constriction zone has a horizontal cross-sectional area that is less than a horizontal cross-sectional area of a top periphery of the opening and is less than a horizontal cross-sectional area of a bottom periphery of the opening.

[0078] Subsequently, the processing steps of any of the preceding embodiments can be performed. The opening through the insulating layer 40 has a narrowing between top and first electrodes (20, 80). The narrowed dimension restricts the number of nanoparticle cores 53 that can occupy the space, thus reducing the switching volume. The constriction generates a higher current density (amps/unit area) in the constriction zone, thus increasing the temperature rise in that zone. The combination of reduced volume and higher current density will enhance phase transformation, i.e. reduced current to reset/amorphize.

[0079] Referring to FIGS. 10A and 10B, a seventh resistive memory cell according to a seventh embodiment of the present disclosure includes a barrier modulated cell (BMC). In FIG. 10A, the combination of metal oxide nanoparticles 52 and inorganic matrix 356 constitute a variable resistance region 50 of barrier modulated cell (BMC). The inorganic matrix 356 forms the barrier of the BMC and acts as an oxygen scavenger or reservoir for interstitial oxygen ion diffusion into and out of the metal oxide nanoparticles 52. The inorganic matrix 356 may be the same as the modified matrix 156 formed by infiltration atomic layer deposition (ALD) synthesis. Alternatively, the inorganic matrix 356 may be a different matrix material formed by a method other than infiltration atomic layer deposition (ALD) synthesis.

[0080] For example, the inorganic matrix material 356 may be, but is not limited to, amorphous silicon, silicon oxide, tantalum oxide, and germanium. The metal oxide nanoparticles 52 comprise a metal oxide material selected from titanium oxide, hafnium oxide, zinc oxide, vanadium oxide, niobium oxide, tantalum oxide, strontium titanate and tin oxide for use in a barrier modulated cell (BMC). Examples of metal oxide materials include a slightly sub-stoichiometric metal oxide such as Τί0 ₂ -δ, SrTi03_ g, Nb0 ₂ _ g, or Nb:SrTi03_ g where value of δ can be independently selected from a range from 0 to 0.5, such as greater than zero to 0.15 (i.e., to form a sub-stoichiometric, oxygen deficient metal oxide). For example, the metal oxide material may be titanium oxide, such as sub-stoichiometric titanium oxide having less than two oxygen atoms for each titanium atom.

[0081] Referring to FIG. 10B, multiple types of nanoparticles (52, 62) are formed in the BMC. Thus, in addition to the nanoparticles 52 (which are herein referred to as first nanoparticles) provided in the liquid dispersion 250, additional nanoparticles 62 (which are herein referred to as second nanoparticles) having a different composition than the nanoparticles 52 can be introduced into the dispensed liquid dispersion 250, and can be subsequently applied over a first electrode 20 (such as within an opening in the insulating layer 40). The additional nanoparticles 62 comprise another material that is selected from a conductive metal oxide or a semiconducting metal oxide above. In this case, an enclosed resistive memory cell with a blend of nanoparticles (52, 62) can be formed.

[0082] The two or more distinct materials that are blended at a specific molar ratio.

When each type of nanoparticles (52, 62) is relatively monodisperse within the liquid dispersion 250, regular and periodic superlattices can be obtained in the matrix (53, 156, 356) or without a matrix (e.g., in the configuration shown in FIGS. 5A-5C). In this case, each type of nanoparticle occupies specific sites on the superlattice. In this way, by tuning the mean sizes of each population in the blend and their molar fractions, it is possible to design how the superlattice will assemble inside the resistive memory cell. FIG. 10B illustrates a specific example, but other cell geometries can also be employed. Various size ratios of

nanoparticles (52, 62) and different blends of more than two types of nanoparticles (52, 62) can also be employed.

[0083] In addition, the feature of the mixture of multiple (e.g., two, three, four, etc.) types of nanoparticles (52, 62) in the seventh embodiment can be incorporated into each of the preceding exemplary resistive memory cells by substitution of the respective liquid dispersion 250.

[0084] Referring to FIG. 11, an eighth resistive memory cell according to an eighth embodiment of the present disclosure includes nanoparticles 72, which can be employed in lieu of the nanoparticle cores 52 in any of the previously described embodiments. The nanoparticle 72 can include an inner core 74 that comprises a first material, and an outer shell 76 that surrounds the inner core 74 and comprises a second material that is different from the first material. Each of the first material and the second material can be independently selected from conductive metal oxides, semiconducting metal oxides, and chalcogenide materials (such as chalcogenide phase change materials) with the proviso that the second material is different from the first material. A fully enclosed memory cell with core-shell type nanoparticles 72 is provided.

[0085] The outer shell 76 of each nanoparticle 72 surrounds the inner core 74 to add functionality to the electronic, optical and/or catalytic properties to the nanoparticle 72. In particular, the second material of the outer shell 76 can be chosen to promote the charge separation of electron-hole pairs as in a material pair. An example of such a material pair is inner nanoparticle core 74 including Ti0 ₂ and the outer nanoparticle shell 76 including Sn0 ₂ .

[0086] Optionally, blends of nanoparticles 72 with different inner core materials or different outer shell materials or both can be employed to add additional functionality. In addition, the feature of at least one type of nanoparticles 72 including a respective inner core 74 and a respective outer shell 76 in the eighth embodiment can be incorporated into each of the preceding exemplary resistive memory cells by substitution of at least one type of nanoparticles 72 of the eighth embodiment for the nanoparticles 52 of previous embodiments. For example, the nanoparticles 72 may be located in the BMC described above, in which the inner core 74 comprises the metal oxide (e.g., sub- stoichiometric titanium oxide) and the outer shell 76 comprises the barrier material, such as amorphous silicon, germanium, silicon oxide, tantalum oxide, aluminum oxide, etc.

[0087] According to a ninth embodiment of the present disclosure, nanoparticle-based memory cells can include a thin film of nanoparticle assemblies or nanocomposites. FIGS. 12A and 12B illustrate a first configuration employing only one type of nanoparticle cores 52, and FIGS. 12C and 12D illustrate a second configuration employing multiple types of nanoparticles (52, 62), which can be a blend of two or more types of nanoparticles (52, 62).

[0088] A first electrode 20 can be formed on a top surface of a substrate 10. A thin film including one monolayer of nanoparticles {52, {52, 62}, or 72} or 2 - 10 monolayers of nanoparticles {52, {52, 62}, or 72} can be formed by applying a liquid dispersion 250 directly on the top surface of the first electrode 20. A patterned insulating layer 40 may, or may not, be omitted. Correspondingly, the variable resistance region 50 can be formed as a patterned layer or as a blanket (unpatterned) layer. A second electrode 80 can be formed on the variable resistance region 50 as a blanket film. The second electrode 80, the variable resistance region 50, and/or the first electrode 20 may be subsequently patterned, for example, by application and lithographic patterning of a photoresist layer and an etch process employing the photoresist layer as an etch mask.

[0089] In one embodiment, the first electrode 20 can be formed as a planar layer over the substrate 10, and a matrix derived from a liquid dispersion 250 can be formed on a top surface of the first electrode 20. In one embodiment, the thickness of the matrix formed from the liquid dispersion 250 can be less than twice the maximum dimension of the ligand-grafted nanoparticles (51, 52). In this case, the thickness of the variable resistance region 50 can be less than twice the maximum dimension of a nanoparticle 52. The second electrode 80 can be formed on the variable resistance region 50.

[0090] Referring to FIG. 13, a tenth exemplary memory cell according to a tenth embodiment of the present disclosure is illustrated. An alternating stack of insulating layers (e.g., silicon oxide) 240 and electrically conductive layers (e.g., TiN and/or W) 220 can be formed over a substrate 210. The substrate 210 may comprise a silicon substrate that includes an overlying insulating material such as silicon oxide, glass, a dielectric metal oxide, and/or silicon nitride. Each of the insulating layers 240 and each of the electrically conductive layer 220 can have a respective thickness in a range from 10 nm to 1,000 nm. At least one opening is formed by patterning the alternating stack of insulating layers 240 and the electrically conductive layers 220. The shape of an opening may be in the shape of a line trench, in which case the remaining portions of the alternating stack of insulating layers 240 and electrically conductive layers 220 can be in the shape of strips that laterally extend along a common horizontal direction, and laterally spaced apart among one another along another horizontal direction. Alternatively, the shape of the opening may be circular or elliptical, in which case the remaining portions of the alternating stack of insulating layers 240 and electrically conductive layers 220 can have an annular shape with a cavity having a circular or elliptical horizontal cross-sectional shape therethrough.

[0091] A sidewall of each electrically conductive layer 220 (i.e., the first electrodes, such as word lines of a ReRAM device) is physically exposed in the opening. Each of the remaining portions of the electrically conductive layers 240 constitutes a first electrode. Thus, a plurality of first electrodes can be provided. The liquid dispersion 250 of any of the previous embodiments can be formed in the opening and directly on the sidewall of the first electrodes. In other words, the processing steps of the previous embodiments can be performed to form a variable resistance region 50 within the opening. An insulating cap layer 290 can be formed over the variable resistance region 50. A second electrode 280 (e.g., a local vertical bit line) can be formed through the variable resistance region 50, for example, at a center portion of the opening. A contact structure (e.g., a global bit line) 282 can be optionally formed on the top surface of the second electrode 280. Alternatively, the contact structure (e.g., global bit line) 282 may be located between the alternating stack and the substrate 210, and each of the second electrodes (e.g., local vertical bit lines) 280 may extend upwards from the contact structure 282 into the alternating stack. [0092] The nanoparticle assemblies of the present disclosure can be employed to form a three-dimensional resistive memory cell employing the methods of the tenth embodiment. Nanoparticles embedded in a matrix (53, 156, 356) or not embedded in a matrix can be used to fill deep trenches of a three-dimensional memory device. Any of the materials and/or configurations of the previous embodiments can be employed.

[0093] Examples of the atomic layer deposition infiltration process that can be employed in various embodiments of the present disclosure are described herein. As discussed above, the atomic layer deposition infiltration process can be employed to induce infiltration of a precursor material into materials of a film derived from the liquid dispersion 250 such that the precursor material forms the matrix upon reaction with, or substitution of, a material in the ligand-grafted nanoparticles, such as by a ligand exchange process.

[0094] In a non-limiting illustrative example, nanoparticles (51, 52) can be synthesized with tethered short ligand molecules (e.g. functionalized alkyl chains) that act as stabilizers for the nanoparticles in liquid dispersions. In another illustrative example, the ligands may be exchanged and replaced by longer polymeric ligands that may facilitate processing or add functionality or make it easier for the nanoparticles to blend in polymeric composites.

Alternatively, the original short ligands may be exchanged for inorganic ligands to tune the optoelectronic properties of the nanoparticles.

[0095] FIGS. 14A - 14E illustrate an exemplary sequence of processing steps that can be employed to form any of the third through twelfth exemplary structures of the present disclosure. Nanoparticles (51, 52) with suitable ligands 51 are prepared as illustrated in FIG. 14A.

[0096] As shown in FIG. 14B, a liquid dispersion 250 is prepared, and is applied on a surface of at least one first electrode 20 by spin-coating, dip-coating, drop-casting, inkjet printing, or spraying. Liquid interfaces such as Langmuir-Blodgett films may also be employed to apply the liquid dispersion 250. The liquid dispersion 250 including the ligand- grafted nanoparticles (51, 52) may be deposited into openings, cavities, or wells, or as a thin film as described above. While FIG. 14B illustrates a configuration in which the liquid dispersion 250 is applied as a thin film, any other geometry that can support initial formation of a matrix 53 can be employed. The applied liquid dispersion 250 is optionally converted into a matrix 53, for example, by polymerization of the ligands 51. Optionally, the matrix 53 may be annealed at an elevated temperature, or may be otherwise cured (for example, by exposure to ultraviolet irradiation and/or by evaporation of solvents).

[0097] Referring to FIG. 14C, the in-process resistive memory cell can be introduced into an atomic layer deposition (ALD) process chamber, and can be exposed to a chemical vapor precursor material 155.

[0098] Referring to FIG. 14D, the matrix material of the modified matrix 156 is synthesized by the interaction of the precursor material 155 and a material within the initial matrix 53 or within the nanoparticles 52. The ligands 51 may be specifically designed to be inert to the precursor material 155, or to react with the precursor material 155, or to detach from the nanoparticles 52 to be substituted by the precursor material 155 that coats the surfaces of the nanoparticles 52.

[0099] In one embodiment, a modified matrix material can be grown by ALD by using a ligand 51 that binds to one of the ALD precursor materials 155. In this case, the modified matrix material of the modified matrix 156 grows over the network of ligand chains derived from the ligands 51. This process may be achieved for example, if the ligand 51 is polymethyl methacrylate (PMMA) and the precursor material 155 is trimethyl aluminum (TMA), which is used for synthesis of aluminum oxide. In this example, TMA selectively binds to the carbonyl groups of PMMA. After the modified matrix material is grown to form the modified matrix 156 using several cycles of ALD synthesis, the unreacted ligands 51 may be optionally removed by a suitable method (such as thermal decomposition,

photodecomposition, reactive ion etch, wet etch, etc). A variable resistance region 50 of a BMC is formed in which the aluminum oxide barrier surrounds the titanium oxide nanoparticles. Referring to FIG. 14E, a second electrode 80 can be deposited on top of the variable resistance region 50.

[0100] In one embodiment, a core-shell nanoparticle of FIG. 11 may be employed in lieu of the nanoparticles described above. A core-shell nanoparticle includes a nanoparticle core and a nanoparticle shell that surrounds the nanoparticle core. The nanoparticle shell can be synthesized around the nanoparticle core during the chemical synthesis of a core- shell nanoparticle. The ligands 51 can be attached to the nanoparticle shell. In one embodiment, the processing steps FIGS. 14B - 14E can be employed to form a variable resistance region 50.

[0101] Alternatively, a new shell material can be formed employing atomic layer deposition after formation of an initial ligands 51 or matrix 53 employing the methods illustrated in FIGS. 15A - 15F. Referring to FIGS. 15 A, a film of ligand-grafted

nanoparticles (51, 52) is deposited on a first electrode 20 over a substrate 10. Each of the ligand-grafted nanoparticles (51, 52) includes a nanoparticle 52 and a ligand 51 attached to the nanoparticle 52. The ligand 51, polymeric or otherwise, is chosen such that the ligand 51 is inert to the ALD precursors used to grow the shell material. [0102] Referring to FIG. 15B, the initial matrix 53 (e.g., ligands 51 attached to nanoparticles 51) is exposed to a first ALD precursor material 255, which interacts with an outer portion of each nanoparticle 52. The first ALD precursor material 255 is selected are such that the first ALD precursor material 255 does not react with the material of the ligands 51 (which comprise the initial matrix 53 at this processing step), but reacts with the material of the nanoparticles 52 to form nanoparticle shells 57 as illustrated in FIG. 15C. The number of cycles of the ALD infiltration process and the size of the nanoparticles 52 are selected such that an inner portion of each nanoparticle 52 remains unchanged, while an outer portion of each nanoparticle 52 is converted into a nanoparticle shell 57.

[0103] Referring to FIG. 15D, the initial matrix 53 is exposed to a second ALD precursor material 155. The matrix material of the modified matrix 156 is grown in the spaces between the remaining nanoparticles 52 as illustrated in FIG. 15E. Unreacted portions of the ligands 51 can be optionally removed, for example, by thermal decomposition, photodecomposition, or an etch process (which may include a dry etch process or a wet etch process). A variable resistance region 50 of a BMC is thereby formed in which the inorganic modified matrix 156 forms the barrier material around the metal oxide nanoparticles 52. A second electrode 80 can be formed on the variable resistance region 50.

[0104] The various embodiments of the present disclosure provide barrier modulated cell comprising: a first electrode (20, 220) comprising a conductive material and located on a substrate (10, 210); a variable resistance region 50 including metal oxide nanoparticles (52, 62, 72) and a barrier material (76, 156, 356) in contact with the metal oxide nanoparticles, and a second electrode (80, 280.).

[0105] The barrier material can be selected from amorphous silicon, germanium, silicon oxide, tantalum oxide, and aluminum oxide, and the metal oxide nanoparticles comprise titanium oxide, hafnium oxide, zinc oxide, vanadium oxide, niobium oxide, tantalum oxide, strontium titanate or tin oxide.

[0106] In one embodiment, the barrier material comprises an inorganic matrix (156, 356) embedding the metal oxide nanoparticles. In another embodiment, the barrier material comprises inorganic shells 76 surrounding the nanoparticles (e.g., the nanoparticle cores 74).

[0107] Additional embodiments of the present disclosure provide a projected memory cell, comprising a first electrode (20, 220), a second electrode (80, 280), and a variable resistance region 50 located between the first and the second electrodes. The variable resistance region comprising chalcogenide phase change memory material nanoparticles (52, 62, 72) and a projection material liner (254, 256) that connects the first electrode to the second electrode. The projection material liner has a resistivity which is between low and high resistance states of the chalcogenide phase change memory material.

[0108] In one embodiment, the variable resistance region 50 is located in an opening 39 in an insulating layer 40 located between the first and the second electrodes. The projection material liner surrounds the chalcogenide phase change memory material nanoparticles in the opening.

[0109] Most commonly, the interface(s) responsible for the switching mechanism in a prior art ReRAM cell can be engineered in a two-dimensional fashion such that the interface(s) is /are parallel to an electrode or electrodes. This configuration limits the ratio of the active interface(s) to the total footprint of the memory cell (i.e., the area of the memory cell in a plan view along a direction perpendicular to a top surface of a substrate on which the memory cell is formed). The prior art interface or interfaces are commonly formed by stacking thin films on top of each other, which constrains the design of the interface to a single-type of interface across the device. Thus, it is not possible to change the material or materials along the interface. The various structures of the present disclosure provide resistance-switching interfaces that are not limited by contact areas between two intersecting conductive structures such as bit lines and word lines. As such, the various structures of the present disclosure can be employed to form high density resistive memory devices such as a three-dimensional array of resistive memory devices.

[0110] Although the foregoing refers to particular embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such

modifications are intended to be within the scope of the disclosure. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.