Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
NETWORK DEVICES FOR SEPARATING POWER AND DATA SIGNALS
Document Type and Number:
WIPO Patent Application WO/2007/121148
Kind Code:
A3
Abstract:
Embodiments disclosed herein provide a network device comprises a transformer with a primary winding and a secondary winding. The primary winding is coupled to receive input signals from a network connector and supply data signals to a physical layer (PHY) module. An inductance boost circuit is coupled to the secondary winding and operable to increase the impedance of the primary winding. In other embodiments, a network device comprises an autotransformer coupled to receive input signals from a network connector and supply data signals to a physical layer (PHY) module. An electronic load coupled in parallel between the autotransformer and the PHY layer module.

Inventors:
CAMAGNA, John R. (4069 Bancroft Drive, El Dorado Hills, California, 95762, US)
CRAWLEY, Philip (10 Datoro Ct, Sacramento, California, 95833, US)
GATTANI, Amit (324 Toscano Ct, Roseville, California, 95661, US)
GHOSHAL, Sajol (3343 Kensington Drive, El Dorado Hills, California, 95762, US)
Application Number:
US2007/066270
Publication Date:
July 24, 2008
Filing Date:
April 09, 2007
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
AKROS SILICON, INC. (275 Turn Pike Drive, Folsom, California, 95630, US)
CAMAGNA, John R. (4069 Bancroft Drive, El Dorado Hills, California, 95762, US)
CRAWLEY, Philip (10 Datoro Ct, Sacramento, California, 95833, US)
GATTANI, Amit (324 Toscano Ct, Roseville, California, 95661, US)
GHOSHAL, Sajol (3343 Kensington Drive, El Dorado Hills, California, 95762, US)
International Classes:
H04B3/26
Attorney, Agent or Firm:
KOESTNER BERTANI LLP et al. (18662 Macarthur Blvd, Suite 400Irvine, California, 92612, US)
Download PDF:
Claims:
WHAT iS CLAIMED ϊS:

1. A network device comprising: a transformer with a primary winding and a secondary winding, wherein the primary winding is coupled to receive input signals from a network connector and supply data signals to a physical layer (PHY) moduie; and an inductance boost circuit coupled to the secondary winding and operable to increase the impedance of the primary winding.

2. A network device comprising; an aυtotraπsformer coupled to receive input signals from a network connector and supply data signals to a physical layer (PHY) module; and an electronic ioad coupled in parallel between the autotransformer and the PHY iayer module.

3. The network device according to Claim 1 or Claim 2 further comprising; a first capacitor coupled between a first lead of the transformer or autotransformer and the PHY module; and a second capacitor coupled between a second lead of the transformer or autotransformer and the PHY module.

4. The network device according to Claim 1 further comprising: an electronic ioad circuit coupled in parailel between the transformer and the PHY layer module.

5. The network device according to Claim 1 wherein; the inductance boost circuit senses the current through the secondary winding and applies a gain factor to increase the impedance at the primary winding. 8. The network device according to Claim S wherein: the impedance at the primary winding is directly proportional to the frequency of the input signal, the inductance of the primary winding, and inversely proportional to the factor (1 - α).

7. The network device according to Claim 1 or Claim 2 further comprising. a rectifying circuit adapted to conductively couple a network connector to an integrated circuit that rectifies and passes a power signal received from the network connector.

8. The network device according to Claim 7 wherein. the rectifying circuit regulates a received power and/or data signal to ensure proper signal polarity is applied to the integrated circuit.

9. The network device according to Ciaϊm 7 wherein: the network connector receives a plurality of twisted pair conductors; and any one of a subset of the twisted pair conductors can forward bias to deliver current and the rectifying circuit can forward bias a return current path via remaining conductors of the subset.

10. The network device according to Claim 7 wherein the rectifying circuit includes a diode bridge,

11. The network device according to Claim 7 wherein the rectifying circuit includes a transistor bridge integrated onto the integrated circuit. 12. The network device according to Claim 11 wherein: the transistor bridge transistors are selected from a group consisting of metal oxide semiconductor (MOS) transistors, bipoiar Junction transistors (BJT) 1 junction fieid effect transistors (JFET), switchable devices, and impedance contro! devices. 13. The network device according to Claim 11 further comprising: a center tap coupied to the transformer, the center tap configured to separate the power signai from the data signal; and the transistor bridge coupled to the center tap of the transformer and configured to regulate the power signal. 14. The network device according to Ciaim 2 or Claim 4 wherein: the electronic ioad circuit is operable to provide common-mode output voltage contra! and a current source to the PHY layer module,

15. The network device according to Claim 11 wherein: the inductance boost circuit is configured to stop functioning during an over- voltage event due to high current saturation of the transformer.

16. A method comprising: coupling an inductance boost circuit coupied to a secondary winding of a transformer, wherein a primary winding of the transformer is operable to receive input signals from a network connector and supply data signals to a physicai layer (PHY) moduie, and the inductance boost circuit is configured to stop functioning during an over-voitage event due to high currents saturation of the transformer.

17. The method according to Claim 16 further comprising: coupling a first capacitor between a first lead of the transformer and the PHY module; and

coupling a second capacitor between a second lead of the transformer and the PHY module.

18. The method according to Claim 16 further comprising; coupling an electronic load circuit in parallel between the transformer and the PHY layer module.

19. The method according to Claim 16 further comprising: configuring the inductance boost circuit to sense the current through the secondary winding and apply a gain factor to increase the impedance at the primary winding. 20. The method according to Claim 19 wherein: the impedance at the primary winding is directly proportional to the frequency of the input signal, the inductance of the primary winding, and inversely proportional to the factor (1 - α),

21. The method according to Claim 16 further comprising; coupling a rectifying circuit between a network connector and an integrated circuit that rectifies and passes a power signal received from the network connector.

22. A network device comprising; a power potential rectifier adapted to conductively couple a network connector to an integrated circuit that rectifies and passes a power signal and data signal received from the network connector, the power potential rectifier that regulates a received power and/or data signal to ensure proper signal polarity is applied to the integrated circuit.

23. A network communication apparatus comprising; a transistor bridge configured for integration into an integrated circuit and adapted to regulate a power and/or data signal to ensure proper signal polarity is applied to the integrated circuit.

24. A network communication apparatus comprising: a metal oxide semiconductor (IViOS) bridge configured for integration into an integrated circuit and adapted to regulate a power and/or data signal to ensure proper signal polarity is applied to the integrated circuit.

25. The network device according to Claim 22 wherein: the power potential rectifier is configured to couple directly to Sines of the network connector and regulate the power signal whereby the power

potential rectifier passes the data signal with substantially no degradation.

26. The network device according to CSaim 22 wherein: the network connector receives a plurality of twisted pair conductors; and any one of a subset of the twisted pair conductors can forward bias to deliver current and the power potential rectifier can forward bias a return current path via a remaining conductor of the subset.

27. The network device according to Claim 22 further comprising: at least one transformer coupled across iine pairs of the network connector comprising a coil and a center tap coupled to the coil, the center tapping configured to separate the power signal from the data signal; and the power potential rectifier coupled to the center tap of the at least one transformer and configured to regulate the power signal.

28. The network device according to Claim 22 further comprising. a power rectifying diode bridge integrated onto the integrated circuit.

29. The network device according to Claim 22 further comprising: a transistor bridge integrated onto the Integrated circuit that rectifies and passes a power signal and data signal received from the network connector.

30. The network device according to CSaim 23 or Ciaim 29 wherein; the transistor bridge couples directly to lines of the network connector and regulates the power signal whereby the transistor bridge passes the data signal with substantially no degradation.

31. The network device according to CSaim 23 or Ciairm 29 further comprising: the transistor bridge transistors being selected from a group consisting of metal oxide semiconductor (MOS) transistors, bipolar junction transistors (BJT), junction field effect transistors (JFET), switchabie devices, and impedance control devices,

32. The network device according to Claim 22 further comprising: a metal oxide semiconductor (MOS) bridge integrated onto the integrated circuit that rectifies and passes a power signal and data signal received from the network connector.

33. The network device according to Claim 24 or CSaim 32 further comprising: at least one transformer coupled across Sine pairs of the network connector comprising a coi! and a center tap coupled to the coil, the center tapping configured to separate the power signal from the data signal; and the MOS bridge coupled to the center tap of the at least one transformer and configured to regulate the power signal.

34. The network device according to Claim 24 or Claim 32 further comprising: the metal oxide semiconductor (MOS) bridge comprising N-channβi metal oxide semiconductor (NMOS) transistors and P-channei metal oxide semiconductor (PMGS) transistors connected in a bridge configuration that emulates a diode bridge whereby pairs of NMOS transistors replace diodes that connect to ground and pairs of PMOS transistors replace diodes that connect to a power Sine.

35. The network device according to Claim 22 or CSaim 24 further comprising- a T connect element and an Ethernet physical layer (PHY) module integrated into the integrated circuit, the T connect element being adapted to enable ground potential of the Ethernet PHY module to float relative to earth ground; and a metal oxide semiconductor (MOS) bridge integrated onto the integrated circuit and coupled to the T connect element.

36. The network device according to Claim 22 further comprising: a transistor bridge integrated onto the integrated circuit, the transistor bridge comprising transistors configured to enable relatively ϊarge drain-source voltage V da and relatively small gate-source voltage V as .

37. The network device according to Claim 36 further comprising: the transistor bridge comprising a plurality of lateral double-diffused metal oxide semiconductor (LDϊVSOS) transistors configured to enable relatively large drain-source voltage V fJa and relatively small gate-source voltage V θS .

38. The network device according to Claim 38 further comprising: the transistor bridge comprising a plurality of metal oxide semiconductor field- effect transistors (MOSFETs), the individual MOSFETs coupled to a limiter configured to maintain an essentially constant gate-source

voltage V gs across the MOSFET at approximately a process limit whereby resistance is minimized or reduced.

39. The network device according to Claim 36 further comprising; the transistor bridge comprising a plurality of metai oxide semiconductor fieid- effect transistors (Sv]QSFETs), the individual MOSFETs coupled to a limit and disable circuit configured to maintain an essentially constant gate- source voltage V gs across the fvtQSFET at approximately a process limit whereby resistance is minimized or reduced, and to disable transistor bridge devices on opposing power iines whereby gates of a IvIOSFET bridge are turned off for iines that are not powered.

40. The network device according to Claim 22 further comprising; an integrated diode bridge integrated onto the integrated circuit and coupled directiy to lines of the network connector, the integrated dtode bridge comprising an input side and an output side, the input side coupled to the network connector iines and the output side coupled to at least one power line and at least one ground line.

41. The network device according to Claim 22 further comprising; a T connect element and an Ethernet physicai layer (PHY) module integrated into the integrated circuit, the T connect element adapted to enable ground potential of the Ethernet PHY module to float relative to earth ground; and an integrated diode bridge integrated onto the integrated circuit and coupitng individual lines of the network connector through an integrated diode into T connect elements. 42. The apparatus according to Claim 24 further comprising; the metai oxide semiconductor (MOS) bridge comprising N-channei metal oxide semiconductor {NMOS} transistors and P-channei metal oxide semiconductor (PfvtQS) transistors connected in a bridge configuration that emulates a diode bridge whereby pairs of NMOS transistors replace diodes that connect to ground and pairs of PMOS transistors replace diodes that connect to a power line. 43, A network device comprising; an interface coupled between an Ethernet physical layer (PHY) module and a network connector, the interface comprising at least one pair of pins coupled to output connections of the Ethernet physical layer (PHY), a

direct current (DC) blocking capacitor coupled to each pin, and a common-mode suppression amplifier coupled between the paired pins configured to suppress common-mode noise by forming a low impedance path from the Ethernet PHY output to ground. 44, A network device comprising; an interface coupled between an Ethernet physical layer (PHY) module and a network connector operative at a voltage substantially higher than the PHY module, the interface configured to pass signals from a relatively high voltage technology at the network connector to a relatively low voitagβ technology at the PHY module, the interface adapted to sense common-mode noise in a high voltage technology region adjacent to the network connector, the high voltage technology region comprising a common-mode suppression amplifier adapted to suppress the common- mode noise in a low voltage technology region adjacent to the PHY module whereby signals are passed to the common-mode suppression amplifier through a capacitor fabricated on a high-voltage die.

45. The network device according to Claim 44 further comprising; the iow voitagβ technology region comprising an integrated circuit configured in fine-Sine geometries, 46. The network device according to Claim 44 further comprising; a common-mode suppression amplifier fabricated in the low voltage technology region and adapted to suppress the common-mode noise.

47. The network device according to Claim 44 further comprising. the interface comprising at least one pair of pins coupled to output connections of the Ethernet physical layer (PHY) and a common-mode suppression amplifier coupled between the paired pins.

48. The network device according to Ciaim 43 further comprising- the common-mode suppression amplifier coupled to the paired pins between the DC blocking capacitors and the Ethernet physical layer (PHY) output connections.

49. The network device according to Claim 43 further comprising. the DC blocking capacitors coupled to the paired pins between the Ethernet physical layer (PHY) output connections and the common-mode suppression amplifier.

50. The network device according to Claim 43 or Claim 47 further comprising: a control device coupled to the common-mode suppression amplifier and the

Ethernet physical iayer (PHY) that controls the common-mode suppression amplifier to enable the Ethernet physical layer (PHY) to set a direct current (DC) value of common-mode voltage and suppress high- frequency common-mode signal components on the paired pins,

51. The network device according to Claim 43 or CSairn 4? further comprising: a control device coupied to the common-mode suppression amplifier and the

Ethernet physical iayer (PHY) that samples common-mode voltage at the Ethernet physical layer (PHY) output connections at regular intervals and adjusts input to the common-mode suppression amplifier to approximate the common-mode voltage. 52. The network device according to Claim 43 further comprising: a control device direct-current (dc)-coupied to the Ethernet physical layer (PHY) that adjusts a control signal to the common-mode suppression amplifier and is adapted to adjust common-mode of the common-mode amplifier at an amplitude that avoids overdriving. 53. The network device according to Ciaim 43 further comprising: a control device aitemating-current (ac)~coup!ed to the Ethernet physical layer (PHY) that adjusts a control signal to the common-mode suppression amplifier and is adapted to suppress common-mode noise.

54. The network device according to Claim 43 further comprising: a control device coupied to the Ethernet physical iayer (PHY) that sets a common-mode direct current (dc) voltage and suppresses common- mode noise above a designated frequency.

55. The network device according to Claim 43 further comprising: the common-mode suppression amplifier is separated from an integrated circuit containing the Ethernet physical layer (PHY).

56. The network device according to Claim 43 further comprising. the interface coupled between the Ethernet physical layer (PHY) module, the network connector, and a T connect integrated circuit.

57. The netwonX device according to Claim 43 further comprising: the common-mode suppression amplifier comprising a bandpass filter.

58. The network device according to Ciaϊm 43 further comprising; the common-mode suppression amplifier comprising a iowpass filter.

59. The network device according to CSaim 43 further comprising; the paired pins coupied to the interface in a configuration adapted to sense common-mode noise at input terminals to the network connector.

80. A network device comprising: an interface coupled between an Ethernet physical layer (PHY) module and a network connector operative at a voltage substantially higher than the PHY module, the interface configured to pass signais from a relatively high voitage technology at the network connector to a relatively iow voltage technology at the PHY module, the interface adapted to sense common-mode noise in a high voltage technology region adjacent to the network connector and adapted to suppress the common-mode noise in a low voitage technology region adjacent to the PHY module by forming a low impedance path from the PHY output to ground.

61. A method of operating a network device comprising; passing signals from a relatively high voitage technology at a network connector to a relatively iow voltage technology at an Ethernet physical layer (PHY) module; sensing common-mode noise in a high voitage technology region adjacent to the network connector; and suppressing the common-mode noise in a low voitage technology region adjacent to the PHY module by forming a iow impedance path from the Ethernet PHY output to ground. 62. The method according to Claim 61 further comprising: fabricating a common-mode suppression ampiifier in the low voltage technology region; and suppressing the common-mode noise using the common-mode suppression ampiifier. 63, The method according to Claim 61 further comprising: controlling common-mode suppression to enable the Ethernet physical layer (PHY) to set a direct current (DC) value of common-mode voitage and suppress high-frequency common-mode signal components.

64. The method according to Claim 61 further comprising: sampling common-mode voitagβ at regular intervals; and adjusting common-mode suppression to approximate the common-mode voltage. 85, The method according to Ciaim 61 further comprising: setting common-mode direct current (dc) voitage; and suppressing common-mode noise above a designated frequency.

66. The method according to Claim 61 further comprising: sensing common-mode noise at input terminals to the network connector. 67. A network device comprising: a network connector adapted to physicaily couple the network device to a network and receive both a power signal and a data signal through the coupled network; an integrated circuit coupled to the network connector and comprising at least one functional element the at least one functional element comprising an Ethernet physical layer (PHY) module; and an interface coupled between the integrated circuit and the network connector and configured to pass signals from a relatively high voitage technology at the network connector to a relatively low voltage technology at the integrated circuit, the interface adapted to sense common-mode noise at the network connector and adapted to suppress the common-mode noise in the integrated circuit by forming a low impedance path from the Ethernet PHY output to ground.

68, The network device according to Claim 67 further comprising: the interface comprising at least one pair of pins coupled to output connections of the Ethernet physical layer (PHY), a direct current (DC) blocking capacitor coupled to each pin. and a common-mode suppression amplifier coupled between the paired pins.

89. The network device according to Claim 88 further comprising: a control device coupled to the common-mode suppression amplifier and the

Ethernet physical layer (PHY) that controls the common-mode suppression amplifier to enable the Ethernet physical layer {PHY} to set a direct current (DC) value of common-mode voltage and suppress high- frequency common-mode signal components on the paired pins.

70, A network device comprising: an active common mode suppression circuit coupled in parallel to transmit and receive differential signal lines connecting an Ethernet physical layer

(PHY) module and a network connector. 71. The network device according to Claim 70 further comprising; the active common mode suppression circuit configured to absorb common mode noise by forming a low impedance path from the PHY module output to a ground.

72, The network device according to Claim 70 wherein; the PHY module has a Class A driver whereby output common mode ievei of the

PHY module can vary up to V C c-

73. The network device according to Claim 70 further comprising- the active common mode suppression circuit configured to terminate common mode impedance over the Ethernet signal frequency range. 74. The network device according to Claim 70 further comprising: the active common mode suppression circuit configured to terminate common mode impedance over an Ethernet signal frequency range whereby the active common mode suppression circuit forms a loop that creates a second-order roll-off in common mode noise suppression at frequencies above 1OkHz.

75. The network device according to Claim 70 further comprising; the active common mode suppression circuit configured in a Class A architecture that matches Ethernet PHY Sine drivers whereby the Ethernet PHY controls output line signa! common mode direct current (DC) voitage, 76. The network device according to Claim 70 further comprising. the active common mode suppression circuit and the Ethernet PHY formed in a same fabrication process and voltage.

77. The network device according to Claim 70 further comprising: the active common mode suppression circuit comprises a two-stage amplifier gain loop whereby common mode noise is suppressed by at least 4OdB from 10OkHz to 30 MHs.

78. The network device according to Claim 70 further compnsing: the active common mode suppression circuit comprises a CSass A output stage coupled between the Ethernet PHY and a first stage preamplifier, the first stage preamplifier and the CSass A output stage forming a two-stage amplifier gain ioop : the first stage preamplifier being capacitively-coupled at input and output terminals.

79, The network device according to Claim 70 further comprising: the active common mode suppression circuit comprises a Ciass A output stage coupled between the Ethernet PHY and a first stage preamplifier, the first stage preamplifier and the Ciass A output stage forming a fevo-stage amplifier gain loop, the first stage preamplifier forming a preamplifier loop with signai and bias controlled at a common input node.

80, The network device according to Claim 70 further comprising: the active common mode suppression circuit comprises a two-stage amplifier gain ioop, a preamplifier loop coupled to the two-stage amplifier gain loop, a low frequency bias loop coupled to the preamplifier loop, a DC filter coupled to the low frequency bias loop, and common mode sampling capacitors coupled from an input terminal to the preamplifier loop to transmit and receive data (TRD+/-) Sines to the Ethernet PHY, the DC filter and the common mode sampling capacitors being configured to set iow frequency bias ioop bandwidth.

81 , The network device according to Claim 80 further comprising. the active common mode suppression circuit is configured to transition from direct current (DC) control to aiternating current (AC) control at a sufficiently low frequency that AC performance begins at approximately 1OkHz. 82. The network device according to Claim 80 further comprising- the DC filter is configured to create resonance in a common mode suppression transfer function in a range approximately between 10OkHz and 30MHz whereby common mode noise is suppressed by at ieast approximately 4OdB and conductive emissions are reduced in a band approximately between 10OkHz and 30MHz.

83, The network device according to Claim 80 further comprising: a Class A output stage coupied between the Ethernet PHY and the preamplifier loop; a first node coupled to an input terminal to the preamplifier loop and to transmit and receive data (TRD+/-) iines to the Ethernet PHY; a second node coupled to an output termina! to the preamplifier loop; and a third node coupled to an input terminal to the Class A output stage, the first, second, and third nodes configured to set DC bias independently.

84, The network device according to Claim 80 further comprising: a Class A output stage coupied between the Ethernet PHY and the preamplifier loop; and

an output stage bias loop coupled between the preamplifier loop and the Ciass A output stage configured to set DC current bias in the Class A output stage.

85. The network device according to Claim 80 further comprising- a Class A output stage coupled between the Ethernet PHY and the preamplifier loop and configured with separate DC bias and AC signal paths for output bias control; and the preamplifier loop configured with an AC~coupied output terminal.

86. The network device according to CSairn 80 further comprising: a Ciass A output stage coupled between the Ethernet PHY and the preampϋfier loop; and loop compensation capacitors coupled to the Class A output stage whereby loading is reduced at the transmit and receive data (TRD+/-) itnes.

87. The network device according to Claim 80 further comprising; a Ciass A output stage coupled between the Ethernet PHY and the preamplifier loop, the output stage configured to roil-off at frequency bands that the preamplifier loop remains at high gain.

88. The network device according to Ciaim 80 further comprising: a Ciass A output stage coupled between the Ethernet PHY and the preamplifier loop, the output stage configured with a selected Unity Gain Bandwidth

(UGBW) and the preamplifier ioop configured with a UGBW at approximately four times the output stage UGBW whereby the output stage rolis-off at frequency bands that the preampϋfier loop remains at high gain. 89. The network device according to Ciaim 80 further comprising. a Ciass A output stage coupled between the Ethernet PHY and the preamplifier ioop; and an output stage gate reference node coupled to the Class A output stage and configured as software programmable to accommodate signal swings to a Vcc range in 1QBase-T, 100Base-T, and 1000Base-T designs with variable output DC control.

90. The network device according to Ciaim 80 further compnsing: the low frequency bias ioop configured to set both input and output common mode voltage of the preamplifier loop whereby input common mode control is set by a sum of preamplifier gain and Sow frequency bias loop gain and output common mode control is set by low frequency bias ioop gain.

91 A network device comprising: an interface coupled in parallel to transmit and receive differential signal lines connecting an Ethernet physical layer (PHY) module and a network connector operative at a voltage substantially higher than the PHY module, the interface comprising a two-stage amplifier gain loop whereby common mode noise is suppressed by at least 4OdB from 10OkHz to 30 MHz 1 the two-stage amplifier gain loop comprising a Class A output stage coupled between the Ethernet PHY and a first stage preamplifier that is capacitiveiy-coupied at input and output terminals. 92. A network device comprising; an interface coupled in parallel to transmit and receive differentia! signal lines connecting an Ethernet physical layer (PHY) module and a network connector operative at a voltage substantially higher than the PHY module, the interface comprising a two-stage amplifier gain loop, a preamplifier loop coupled to the two- stage amplifier gain loop, a low frequency bias loop coupled to the preamplifier loop, a DC filter coupled to the Sow frequency bias loop, and common mode sampling capacitors coupied from an input terminal to the preamplifier loop to transmit and receive data (TRD+/-) lines to the Ethernet PHY, the DC filter and the common mode sampling capacitors being configured to set low frequency bias bandwidth,

93. A network device comprising; an interface coupled in parallel to transmit and receive differential signal lines connecting an Ethernet physical layer (PHY) module and a network connector operative at a voltage substantially higher than the PHY module, the interface comprising a preamplifier, a Class A output stage coupied between the Ethernet PHY and the preamplifier, a low frequency bias loop coupled to the preamplifier, and a DC filter coupled to the low frequency bias loop, the preamplifier being capacitiveiy-coupled at input and output terminals,

94. A method of operating a network device comprising: passing signals from a relatively high voltage technology at a network connector to a relatively low voltage technology at an Ethernet physical layer (PHY) moduie; forming a low impedance pathway from an output terminal of the PHY module to ground that absorbs a common mode noise portion of the signals while enabling a differential portion of the signals to pass; and

suppressing common mode noise using a two-stage amplifier gain ioop.

95. The method according to Claim 94 further comprising: applying a second order roll-off in a range from approximately 1OkHz to 10OkHz; and suppressing the common mode noise by at least 4OdB in a range from approximateiy 10OkHz to 30MHz and by 3OdB in a range from 30MHz to 100MHz.

96. A power source equipment (PSE) network device operable to distribute both a network power signal and a network data signai through a coupied network, comprising: a network connector operable to physically coupie the PSE network device to the network; an integrated circuit (IC) coupled to the network connector that further comprises a power feed circuit, wherein the power feed circuit is operable to; exchange data signals with a network physical layer (PHY) module,

Ethernet switch, and the network connector; suppress common-mode noise by forming a Sow impedance path from the

PHY output to ground; and balance the network power signai as directed by a power source equipment (PSE) controlier, wherein the network power signal comprises a plurality of power signals drawn from an isoiated power supply.

97. A power source equipment (PSE) network device operable to distribute both an Ethernet power signal and an Ethernet data signai through a coupied Ethernet network, comprising: an Ethernet network connector operable to physically couple the PSE network device to the Ethernet network; a PSE controller: and an Ethernet physical layer (PHY) module operable to interface the PSE network device to a multiport switch; and an integrated circuit (IC) coupled to the Ethernet network connector that further comprises a power feed circuit, wherein the power feed circuit is operable to; exchange Ethernet data signals with the Ethernet PHY module and the

Ethernet connector: and coupie to a power supply; draw a plurality of power signals from the power supply;

sense a current associated with each power signal of the plurality of power signals; suppress common-mode noise by forming a Sow impedance path from the

Ethernet PHY output to ground; balance the plurality of power signal based on the sensed current associated with each power signal of the plurality of power signals; pass the Ethernet power signal to the Ethernet connector as directed by the PSE controller, wherein the Ethernet power signal comprises the plurality of balanced power signals, and the plurality of balanced power signals comprise: a first power signal that utilizes a first pair of twisted pairs; and/or a second power signal that utilizes a second pair of twisted pairs.

98. The PSE network device of Claim 96 wherein; the PSE controller is operable to sense a current associated with each power signal of the plurality of power signals; an active control circuit balances the plurality of power signals based on the sensed current associated with each power signal of the plurality of power signals.

99. The PSE network device of Claim 96 wherein; the network power signals comprise: a first power signal that utilizes a first pair of twisted pairs; and/or a second power signal that utilizes a second pair of twisted pairs.

100. The PSE network device of Claim 99 wherein the first power signal and second power signal each do not exceed about 17 watts. 101. The PSE network device of Claim 96 wherein the received power signal does not exceed 57 volts.

102. The PSE network device of Claim 96 wherein the Ethernet PHY module is operable to implement 10Mbps, IOOMbps and/or 1 Gbps physical layer functions.

103. The PSE network device of Claim 96 wherein the IC further comprises an Ethernet media access controller (MAC) wherein the Ethernet PHY and Ethernet MAC are operable to implement hardware layers of an Ethernet protocol stack,

104. The PSE network device of Claim 96 wherein the network power signal is IEEE 802.3af compliant.

105. The PSE network device of Claim 96 or Claim 97 wherein the PSE network device is operable to determine if a network attached powered device is IEEE 802.3af compliant.

106. The PSE network device of Claim 96 or Ciaim 97 wherein the SC further comprises at least one circuit selected from the group consisting of: the PSE controller; a media processor; factory controller: a muitiport switch; an Ethernet switch; and the network PHY module

107. The PSE network device of Claim 96 wherein the power supply is a 48 volt power.

108. The PSE network device of Claim 96 wherein the PSE network device further comprises a multi-port switch operable to couple the Ethernet PHY module to an externa! network.

109. A method to supply power from a power source equipment (PSE) network device with an Ethernet power signa! fed through an Ethernet network connection, comprising: physically coupling the PSE network device to an isolated power supply, wherein an integrated circuit (IC) within the PSE network device draws a plurality of power signals from the isolated power supply: sensing a current associated with each power signal of the plurality of power signals; balancing the plurality of power signals based on the sensed current, wherein the

Ethernet power signal comprises the balanced plurality of power signal: physically coupling the PSE network device to an Ethernet network; combining with the IC. an Ethernet data signal and the Ethernet power signa! to produce an Ethernet signal; providing ground isolation for the Ethernet data signal and the Ethernet power signal; exchanging the Ethernet signa! with at ieast one Ethernet network power device (PD) physically coupled to the Ethernet network within the PSE network device; and suppressing common-mode noise by forming a low impedance path from the PD to ground.

110. The method of Ciaim 109 wherein the sensed current of each of the balanced power signals is equal

111. The method of Ciaim 109 wherein balancing the plurality of power signals results in each sensed current not exceeding a reference current

112. The method of Claim 109 wherein physically coupling the PSE network device to the Ethernet network further comprises interfacing the SC to a piuraiity of twisted pairs, wherein the plurality of twisted pairs pass the Ethernet signal,

113. The method of Ciaim 109 wherein: the Ethernet power signals comprise: a first power signal that utilizes a first pair of twisted pairs; and/or a second power signal that utilizes a second pair of twisted pairs.

114. The method of Ciaim 109 wherein the PSE network device further comprises an Ethernet PHY module operable to implement physical layer functions associated with data rates selected from the group of data rates consisting of; IGMbps, IQOMbps, iGbps, and 100bps.

115. The method of Ciaim 109 wherein the IC comprises a power feed circuit, wherein the power feed circuit is operable to: exchange data signals with a network physical layer (PHY) module, Ethernet switch, and the network connector; and balance the network power signal as directed by a power source equipment

(PSE) controller, wherein the network power signal comprises a plurality of power signals drawn from an isolated power suppiy,

1 16. The method of Ciaim 109 wherein the IC further comprises at least one circuit selected from the group consisting of. the PSE controller: a media processor; a home plug manager; factory controller; a mυltiport switch; an Ethernet switch; and the network PHY module.

117. The method of Ciaim 109 wherein the PSE network device comprises at least one device selected from the group consisting of an Ethernet router; a controller; a content distribution controller; an Ethernet switch.

118. The method of Ciaim 109 wherein the power signal is IEEE 802.3af compliant.

119. The method of Ciaim 109 wherein the PSE network device is operable to determine if the Ethernet network PD is IEEE 802.3af compliant

120. The method of Claim 109 wherein the Ethernet network comprises at least one network selected from the group consisting of: a vehicle based network; a high speed data network; a low speed data network; a iocai-interconnect network (UN); a controller area network (CAN); a FlexRay network; a TTCAN network; a J1939 compliant network; an ISO 11808 compliant network; a Homepiug network; a Home PNA network; and an ISO 11519-2 compliant network. 121. Power feed circuitry of a power source equipment (PSE) network device operable to detect fault conditions within power and data distribution lines coupled to the power feed circuitry, comprising: network interface circuitry communicativeSy coupled to the network to exchange both data and power signals: power interface circuitry communicatively coupled to: at least one isolated power supply in order to draw power; and the network interface circuitry in order to supply a network power signal to an attached network device; and a fault detection module coupled to the power interface circuitry and network interface circuitry, wherein the fault detection module is operable to sense a fault condition associated with the power interface circuitry, network interface circuitry, and associated distribution Sines.

122. A power source equipment (PSE) network device operable to distribute both an Ethernet power signal and an Ethernet data signal through a coupled Ethernet network, comprising: an Ethernet network connector operable to physically couple the PSE network device to the Ethernet network; a PSE controller; an Ethernet physical layer (PHY) module operable to interface the PSE network device to a multiport switch; and

an integrated circuit (!C) coupled to the Ethernet network connector that further comprises power feed circuitry, wherein the power feed circuitry comprises: power interface circuitry communicatively coupled to: at least one isolated power supply in order to draw power; and network interface circuitry in order to suppiy a Ethernet power signal to the Ethernet network connector; a fault detection module coupled to the power interface circuitry and network interface circuitry, wherein the fault detection module is operable to: sense a fault condition associated with the the power interface circuitry, network interface circuitry, and associated distribution lines; and balance power signals based on the sensed fault condition, 123. The power feed circuitry of Claim 121 or the PSE network device of Claim

122 wherein; the fault detection module is operable to sense a current associated with each power distribution iine : wherein the fault detection module identifies fault conditions based on the sensed current associated with each power distribution line.

124. The power feed circuitry of Claim 121 or the PSE network device of Claim 122 wherein: the network power signals comprise: a first power signal that utilizes a first pair of twisted pairs; and/or a second power signal that utilizes a second pair of twisted pairs.

125. The power feed circuitry of Claim 125 or the PSE network device of Claim 122 wherein the fault detection module balances power within each power distribution Sine based on the identified fault condition.

126. The power feed circuitry or the PSE network device of Claim 125 wherein when a first power distribution lines open circuits, the fault detection module loads the remaining power distribution lines, wherein this loading does not exceed a power rating of the remaining power distribution lines,

127. The power feed circuitry or the PSE network device of Claim 126 wherein the power distribution lines couple the power feed circuitry to at least one power supply, 128. The power feed circuitry or the PSE network device of Claim 128 wherein the power distribution lines couple the power feed circuitry to at least one network attached device.

129. The power feed circuitry of Claim 121 or the PSE network device of Claim 122 wherein the data distribution Sines are operabie to implement lOMbps, IOOMbps and/or iGbps physical layer functions.

130. The power feed circuitry of Claim 121 wherein the power feed circuitry is implement ed as an integrated circuit (IC) that further comprises an Ethernet media access controller (MAC) wherein an Ethernet PHY and Ethernet MAC are operable to implement hardware layers of an Ethernet protocol stack,

131. The power feed circuitry of Claim 121 wherein the network power signal is IEEE 802.3af compliant. 132. The power feed circuitry of Claim 121 wherein the at least one power supply is a 48 volt power.

133. The power feed circuitry of Claim 121 wherein the PSE network device further comprises a multi-port switch operabie to couple an Ethernet PHY module to an externa! network. 134. A method to supply power from a power source equipment (PSE) network device with an Ethernet power signal fed through an Ethernet network connection, comprising: physically coupling the PSE network device to at least one isolated power supply, wherein an integrated circuit (IC) within the PSE network device draws a first plurality of power signals from the at least one isolated power supply; sensing a current associated with each power signal of the first plurality of power signals; detecting a fault condition based on the sensed current; drawing each power signal of the first plurality of power signals based on the sensed fault condition; physically coupling the PSE network device to an Ethernet network; combining with the IC, an Ethernet data signal and an Ethernet power signal to produce an Ethernet signal; and exchanging the Ethernet signal with at least one Ethernet network power device (PD) physically coupled to the Ethernet network within the PSE network device.

135, The method of Claim 134 further comprising identifying a fault condition based on the sensed current.

138. The method of Claim 134 wherein drawing each power signal results in each sensed current not exceeding a predetermined threshold.

137. The method of Claim 134 further comprising: loading remaining power distribution lines, wherein this loading does not exceed a power rating of the remaining power distribution lines when a first power distribution line open circuit fault condition is detected. 138. The method of Claim 137 wherein the power distribution lines couple the power feed circuitry to at ieast one power supply.

139. The method of Claim 137 wherein the power distribution lines couple the power feed circuitry to at least one network attached device.

140. The method of Claim 134 wherein the Ethernet signal implements lOMbps, lOOiVibps and/or 1Gbps physical layer functions.

141. The method of Claim 134 wherein the power feed circuitry is implemented as an integrated circuit (IC) that further comprises an Ethernet media access controller (MAC) wherein an Ethernet PHY and Ethernet MAC are operable to implement hardware layers of an Ethernet protocol stack. 142. The method of Claim 134 wherein the Ethernet signal is IEEE 802.3af compliant.

143. The method of Claim 134 wherein the Ethernet network comprises at least one network selected from the group consisting of: a vehicle based network; a high speed data network; a low speed data network; a local-interconnect network (LIN); a controller area network (CAN); a FlexRay network; a TTCAN network; a J1939 compliant network; an ISO 11898 compliant network; a Homepiug network; a Home PNA network; and an !SO 11519-2 compliant network.

Description:

NETWORK DEVICES FOR SEPARATING POWER AND DATA SIGNALS

BACKGROUND

[0001] Many networks such as local and wide area networks (LAN/WAN) structures are used to carry and distribute data communication signals between devices. Various network elements include hubs, switches, routers, and bridges, peripheral devices, such as : but not limited to, printers, data servers, desktop personal computers (PCs), portable PCs and personal data assistants (PDAs) equipped with network interface cards. Devices that connect to the network structure use power to enable operation. Power of the devices may be supplied by either an internal or an externa! power supply such as batteries or an AC power via a connection to an electrical outlet,

[0002] Some network solutions can distribute power over the network in combination with data communications. Power distribution over a network consolidates power and data communications over a single network connection to reduce installation costs, ensures power to network elements in the event of a traditional power failure, and enables reduction in the number of power cables, AC to DC adapters, and/or AC power supplies which may create fire and physical hazards. Additionally, power distributed over a network such as an Ethernet network may function as an uninterruptible power supply (UPS) to components or devices that normally would be powered using a dedicated UPS, [0003] Additionally, network appliances, for example voice-over-lnternet-Protocol (VOIP) telephones and other devices, are increasingly deployed and consume power. When compared to traditional counterparts, network appliances use an additional power feed. One drawback of VOIP telephony is that in the event of a power failure the ability to contact emergency services via an independently powered telephone is removed. The ability to distribute power to network appliances or circuits enable network appliances such as a VOIP telephone to operate in a fashion similar to ordinary analog telephone networks currently in use.

[0004] Distribution of power over Ethernet (PoE) network connections is in part governed by the Institute of Electrical and Electronics Engineers (IEEE) Standard 802.3 and other relevant standards, which are incorporated herein by reference. However,

_ i ~

power distribution schemes within a network environment typically employ cumbersome, real estate intensive, magnetic transformers. Additionally, power over Ethernet (PoE) specifications under the !EEE 802,3 standard are stringent and often limit allowable power. [CSGOS] Many limitations are associated with use of magnetic transformers

Transformer core saturation can limit current that can be sent to a power device, possibly further limiting communication channel performance. Cost and board space associated with the transformer comprise approximately 10 percent of printed circuit board (PCB) space within a modern switch. Additionally, failures associated with transformers often account for a significant number of field returns. Magnetic fields associated with the transformers can result in lower electromagnetic interference (EMi) performance,

[0006] However, magnetic transformers also perform several important functions such as supplying DC isolation and signal transfer in network systems. Thus, an improved approach to distributing power in a network environment may be sought that addresses limitations imposed by magnetic transformers while maintaining transformer benefits.

SUiMI β/IARY

[0007] In some embodiments, a network device comprises a transformer with a primary winding and a secondary winding. The primary winding is coupled to receive input signals from a network connector and supply data signals to a physical layer (PHY) moduie. An inductance boost circuit is coupled to the secondary winding and operable to increase the impedance of the primary winding.

[0008] In other embodiments, a network device comprises an autotransformer coupled to receive input signals from a network connector and supply data signals to a physical layer (PHY) module. An electronic load coupled in parallel between the autotransformer and the PHY layer module.

[0009] In further embodiments, methods are disclosed that include coupling an inductance boost circuit coupied to a secondary winding of a transformer The primary winding of the transformer receives input signals from a network connector and supplies data signals to a physical iayer (PHY) module The inductance boost circuit is configured to stop functioning during an over-voitage event due to high currents saturation of the transformer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the invention relating to both structure and method of operation may best be understood by referring to the following description and accompanying drawings; FIGURES 1A and 1B show embodiments of client devices in which power is supplied separately to network attached client devices, and a power-over Ethernet (PoE) enabled LAN switch that supplies both data and power signals to the client devices;

FIGURE 2 shows an embodiment of a network interface device including a network powered device (PD) interface and a network power supply equipment

(PSE) Interface, each implementing a non-magnetic transformer and choke circuit;

FIGURE 3A is a diagram of an example of a configuration for a network interface device that includes active boosting circuits for a magnetic transformer and diode bridges to rectify power signals received from the transformers;

FIGURE 3B is a diagram of an embodiment of an active inductance boost circuit; FIGURE 3C is a diagram of an embodiment of an electronic load circuit;

FIGURE 4 is a diagram of another embodiment of a configuration for a network interface device that includes autotransformers and diode bridges to rectify power signals received from the transformers;

FIGURE 5 is a functional circuit diagram showing an embodiment of a network device that includes transformers and rectifying circuits whereby power is delivered via the center taps of the transformers;

FIGURE 6 is a schematic circuit diagram showing an example of a configuration for a network interface that includes magnetic transformers and dtode bridges to rectify power signals received from the transformers;

FIGURE 7 is a schematic circuit diagram illustrating an embodiment of a network device including a transistor bridge integrated onto an integrated circuit that rectifies and passes a power signai and data signal received from the network connector;

FIGURES 8A and 8B are functional circuit diagrams showing embodiments of network devices that include transformers whereby power is delivered via the center taps of the transformers;

FIGURE 9 is a partial functional block and circuit diagram illustrating an embodiment of a network device including ϋmiter circuits that ensure operation within process limits and disable functionality;

FIGURES 1OA and 1OB are circuit diagrams depicting example embodiments of limϊter circuits that may be implemented in a network device;

FIGURE 11 is a schematic functional diagram depicting an embodiment of a network device that inciudes an integrated diode bridge integrated onto an integrated circuit;

FIGURE 12 is a functional circuit diagram illustrating an embodiment of a network device further comprising a T connect and rectification diodes that improves pair to pair isolation at the expense of iarger area and inclusion of externa! components;

FIGURE 13 is a functional circuit diagram illustrating an embodiment of a network device further comprising a T connect and metal oxide semiconductor (MOS) rectifying components that improve pair to pair isolation at the cost of a greater number of external components;

FIGURE 14 is a schematic circuit diagram that illustrates an embodiment of a T connect circuit that is suitable for usage in a network device;

FIGURE 15 is a schematic circuit diagram depicting an embodiment of a T connect circuit that is adapted for insertion loss control;

FIGURE 16 is a schematic biock and circuit diagram showing embodiments of a network device adapted for common-mode noise suppression;

FIGURES 17A and 17B are schematic biock and circuit diagrams depicting embodiments of a network system including a common-mode suppression circuit; FIGURES 18A and 18B are schematic circuit and block diagrams which iSlustrate example implementations of a transformer function for usage in a power-over- Ethernet application;

FIGURE 19 is a schematic circuit diagram showing an embodiment of a T connect integrated circuit that includes a common-mode suppression circuit; and FIGURE 20 is a schematic biock and circuit diagram showing an embodiment of a system architecture that integrates common-mode rejection with T connect functionality;

FIGURE 21 is a schematic block and circuit diagram showing an embodiment of a network device that includes a common mode suppression circuit;

FIGURE 22 is a schematic block and circuit diagram showing an embodiment of a traditional choke that may be used in conjunction with an Ethernet physical layer (PHY);

FIGURE 23 is a schematic circuit and block diagram depicting an example of system noise coupling paths for emissions that may arise in a network device;

FIGURE 24 is a schematic circuit diagram illustrating a common mode suppression circuit with additional detail of the circuit and further description of the signal path;

FIGURE 25 is a schematic block and circuit diagram showing an embodiment of a programmable output stage.

FIGURE 26A shows a traditional real-estate intensive transformer based Network interface Card (NIC); FIGURE 28B is a traditional functional block diagram showing a magnetic-based transformer power supply equipment (PSE);

FIGURE 27A is a functional block diagram illustrating a network powered device interface utilizing non-magnetic transformer and choke circuitry in accordance with the illustrative embodiments; FIGURE 27B is a functional block diagram depicting a PSE utilizing non-magnetic transformer and choke circuitry in accordance with the illustrative embodiments:

FIGURE 28A illustrates two allowed power feeding schemes per the 802, 3af standard:

FIGURE 28B Illustrates the use of embodiments of the illustrative system to deliver both the power feeding schemes illustrated with FIGURE 28A allowed per the 802.3af standard;

FIGURE 29A is an embodiment of a network powered device (PD) that integrates devices at the IC leve! for improved performance;

FIGURE 29B shows an embodiment of a power source equipment (PSE) network device that integrates devices at the IC level for improved performance;

** O **

FIGURE 3OA illustrates technology associated with embodiments of the illustrative circuits as applied in the case of an enterprise VoIP phone for PD applications;

FIGURE 3OB illustrates technology associated with embodiments of the illustrative circuits as applied in the case of a network router for PSE applications with different power isolation schemes;

FIGURES 31 A through 318 illustrate various embodiments of a power feed circuit;

FIGURE 32 illustrates one embodiment of a power feed circuit diagram; FIGURE 33A is a 2 twisted pair Alternative A embodiment operable to support

10/100M Ethernet signaling;

FIGURE 33B is a 2 twisted pair Alternative B embodiment operable to support 10/10OM Ethernet signaling;

FIGURE 33C is a 2 twisted pair Alternative A embodiment operable to support 10/100/1000y Ethernet signaiing;

FIGURE 33D is a 4 twisted pair operable to support 10/10OM Ethernet signaling;

FIGURE 33E is a 4 twisted pair operable to support 10/100/1000M Ethernet signaling;

FIGURE 34 is a logic flow diagram iilustrating operation of the illustrative system; FIGURE 35 illustrates one embodiment of a power feed circuit having a separate fault detection module in accordance with an embodiment of the illustrative system;

FIGURE 38 illustrates one embodiment of a power feed circuit having a separate fault detection module in accordance with an embodiment of the illustrative system; and

FIGURE 37 is a logic flow diagram in accordance with an embodiment of the illustrative system.

~ 8 ~

DETAfLED DESCRIPTION

[0011] The IEEE 802.3 Ethernet Standard, which is incorporated herein by reference, addresses loop powering of remote Ethernet devices (802.3af). Power over Ethernet (PoE) standard and other similar standards support standardization of power delivery over Ethernet network cables to power remote client devices through the network connection. The side of Sink that supplies power is called Powered Supply Equipment (PSE). The side of link that receives power is the Powered device (PD). Other implementations may supply power to network attached devices over alternative networks such as, for example, Home Phoneiine Networking alliance (HomePNA) Socaf area networks and other similar networks. HomePNA uses existing telephone wires to share a single network connection within a home or building. In other examples, devices may support communication of network data signals over power lines.

[0012] In various embodiments, an active inductance boost transformer reduces the size of the transformer required to separate power signals from data signals, it is expected that the boost transformer will have at least 10X-10QX less voiurπe than a conventional transformer. The active boost transformer increases the impedance for data signals, and acts as a short circuit during over-voltage and over-current events, As a result, the surge current will flow through the protection circuit, thereby preventing damage to connected devices. [0013] Furthermore, conventional transformers create insertion loss and return loss as well as limit high frequency performance, Repiacing a conventional transformer with a boost transformer (or an autotransformer) removes a major source of data signal degradation and helps enable high speed operation, for example. Gigabit and 10 Gigabit operation, [0014] FIGURE 1A is a schematic block diagram that illustrates a high level example embodiment of devices in which power is supplied separately to network attached client devices 112 through 118 that may benefit from receiving power and data via the network connection. The devices are serviced by a local area network (LAN) switch 110 for data. Individual client devices 112 through 116 have separate power connections 118 to electrical outlets 120. FIGURE 1B is a schematic block diagram that depicts a high level example embodiment of devices wherein a switch 110 is a power supply equipment (PSE)-capabSe power-over Ethernet (PoE) enabled LAN switch that supplies both data and power signals to client devices 112 through 116. Network attached devices may include a Voice Over Internet Protocol (VOIP) telephone 112, access points, routers, gateways 114 and/or security cameras 116, as well as other network appliances.

Network supplied power enables client devices 112 through 116 to eliminate power connections 118 to electrical outlets 120 as shown in FIGURE 1A, Eliminating the second connection enables the network attached device to have greater reliability when attached to the network with reduced cost and facilitated deployment. [0015] Although the description herein may focus and describe a system and method for coupling high bandwidth data signals and power distribution with particular detail to the IEEE 802.3af Ethernet standard, the concepts may be applied in non-Ethernet applications and non-IEEE 802.3af applications. Also, the concepts may be applied in subsequent standards that supersede or complement the SEEE 802.3af standard, such as HDSL {High bit-rate Digital Subscriber Line), T1/E1, cable modem, and other suitable technologies.

[0016] Typical conventional communication systems use transformers to perform common mode signal blocking, 1500 volt isolation, and AC coupling of a differential signature as well as residual lightning or electromagnetic shock protection. The functions are replaced by a solid state or other similar circuits in accordance with embodiments of circuits and systems described herein whereby the circuit may couple directly to the line and provide high differential impedance and low common mode impedance. High differential impedance enables separation of the physical layer (PHY) signal from the power signal. Low common mode impedance enables elimination of a choke, aiiowing power to be tapped from the line. The local ground plane may float to eliminate a requirement for 1500 volt isolation. Additionally, through a combination of circuit techniques and lightning protection circuit, voltage spike or lightning protection can be supplied to the network attached device, eliminating another function performed by transformers in traditional systems or arrangements. The disclosed technology may be applied anywhere transformers are used and is not limited to Ethernet applications.

[0017] Specific embodiments of the circuits and systems disclosed herein may be applied to various powered network attached devices or Ethernet network appliances. Such appliances include, but are not limited to VoIP telephones, routers, printers, and other suitable devices. [0018] In an Ethernet application, the IEEE 802,3af standard (PoE standard) enables delivery of power over Ethernet cables to remotely power devices. The portion of the connection that receives the power may be referred to as the powered device (PD). The side of the link that supplies power is called the power sourcing equipment (PSE).

[0019] Referring to FIGURE 2, a functional block diagram depicts an embodiment of a network device 200 including power source equipment (PSE) interface 202 coupled to

powered device (PD) interface 204 via respective network connectors 206 and multiple twisted pair conductors 208 between connectors 206, Twisted pair conductors 208 can be, for example, twisted 22-26 gauge wire and connectors 206 can be RJ-45 connectors. Other suitable conductors and connectors can be used. [0020] In the embodiment shown, PSE interface 202 includes non-magnetic transformers and choke circuit 212 and power source equipment (PSE) controller 214 coupled between physical iayer (PHY) layer module 216 and connector 206, Nonmagnetic transformer and choke circuit 212 are implemented in integrated circuitry and replace the functionaiity of a magnetic transformer Eliminating magnetic transformers with integrated system solutions enable an increase in component density by replacing magnetic transformers with solid state power feed circuit in the form of an integrated circuit or discreet component.

[0021] PD interface 204 can include active inductance boost transformers 220, nonmagnetic choke circuit 222, and electronic load (eload) circuit 224 coupled between another connector 206 and PHY layer module 226. Power potential rectifiers 228 and power device controller 230 can be coupled between connector 206 and DC-DC converter 232.

[0022] Power potential rectifiers 228 rectify and pass a received power signal to ensure proper signai polarity is applied to DC-DC converter 230 The network device 200 is shown sourcing power through lines 3, 4, 5, and 8 of the network connectors 206, however, other lines can be used. Power potential rectifiers 228 may be a diode bridge or other rectifying component or device. The circuits may be discrete components or an integrated circuit. Any one of a subset of the twisted pair conductors 208 can forward bias to deliver current, and the power potential rectifiers 228 can forward bias a return current path via a remaining conductor of the subset.

[0023] Power device controller 230 may be used to control power supply to network attached devices, The power signals are supplied by power potential rectifiers 228 to converter 232. Typically the power signal received does not exceed 57 volts SELV (Safety Extra Low Voitage). Typical voltage in an Ethernet application is 48-voSt power. Converter 232 may then further transform the power to provide 1.8 to 12 volts, or other voltages specified by many Ethernet network attached devices, such as wireless access point circuitry or IP telephony circuitry.

[0024] If the PD interface 204 is used in an Ethernet network, may support the 10/100/1000 Mbps data rate and other future data networks such as a 10000 Mbps Ethernet network as we!! as other Ethernet data protocols that may arise. An Ethernet

PHY layer module 228 may additionally couple to an Ethernet media access controller (MAC) (not shown). The PHY layer module 226 and Ethernet MAC when coupled can implement the hardware layers of an Ethernet protocol stack. The architecture may also be applied to other networks and protocols. If a power signal is not received but a traditional, non-power Ethernet signal is received at connector 206, the PD interface 204 still passes the data signal to the PHY layer module 226.

[0025] PSE interface 202 and PD interface 204 may be applied to an Ethernet application or other network-based applications such as, but not limited to, a vehicle- based network such as those found in an automobile, aircraft, mass transit system, or other like vehicle. Examples of specific vehicle-based networks may include a local interconnect network (LIN), a controller area network (CAN), or a flex ray network. Al! may be applied specifically to automotive and aircraft networks for the distribution of power and data to various monitoring circuits or for the distribution and powering of entertainment devices, such as entertainment systems, video and audio entertainment systems often found in today's transportation. Other networks may include a high speed data network, Sow speed data network, time-triggered communication on CAN (TTCAN) network, a J1939-compiiant network, !SO11898-compliant network, an ISO11519-2- compliant network, as well as other similar networks. Other embodiments may supply power to network attached devices over alternative networks such as but not iirnited Io a HomβPNA local area network and other similar networks. HomePNA uses existing telephone wires to share a single network connection within a home or building Alternatively, embodiments may be applied where network data signals are provided over power lines,

[0026] In some embodiments, non-magnetic transformer and choke circuit 212, PHY layer modules 216, 226, PSE controller 214 : non-magnetic choke circuit 222, rectifiers 228, PD controller 230, and converter 232 may be implemented in integrated circuits rather than discrete components at the printed circuit board level. The circuits may be implemented in any appropriate process, for example, power components may be implemented using a high voltage silicon on insulator process whereas other components can be implemented using a 0.18 or 0.13 micron process or any suitable size process.

[0027] Network device 200 may implement functions including IEEE 802.3. af signaling and load compliance, iocal unregulated supply generation with over current protection, and signal transfer between the lines 208 and integrated Ethernet PHY layer modules 216, 226. Since devices are directly connected to the line 208, the device 200 may be implemented to withstand a secondary voltage surge.

[0028] Non-magnetic transformer and choke circuit 212 may take the form of a single or multiple port switch to supply power to single or multiple devices attached to the network. Power sourcing equipment interface 202 may be operabie to receive power and data signals and combine to communicate power signals which are then distributed via an attached network, if power sourcing equipment interface 202 is included in a gateway or router computer, a high-speed uplink coupies to a network such as an Ethernet network or other network. The data slgna! is relayed via network PHY 216 and supplied to non-magnetic transformer and choke circuit 212. Power sourcing equipment interface 202 may be attached to an AC power supply or other internal or external power supply to supply a power signal to be distributed to network-attached devices that coupie to power sourcing equipment interface 206.

[0029] Power sourcing equipment (PSE) controller circuit 214 within or coupled to non-magnetic transformer and choke circuit 212 may determine, in accordance with IEEE standard 802.3af or other suitable standard, whether a network-attached device in the case of an Ethernet network-attached device is a device operabie to receive power from power supply equipment. When determined that an SEEE 802.3af compliant powered device (PD) is attached to the network, PSE controiler circuit 214 may supply power from power supply to non-magnetic transformer and choke circuit 212, which is sent to the downstream network-attached device through network connectors 206, which in the case of the Ethernet network may be an RJ45 receptacSe and cable.

[0030] IEEE 802.3af Standard is to fulSy comply with existing non-line powered Ethernet network systems. Accordingly, PSE detects via a well-defined procedure whether the far end is PoE compliant and classify sufficient power prior to applying power to the system. Maximum allowed voltage is 57 volts for compliance with SELV (Safety Extra Low Voltage) limits.

[0031] For backward compatibility with non-powered systems, applied DC voltage begins at a very Sow voltage and only begins to deliver power after confirmation that a PoE device is present. In the classification phase, the PSE applies a voltage between 14.5V and 20.5V, measures the current and determines the power class of the device. In some embodiments, the current signature is appiied for voltages above 12.5V and below 23 Volts. Current signature range is 0-44mA.

[0032] A maintain power signature can be appiied in the PoE signature block - a minimum of 10mA and a maximum of 23.5 kilo-ohms may be applied for the PSE interface 202 to continue to feed power. The maximum current allowed is limited by the power class of the device (class 0-3 are defined). For class 0, 12,95 Watts is the

maximum power dissipation allowed and 400 miiliampβres is the maximum peak current. Once activated, the PoE will shut down if the applied voltage fails below 30V and disconnect from the Sine 208.

[0033] Power source devices in normal power mode provide a differential open circuit at the Ethernet signal frequencies and a differential short at Sower frequencies. The common mode circuit presents the capacitive and power management ioad at frequencies determined by PSE controiler circuit 214.

[0034] Referring to FfGURE 3A, a schematic circuit diagram of an embodiment of powered device (PD) interface 300 is shown that is suitable for use as PD interface 202 in FJGURE 2. PD interface 300 includes connector 206 coupled to active inductance boost transformers 304, 306 that include primary and secondary windings. Transformers 304 are connected across Sine pairs 1 and 2, and 3 and 6. Transformers 308 are connected across iinβ pairs 4 and 5 : and 7 and 8, Active inductance boost circuits 308 are coupled to respective secondary windings of transformers 304, 306. Capacitors 310 are coupled between transformers 304, 306 and PHY layer modules 226. Electronic ioads (ELOAD) 224 are coupled in paralie! between respective transformers 304, 306 and PHY layer modules 226,

[0035] The purpose of using either an autotransformer or a traditional transformer is to provide high impedance at as low a frequency as possible to avoid affecting the data signal. High impedance can be achieved with large inductance, which is physically large and costiy. Active inductance boost circuits 308 reduce the size of the inductance needed. During an over-voltage event active boost circuits 308 will not function because the high currents will saturate the core of the transformer. Because the inductance is much smaller than in a traditional transformer, the inductor quickly shorts out and provides an excellent current discharge path. This would also happen in a traditional transformer, but because the inductance is so much smaller the voltage excursion during the over-voltage event, which couid affect the PHY devices, is also much smaller

[0036] FIGURE 3B shows an embodiment of active inductance boost circuit 308 coupied to the secondary winding of transformer 304 that can be used in PD interface 300 to reduce the size of the transformer component and avoid other problems associated with other types of transformers. Boost circuit 308 typically includes an active circuit (not shown) that senses the current from transformer 304 and feeds back a proportional amount of current. Primary and secondary windings of transformer 308 typically have a 1:1 ratio. A feedback gain factor (α) is applied to the sensed current

(isenβa) to increase the impedance (z) on the primary side of transformer 304. The increase in impedance on the primary side of transformer 304 is (1 / (1 - «)), where α is typically close to, but less than one (1). The impedance (Zi,,) on the primary side of transformer 304 is given by;

Z 111 = sL 2 /{1 - α)

where: s = frequency of the input signal.

L 2 - the inductance of the primary winding, and α = feedback gain factor.

[0037] Note that active inductance boost circuit 308 reduces the requirement for surge protection compared to &n autotransformer or traditional transformer due to the fact that the required inductance is achieved with boost transformer 308 rather than a larger transformer. Note that smaller transformers 304 : 30$ wilt saturate at a much lower current. Thus, in an over-voitagβ event, capacitors (not shown) in PD controller 320 effectively short out the tines to chassis (or earth) ground and limit the energy provided to PHY layer module 226. In some embodiments, over-voltage protection circuitry can be included with rectifier circuit 316 in addition to, or instead of using capacitors in PD controller 320.

[0038] Eioad circuit 224 provides provide common-mode output voltage control and a current source to the PHY layer module 226. FIGURE 3C shows an embodiment of eload circuit 224 that includes leads 352 coupled to respective positive and negative medium dependent interface (MD!) input signals to PHY layer module 228. Voltage source Vcc is coupled between leads 352, and current sources 354 are coupled inline with leads 352 between voltage source Vcc and fvtDS input signals to PHY layer module 226. Sense resistors 356 are coupled in series between positive and negative leads 352. Common mode (CM) lead is coupled between first and second sense resistors 356, and differential amplifier 358. A reference voltage is supplied to another input of differential amplifier 358 and a signal representing the difference between the CM input signal and the reference voltage signal is output by differential amplifier 358 and supplied to current sources 354. [0039] The embodiment shown also includes an active common mode suppression (CMS) circuit 360 coupled to respective positive and negative MD! input signals to PHY layer module 226. CMS circuit 360 includes an inductor that blocks alternating current wht!e passing direct current to PHY layer module 226.

[0040] Eioad circuit 224 can sense and supply the current required by PHY layer module 226 and active CMS circuit 360. The common mode voltage level is controlled by active feedback to current supplies 354 through differential amplifier 358, thereby providing a high differential mode impedance in the frequency band of interest for the signals to PHY layer module 228. Additionally, eSoad circuit 224, active CMS circuit 380, and PHY iayer module 226 can be integrated in the same integrated circuit process technology, thereby reducing fabrication cost and complexity.

[0041] Referring again to FIGURE 3A 1 rectifier circuits 316, 318 receive input signals from center taps of transformers 304, 306. A first rectifier circuit 316 receives input power and data signals from the center taps of the transformers 304 connected across ϋnes 1 and 2, and across lines 3 and 8 of the network connector 306. A second rectifier circuit 318 receives input power and data signals from the center taps of the transformers 306 connected across lines 4 and 5, and across lines 7 and 8 of the network connector 302. For the power over Ethernet (PoE) to be IEEE 802.3af standard compliant the PoE may be configured to accept power with various power feeding schemes and handle power polarity reversal, A rectifier, such as a diode bridge, a switching network, or other circuit, may be implemented to ensure power signals having an appropriate polarity are delivered to PD controller and DC-DC converter circuits 320,

[0042] The illustrative PD interface 300 may be implemented as part of a powered device (PD) that receives power sourced by power sourcing equipment (PSE), for example, on line pairs 1 and 2, and 3 and 8 on the network connector 302. Each rectifier circuit 316, 318 has connections to respective transformers 304, 306. One of the two connections is at supply potential, for example VDD, and one is at ground potential. Power is applied to the two input terminals of rectifier circuits 316, 318 at a high potential and a low potential but the potential applied to a particular input terminal is not important Rectifier circuits 316, 318 rectify the power signal so that no matter how power is connected, one output line is always at the VDD supply potential (VDD OUT) and another output line is at ground potential (GND OUT). Examples of rectifier circuits 316, 318 that can be used include diode bridge rectifier circuits or MOSFET bridge rectifier circuits, among others.

[0043] Referring to FIGURE 4 : another embodiment of a powered device (PD) interface 204 is shown that is suitable for use as PD interface 204 in FiGURE 2. PD interface 400 includes connector 402 coupled to autotransformers 404, 406. Autotransformers 404, 406 are eiectrica! transformers with only one winding. The winding has at least three eiectrica! connection points called taps. The voltage source is applied to two taps and an electronic load 408 is connected to two taps, one of which is

usually a common connection that is aiso connected to the source. A portion of the same winding effectively acts as part of both the primary and secondary winding. Transformers 404 are connected across line pairs 1 and 2, and 3 and 6 of connector 402. Transformers 406 are connected across line pairs 4 and 5, and 7 and S of connector 402. Capacitors 410 can be coupled to the leads between transformers 404, 406 and PHY layer modules 412, Electronic loads 408 are coupled in parallel to leads between capacitors 410 and PHY layer modules 412.

[0044] Common mode suppression (CMS) circuits and surge protection Circuits can be included between transformers 404, 406 and PHY layer modules 412 [0045] Rectifier circuits 416, 418 may be a diode bridge or other rectifying component or device. A bridge or rectifier may couple to individual conductive lines 1-8. For example, FIGURE 4 shows rectifier circuits 416, 418 receiving input signals from the center taps of the transformers 404 : 406, A first rectifier circuit 416 receives input power signals from the center taps of the transformers 404 connected across lines 1 and 2, and connected across lines 3 and 8 of the network connector 402, A second conditioning circuit 418 receives input power signals from the center taps of the transformers 406 connected across lines 4 and 5, and connected across lines 7 and 8 of the network connector 402.

[0046] The illustrative PD interface 400 may be implemented as part of a powered device (PD) that receives power sourced by power sourcing equipment (PSE), for example, on line pairs 1 and 2, and 3 and 6 on the network connector 402. Each conditioning circuit 416, 418 has two connections to center taps of two respective transformers 404, 406. One of the two connections is at supply potentiai, for example VDD, and one is at ground potential Power is applied to the two input terminals of the conditioning circuit 416, 418 at a high potential and a low potential but the potential applied to a particular input terminal is not known. Thus, the conditioning circuit 416, 418 rectifies the power signal so that no matter how power is connected, one output line is always at the VDD supply potential (VDD OUT) and another output line is at ground potential (GND OUT), A disadvantage of using a diode bridge in conditioning circuits 416, 418 is lossy rectification performance. Accordingly, rectifier circuits 416, 418 can be implemented with a transistor bridge, for example, with metal oxide semiconductor field effect transistors (SViGSFETs) replacing the diodes shown in rectifier circuits 416, 418.

[0047] Referring to FIGURE 5. functional circuit diagrams illustrate embodiments of network device 500 that includes transformers 502 whereby power is delivered via the

center taps 506 of the transformers 502. The transformer center taps 506 separates the power signal from the data signal.

[0048] In addition to a power potential rectifier circuit 504 that rectifies and passes a power signal and data signal received from a network connector 508, the network device 500 further comprises one or more transformers 502 coupled across Sine pairs of the network connector 508. The transformers 502 include a coil 510 and a center tap 506 coupled to the coil 510. The center tap 506 is configured to separate the power signal from the data signal. Power potential rectifier circuits 504 are coupled to the transformer center taps 506 and configured to regulate the power signal. In an illustrative embodiment, the power potential rectifier circuits 504 may be a MOSFET bridge.

[0049] Power signals accessed from the transformer center taps 506 cross-couple the input line pairs to ensure that one line pair is high and one line pair is low at any time. For example, in the illustrative structure if line pairs 1 and 2 are high : then line pairs 3 and β are low. Accordingly, the center tap voltage of Sines 1 and 2 is used to control the NMOS transistor in the connected MOSFET rectifier circuits 504 to control the other lines or route power to the other lines to ground. Thus, if the same potential is tied to the PiVlOS transistor, which extends to the VDD OUT signal line, then the PMOS transistors are in an off state because lines 1 and 2 are high and the voltage at the center tap 506 of the transformer 502 controis the rectifier circuits 504 so that PMOS transistors are turned on, routing power to VDD OUT, and NMOS transistors are turned off.

[0050] Although FIGURE 5 shows network device 500 with MOSFET rectifier circuits 504 in combination with transformers 502, other embodiments may employ rectifiers constructed from other transistor types such as junction field effect transistors (JFETs), bipolar transistors, and others. [0051] The MOSFET rectifier circuits 504 can route power in configurations that include transformers as shown in FIGURE 5, and in configurations that omit the transformers depicted in FIGURE 4.

[0052] FIGURE 5 illustrates a technique for supplying power over a communication interface such as an Ethernet interface wherein power is supplied from the center tap 506 of a transformer 502. Center tapping of the transformer coil 510 enables power to be separated from the Ethernet signal. Power iines connected to the center taps of the transformers are connected to a rectifier bridge circuit 504, illustrated as a MOSFET bridge, but which can be implemented in other forms such as junction field effect transistor (JFET), bipolar transistors, other switching devices, diode bridges, and others. The rectifier circuit 504 rectifies the power signal. In the illustrative embodiment an

R J45 interface has eight lines with paired Sines 1 and 2. 3 and 6, 4 and S 1 and 7 and 8 respectively connected to two bridges or four bridges. Each bridge has two input lines, each supplied from the center tap of a transformer, and two output lines including a VDD supply out and a ground output, input Sines to the bridges are connected to the transformer center-tap rather than direct connections to the interface lines because direct connections can result in degradation to the Ethernet data signals. Bridge rectifier functional performance is determined by a capability to rectify the power signal and pass the Ethernet signa! with a reduced or minimized degradation.

[0053] Limiter circuits 512 can be included to ensure operation within process limits, [0054] Embodiments disclosed herein provide improved network interface devices by reducing the size of the transformer required to separate the power from the data signal, in some implementations, it is expected that transformers 304, 306 (FIGURE 3A) wiii require 10 to 100 times less voiume. Aiso, while the active boost circuit 308 increases the impedance for the data signal, boost circuit 308 and capacitors in PD controller 320 protect devices coupled to PHY layer module 226 from over-voltage and over-current protection, such as defined by I EC61000-4-2/4/5, allowing the surge current to flow through a board ground path. By removing the traditional transformer, embodiments disclosed herein remove one of the major degrading circuits in the data signai path. The transformer creates insertion loss and return loss as well as limiting the high frequency performance. With the active boost approach, a transformer is no longer in the data signal path Such features wiϋ help enable high speed data transfer in PoE networks, for example, Gigabit and 10 Gbit operation.

[0055] According to an embodiment of a network device, a power potential rectifier is adapted to conductively couple a network connector to an integrated circuit that rectifies and passes a power signai and data signai received from the network connector. The power potential rectifier regulates a received power and/or data signai to ensure proper signal polarity is applied to the integrated circuit,

[0056] Electrostatic discharge (ESD) and power rectification can be attained through integration of elements available in a complementary metal oxide semiconductor (CMOS) high-voltage process. High voltage isolation can be implemented via a power potential rectifier that regulates a received power and/or data signa! to ensure proper signal polarity is applied to the integrated circuit.

[0057] The IEEE 802,3 Ethernet Standard, which is incorporated herein by reference, addresses loop powering of remote Ethernet devices (802.3af) Power over Ethernet (PoE) standard and other similar standards support standardization of power

delivery over Ethernet network cables to power remote client devices through the network connection. The side of link that supplies power is called Powered Supply Equipment (PSE). The side of link that receives power is the Powered device (PD). Other implementations may suppiy power to network attached devices over alternative networks such as, for example. Home Phoneiine Networking alliance {HomePNA} iocai area networks and other similar networks, HomePNA uses existing telephone wires to share a single network connection within a home or building. In other examples, devices may support communication of network data signals over power lines

[0058] In various configurations described herein, a magnetic transformer of conventional systems may be eliminated while transformer functionality is maintained. Techniques enabling replacement of the transformer may be implemented in the form of integrated circuits (!Cs) or discrete components.

[0059] In various embodiments, bridging circuits can be implemented that are connected directly to lines of the network interface with no intervening transformer. Coupling is present between the paired lines. Therefore, the bridging circuits may be configured to reduce or minimize cross-talk. The bridging circuits may be further configured to track the Ethernet signal with reduced or minimal signal degradation, while pulling and rectifying the power signal which is then passed to a T connect that facilitates separation of the Ethernet signal from the power signal. Some illustrative bridging circuits may be constructed from metal oxide semiconductor field effect transistors (MOSFETs), although diodes or other active circuits may be used in other implementations with some variability in aspects of performance. Aspects of the design involve consideration of the intimate association of the Ethernet and power signals, and handling of the association in optimizing performance characteristics including power ioss, cross-talk, Ethernet signal fidelity, and other considerations.

[0060] The illustrative bridge circuit inciudes a limiter circuit which is adapted to ensure that the gate-to-soυrce voltage of each line oscillates with the Ethernet signal so that the voltage across the switch remains relative constant since the Ethernet signal is passed on the line. The bridge circuit reduces or minimizes cross-talk by ensuring that gates are off with respect to lines that are not connected to lines Tc_ydd and Tc ^ gnd. The circuits ensure that all gates are off for the lines that are not powered and therefore disconnect cross-coupling from various pins from the RJ45 connector.

[0061] Referring to FIGURE 6. a schematic circuit diagram illustrates an example of a conventional configuration for a network interface 600 that includes magnetic transformers 602 and diode bridges 604 with the diode bridges 604 receiving input

signals from the center taps 606 of the transformers 602. Transformers 602 are connected across line pairs 1 and 2, 4 and 5, 7 and 8, and 3 and 6. A first diode bridge 604 receives input power and data signals from the center taps of the transformers 602 connected across ϋnes 1 and 2. and connected across lines 4 and 5 of the network connector 608. A second diode bridge 604 receives input power and data signals from the center taps of the transformers 602 connected across lines 7 and 8, and connected across iines 3 and 8 of the network connector 60S.

[0062] The illustrative network interface 600 may be implemented as part of a powered device (PD) that receives power sourced by power sourcing equipment (PSE), for example, on line pairs 1 and 2, and 3 and 6 on the network connector 608. Each diode bridge 604 has two connections to center taps of two respective transformers 602. One of the two connections is at supply potential, for example VDD, and one ts at ground potential Power is applied to the two input terminals of the diode bridge 604 at a high potential and a low potential but the potential applied to a particular input terminal is not known. Thus, the diode bridge rectifies the power signal so that no matter how power is connected, one output line is always at the VDD supply potential (VDD OUT) and another output line is at ground potential (GND OUT) A disadvantage of the diode bridge 604 is a lossy rectification performance.

[0063] In some embodiments, a network interface can be configured that enables elimination of the transformers. Referring to FIGURE 7, a schematic circuit diagram illustrates an embodiment of a network device 700 including a transistor bridge 702 integrated onto an integrated circuit 704 thai rectifies and passes a power signal and data signal received from the network connector 732. in the illustrative embodiment, a metal oxide semiconductor (SvIGS) bridge is integrated onto the integrated circuit. [0064] The transistor bridge 702 is adapted for direct connection to the network connector 732, enabling elimination of an intervening transformer. The illustrative transistor bridge 702 )s power bπdge circuitry that connects into a T connect element 706 in a configuration whereby power rectification functionality integrated on the integrated circuit 704. [0065] The transistor bridge 702 is configured for integration into the integrated circuit 704 and is adapted to regulate a power and/or data signal to ensure proper power potential polarity ts applied to the integrated circuit 704.

[0066] The transistor bridge 702 couples directly to lines of the network connector 732 and regulates the power signal whereby the transistor bridge 702 passes the data signal with substantially no degradation. Thus, the transistor bridge 702 performs the

signal rectification function of the diode bridge depicted in FIGURE 6 while essentially eliminating power signal loss that is inherent in the diode implementation. The transistor bridge 702 is depicted as a meta! oxide semiconductor field effect transistor (MOSFET) bridge that is used as a power rectification circuit rather than a diode bridge to enable routing of power substantially without voltage or power loss, in contrast, a diode bridge loses power due to voltage loss across the diodes. The MOSFET implementation avoids loss and saves, in a typical worst case condition, about 5% of power.

[OO6?3 The meta! oxide semiconductor (MOS) bridge 702 comprises M~channeS metal oxide semiconductor (NMOS) transistors and P-channe! metal oxide semiconductor (PyOS) transistors connected in a bridge configuration that emulates a diode bridge with pairs of NMOS transistors replacing diodes that connect to ground and pairs of PMOS transistors replacing diodes that connect to a power line, for example VDD. Each MOSFET bridge 702 comprises a set of four transistors including two N- channel metal oxide semiconductor (NMOS) and two P-channe! metal oxide semiconductor (PiViOS) transistors. The PIV50S transistors are paired and have mutually coupled gates. The NMOS transistors are paired also with coupled gates. Paired lines of the network connector 732 couple to the source-drain pathways of the respective PMOS and NMOS transistors on the input side of the bridge, and cross-coupie to the source-dratn pathways of the respective NMOS and PMOS transistors on the output side of the bridge. The paired lines are connected through resistors RCM with a center connection between the resistors RCM coupled to the gates of an adjacent line pair. As shown, the center connection between lines 1 and 2 is coupled to gates of the MOSFET bridge coupled to lines 3 and 6. Similarly, the center connection between lines 3 and 6 is coupled to the gates of the MOSFET bridge coupled to iines 1 and 2. The MOSFET bridges coupled to line pairs 4 and 5, and 7 and 8 are similarly connected.

[0068] The network device 700 may further comprise a T connect element 706 and an Ethernet physical layer (PHY) module integrated into the integrated circuit 704. The T connect element 706 is adapted to enable the ground potential of the Ethernet PHY module to float relative to earth ground. The network device may further comprise a metal oxide semiconductor (MOS) bridge 702 integrated onto the integrated circuit and coupled to the T connect element 706.

[0069] Elimination of the transformers results in an increase in the number of bridging circuits. For example, as shown in the illustrative implementation, the integrated circuit 704 includes four transistor bridges 702, one for each pair of Sines, in contrast, the interface with transformers shown in FIGURE 6 has only two bridging circuits. Output power is routed through T connect elements 706 to present a high impedance to the

lines because the Ethernet signals are communicated on the Sines, The power signals Tc_ydd1« Tc_vdd2, TcjjndL and Tc_gnd2 are supply lines to intermediate nodes. When Ethernet signals are communicated, the signals Tc_vdd1, Tc_vdd2, Tc_gnd1, and Tc_gnd2 osciliate near ground potential. The T connect elements 706 pull the power signal out of the bridges 702 with the Ethernet signal unaffected as a short circuit for common mode signals and an open circuit for differential signals.

[0070] The iliυstrative network device 700 has the network connector 732, for example an RJ45 connector, which is external to the integrated circuit 704. Any inductors in the network device 700 typically cannot be integrated. AIi other elements can foe integrated within the integrated circuit 704. In other connect circuit embodiments, external components may be avoided or eliminated through usage of staictures such as a cascaded T connect circuit.

[0071] The source-drain pathways of the PMOS transistors in the MOSFET bridges 702 supply power VDD to T connect elements 706, depicted on Sines Tc_vdd1 and Tc_vdd2. The source-drain pathways of the NMOS transistors in the MOSFET bridges 702 supply ground GND to T connect elements 706, depicted on Sines Tc_gnd1 and Tc__gnd2. The MOSFET bridges 702 enable supply of the power Tc_vddi, Tc_vdd2 and ground lines Tc__gnd1 , Tc_gnd2 to a powered device (PD) while also carrying an Ethernet signal. The illustrative configuration enables control of the four pairs of lines Tc_vdd1, Tc_vdd2, Tc ^ gndl and Tc_gnd2 on the output side of the MOSFET bridges 702 so that three of the lines can be held near ground while one, which operates as a power line, can be at a power level, for example 60 volts,

[0072] Although the network device 700 is depicted with a transistor bridge 702 using MOSFET transistors, in other embodiments various other types of transistors may be used including, for example, bipolar junction transistors (BJT). junction field effect transistors (JFET), switchabie devices, impedance control devices, and others.

[0073] Referring to FIGURES 8A and 8B : functional circuit diagrams illustrate embodiments of network devices 800A and 800B that include transformers 802 whereby power is delivered via the center taps 806 of the transformers 802. The transformer center taps 806 separates the power signal from the data signal.

[0074] In addition to a power potential rectifier 804 that rectifies and passes a power signal and data signal received from a network connector 808, the network devices 800A , 800B further comprise one or more transformers 802 coupled across line pairs of the network connector 808. The transformers 802 comprising a coil 810 and a center tap 806 coupled to the coil 810, The center tap is configured to separate the power signal

from the data signal. Power potential rectifiers 804 are coupled to the transformer center taps 806 and configured to regulate the power signal In an illustrative embodiment, the power potential rectifier may be a MOSFET bridge.

[0075] Power signals accessed from the transformer center taps 806 cross-coupie the input Sine pairs to ensure that one line pair is high and one line pair is low at any time. For example, in the illustrative structure if line pairs 1 and 2 am high, then line pairs 3 and 6 are low. Accordingly, the center tap voltage of lines 1 and 2 is used to control the NMOS transistor in the connected MOSFET rectifier 804 to control the other lines or route power to the other iines to ground. Thus, if the same potential is tied to the PMOS transistor, which extends to the VDD OUT signal One, then the PMOS transistors are in an off state because lines 1 and 2 are high and the voltage at the center tap 806 of the transformer 802 controls the rectifier 804 so that PMOS transistors are turned on, routing power to VDD OUT, and NMOS transistors are turned off

[0078] Although FiGUREs BA and 8B show network device embodiments 800A and 800B with MOSFET bridging circuits 804 in combination with transformers 802, other embodiments may employ rectifiers constructed from other transistor types such as junction field effect transistors (JFETs) : bipolar transistors, and others.

[0077] The MOSFET bridging circuits can route power in configurations that include transformers as shown in FJGUREs 8A and 8B t and in configurations that omit the transformers depicted in FIGURE 7.

[0078] FIGURES 8A and 8B illustrate a technique for supplying power over a communication interface such as an Ethernet interface wherein power is supplied from the center tap 806 of a transformer 802. Center tapping of the transformer coil 810 enables power to be separated from the Ethernet signal. Power lines connected to the center taps of the transformers are connected to a rectifier bridge S04 ; illustrated as a MOSFET bridge, but which can be implemented in other forms such as junction field effect transistor (JFET), bipolar transistors, other switching devices, diode bridges, and others. The bridge 804 rectifies the power signal. In the illustrative embodiment, an RJ45 interface has eight lines with paired lines 1 and 2, 3 and 6, 4 and 5, and 7 and 8 respectively connected to two bridges or four bridges. Each bridge has two input lines, each supplied from the center tap of a transformer and two output lines including a VDD supply out and a ground output. Input iines to the bridges are connected to the transformer center-tap rather than direct connections to the interface lines because direct connections can result in degradation to the Ethernet data signals. Bridge rectifier

functional performance is determined by a capability to rectify the power signal and pass the Ethernet signal with a reduced or minimized degradation.

[0079] T connect circuits can be implemented following the bridges, which are not shown in FIGURES 8A and 8B ; actually separate an Ethernet signal from the power signal.

[0080] FJGURE SB depicts a network device 800B similar to network device 800A but adding iimiter circuits 812 to ensure operation within process limits.

[0081] Referring to FIGURE 9, a partial functional block and circuit diagram illustrates an embodiment of a network device 900 including iimiter circuits 912 which ensure operation within process limits and support functionality to disable bridge devices on opposing power lines. A particular process may impose limits on transistor gate voltages. For example, a particular process may impose a get voitage iimit of 5 voits. Other similar processes may impose higher or lower limits. High voltage transistors may be used that are allowed to have iarge voltages across the drain source but not across the gate source, a useful characteristic because transistors may have large drain voltages. For example, a typical MOSFET may be a 5 volt device that can have a very large drain voltage, in addition to a iimiter function, the Iimiter circuits 912 are supplemented by a disable functionality. The Iimiter and disable circuits 912 to ensure that gates of the MOS bridge are turned off for lines that are not powered. [0082] The network device 900 may be configured to comprise a transistor bridge 902 integrated onto an integrated circuit 904 In a particular implementation, the transistor bridge 902 comprises transistors configured to enable relatively large drain- source voitage V f κ and relatively smali gate-source voltage V gs . The transistors may be any suitable type. Some configurations may be formed using lateral double-diffused metal oxide semiconductor (LDMOS) transistors.

[0083] In another embodiment, the transistor bridge 902 may comprise a plurality of metal oxide semiconductor field-effect transistors (SVIOSFETs). individual IvIGSFETs may be coupied to a Iimiter 912 configured to maintain an essentially constant gate- source voltage V gs across the MOSFET at approximately a process limit whereby resistance is minimized or reduced.

[0084] For a power over Ethernet (PoE) functionality, the iimiters 912 can be configured so that current drawn during start-up is limited to a sufficiently iow level. Accordingly, the ϋmiter circuit 912 may be constructed in a simple form or more complicated form depending on the level of control that is desired. FIGURE 9 shows cross-coupling between the MOSFET bridges 902. Center taps 910 between resistor

(RGM)-connected paired lines of one MOSFET bridge 902 couple to lsmster circuit connections of a second MOSFET bridge 902 : as shown. Power and ground Sines Tc_vdd1 ; Tc_vdd2. Tc_α,nd1, and Tc_gnd2 pass signals to a T connect circuit.

[0085] The iimiter circuits 912 are implemented, typically specific to the applied fabrication process, to ensure gate voltages are limited to a specified value.

[0088] The network device 900 is configured to reduce or minimize cross-talk between pairs of network cables. For example, signals on Sine pair 1 and 2 and signals on line pair 3 and 6 are mutually protected against cross talk. Line pair 4 and 5 and ϋne pair 7 and 8 are similarly protected. Cross-talk is avoided by reducing or minimizing cross-coupling capacitances. In a specific embodiment, offset capacitance of the

MOSFETs, which is cross-coupling capacitance, is reduced to a very small ievei. For example, ϋne 2 from the network connector 908 is coupled to NMOS transistor MN2 and the source of transistor MN2 crosses back to NMOS transistor MN3. Accordingly, transistor MN3 is in an ON state when transistor MN2 is in an OFF state, if transistor MN3 is on, then the source of NMOS transistors SV5N2 and MN8 are mutually tied, creating a potential coupling between Sines 2 and 6 through a reverse connection - when one device is on, the other is off. One technique for avoiding cross-coupling may be implemented by adjusting process technology to enable the capacitance of the transistor in the off state to be essentially zero. Another technique is design of the Iimiter circuit 912 to prevent high frequency coupling,

[0087] Referring to FIGURES 1OA and 1OB, circuit diagrams illustrate example embodiments of ϋmiter circuits that may be implemented in a network device. GeneraSly, the iimiter circuits tie a gate (G) of a transistor to a common-mode signal of another iine. Referring to FIGURE 1OA, a Iimiter circuit 1000A comprises a stack of diodes (D1 , D2, . . . . DN tied between input (I) and output (O) terminals. When ail diodes are in an off state, the diodes are inverted due to the potential of an adjacent diode. The Iimiter 1000A essentialiy eliminates cross-coupling even if drain to gate capacitance of the MOSFETs is iarge. Limiter circuit 1000A also includes a disable circuit 1002 that ensures that gates of the fVIOS bridge are turned off for lines that are not powered. FIGURE 1OB illustrates a iimiter circuit 10008 comprising a zener diode, In some embodiments, the limiter circuit 1000B may also be implemented to include disable functionality.

[0088] Referring to FIGURE 11, a schematic functional diagram depicts an embodiment of a network device 1100 that includes an integrated diode bridge 1102 integrated onto an integrated circuit 1104 and coupled directly to lines of a network

connector 1104. The integrated diode bridge 1102 comprises an input side 11141 and an output stde 11140 with the input side coupled to the network connector lines and the output side coupled to at least one power Sine VDD_TC1, VDD_TC2 and at least one ground line GNDJTC 1 , GNDJTC2 Although the illustrative integrated diode bridge 1102 illustratively feeds a T connect, in other embodiments the bridge can be configured to feed another type of power device. The power connection of the bridge circuit through the center tap of the transformer enables a configuration whereby the T connect may be eliminated For example, a powered device may receive power directly such as through a MOSFET bridge, a diode bridge as depicted, or through another type of bridge. [0089] The diode bridge 1102 functions as a power rectifying diode bridge integrated onto the integrated circuit.

[0090] Referring to FIGURE 12, a functiona! circuit diagram illustrates an embodiment of a network device 1200 further comprising a T connect eSement 1212 and an Ethernet physical layer (PHY) moduie 1214 integrated into an integrated circuit 1204. The iliustrative network device 1200 also inciudes rectification diodes that improve pair to pair isolation at the expense of larger area and inclusion of externa! components. The T connect eiement 1212 is adapted to enabie ground potential of the Ethernet PHY module 1214 to float relative to earth ground In the illustrative example, an integrated diode bridge 1202 is integrated onto the integrated circuit 1204 and couples individual lines of a network connector 1208 through an integrated diode into T connect elements 1212.

[0091] The integrated diode bridge 1202 reduces cross-talk between the lines. Combined power and Ethernet signals are fed through diodes of the diode bridge 1202 from each line, in comparison to a MOSFET bridge implementation, the network device 1200 with diode bridges 1202 generally has more T connect circuits 1212 to reduce or minimize cross-talk to a similar levei, and is more iossy due to the voltage drop across the diodes.

[0092] Referring to FIGURE 13, a functional circuit diagram illustrates an embodiment of a network device 1300 including a T connect element 1312 and metal oxide semiconductor (MOS) rectifying components that improve pair to pair isolation at the cost of a greater number of external components. An Ethernet physical layer (PHY) moduie 1314 is integrated into an integrated circuit 1304. An integrated MOSFET bridge 1302 is integrated onto the integrated circuit 1304 and couples individual lines of a network connector 1308 through an integrated diode into T connect eiements 1312, The illustrative network device 1300 eliminates loss associated with rectification and

improves crosstalk performance at the cost of more T connect circuits and external components.

[0093] Referring to FIGURE 14, a schematic circuit diagram illustrates an embodiment of a T connect circuit 1400 that is suitable for usage in a network device, The T connect circuit 1400 eliminates active amplifier control in case high-Q inductors are implemented in a design. With no active amplifier control, resistive feedback with current controls insertion loss. One current removes the threshold component of insertion loss. Another current controls amplification based on the type of signal on the line, either power or Ethernet. The T connect circuit 1400 is a relatively simple design with low power consumption. Elimination of amplifiers improves stability but may affect accuracy of insertion loss controi.

[0094] Referring to FIGURE 15, a schematic circuit diagram depicts an embodiment of a T connect circuit 1500 that is adapted for insertion loss controi, A V τ generator is formed by taking the current difference between V OT + V T and a V 0n circuit. An Ethernet insertion loss controi signal is a programmable current source based on a current, thereby enabling accurate voltage generation when the current is passed through a matching polysilicon resistor.

[OOθδ] According to an embodiment of a network device, an interface is coupled between an Ethernet physical layer (PHY) module and a network connector, and comprises at least one pair of pins coupled to output connections of the Ethernet physicai layer (PHY), a direct current (DC) blocking capacitor coupled to each pin, and a common-mode suppression amplifier coupled between the paired pins.

[0096] In an illustrative architecture of a common-mode suppression circuit, a common-mode suppression amplifier may be added directly to the output lines of a Ethernet physicai layer (PHY).

[0097] The common-mode suppression circuit senses common-mode and may use an amplifier, which only operates in a common-mode sense, to suppress noise from a Ethernet physicai layer (PHY) or any noise from the remainder of a network system.

[0098] In various embodiments, common-mode noise may be sensed directly at the output terminal of the Ethernet physical layer (PHY) , may be sensed at the location of a network connector jack as close as possible to the network line, or may be sensed at any location between the line and the PHY, Typically, sensing of common-mode noise as ciose as possible to the network line is an optimum sensing point, preventing common-mode noise from passing out on the line and enabling maximum noise suppression.

[0099] Referring to FIGURE 16, a schematic block and circuit diagram illustrates an embodiment of a network device 1600 adapted for common-mode noise suppression. The iliustrative network device 1600 comprises an interface 1602 coupled between an Ethernet physical layer (PHY) moduSe 1604 and a network connector 1606. The interface 1602 comprises at ieast one pair of pins 1608 coupled to output connections 1610 of the Ethernet physical layer (PHY) 1604. A direct current (DC) blocking capacitor 1612 is coupled to each pin 1608, A common-mode suppression amplifier 1614 is coupled between the paired pins 1608. In a particular embodiment, the interface 1602 may be a 10/1000fvlbps Ethernet or Gigabit Ethernet with four pair of pins 1608 of which only a single pair is depicted, In other embodiments, the interface may be configured for usage with any suitable communication technology, such as lower frequency or intermediate frequency (SF) wireless, that uses common-mode noise suppression to handle emissions standards as set by trie Federal Communication Commission (FCC) in the United States, Internationa! Special Committee on Radio interference (CiSPR) in Europe, and the like.

[0100] The illustrative interface 1602 includes two additional pins 1608 that couple to the output lines of the PHY 1604. The two lines 1608 are used to sense common-mode noise on the PHY output connections 1610. Pins 1608 can be added at any suitable location tn the interface 1602 to enable sensing of common-mode noise at any position the noise may be emitted. The pins 1608 and the common-mode suppression amplifier 1614 may be independently positioned in a manner that enables efficient processing and reduction or elimination of noise emissions. In other embodiments, the interface 1602 may foe integrated on the same die as the PHY so that additional pins are not needed. Also some embodiments may incorporate emission reduction circuitry integrated with a transmitter/receiver of the PHY.

[0101] The interface 1602 to a Ethernet physical layer (PHY) 1604 includes the extra pins 1608 that enable sensing common-mode noise. The pins 1608 facilitate implementation of an active choke.

[0102] In some embodiments, the network device 1600 may further comprise a control device 1816 coupled to the common-mode suppression amplifier 1614 and the Ethernet physical layer (PHY) 1604. The control device 1616, shown in the illustrative embodiment as an analog~to~digital converter and digital-to-analog converter (ADC/DAC) element, controls the common-mode suppression amplifier 1614 to enable the Ethernet physical layer (PHY) 1604 to set a direct current (DC) vaiue of common-mode voltage and suppress high-frequency common-mode signal components on the paired pins 1608.

[0103] The interface 1602 has the common-mode suppression amplifier 1614 coupled to the output connection 1610 of the Ethernet physical layer (PHY) 1604. The control device 1816 generates a dean or low-noise reference voltage for application to the common-mode suppression amplifier 1614. The common-mode suppression amplifier 1614 may be either DC-coupled or AC-coupled to the Ethernet physical layer (PHY) 1604 so long as a low-noise reference signal is applied to control the amplifier 1614 for comparison to common-mode noise in the system, facilitating suppression of the common-mode noise The reference signal may be called a ground referenced signal that may, for example, be referenced to the ground level in the PHY, [0104] The control device 1618 may generate a reference voltage Vref created by sampling the common-mode voitage at the output terminal of the Ethernet physical layer (PHY) 1604 at a regular, but low frequency, interval and then adjusting a DAC code to be close to the common-mode voltage value. The precise Vref reference is typically unnecessary unless the interface is DC-coupled to the output lines of the PHY, In another embodiment, the control device 1616 may be replaced by a very low frequency lowpass filter, A suitable operation enables the Ethernet physical layer (PHY) 1604 to set the DC value of the common-mode voltage and suppress the high frequency component.

[0105] In a particular implementation, the control device 1616 may sample common- mode voltage at the Ethernet physical layer (PHY) output connections 1610 at regular intervals and adjust an input signal 1618 to the common-mode suppression amplifier 1614 to approximate the common-mode voltage,

[0106] The common-mode suppression circuit 1602 senses common-mode and uses the common-mode suppression amplifier 1614 to suppress noise from a Ethernet physical layer (PHY} or any noise from the remainder of a network system. For example, a network device 1600 with power-over- Ethernet (POE) functionality may include a DC- DC converter to transition from high power signal levels on the network to low voltage electronic or signal handling electronics at the Ethernet physical layer (PHY) 1604. DC- DC converters may generate a relatively large noise signal that is suppressed by the common-mode suppression circuit 1602.

[0107] In some configurations, the control device 1616 may be direct-current (decoupled to the Ethernet physical layer (PHY) 1604 and may adjust a control signal 1618 to the common-mode suppression amplifier 1614 to adjust common-mode of the common-mode amplifier 1614 at an amplitude that avoids overdriving. In other arrangements, the control device 1616 may be alternating-current (ac)-couρ!ed to the

Ethernet physical layer (PHY) 1604 and adjust the control signal 1618 to the common- mode suppression amplifier 1614 to suppress common-mode noise. The control device 1816 may be configured to set common-mode direct current (dc) voltage and suppress common-mode noise above a designated frequency. [010S] The illustrative network device 1600 includes a common-mode suppression amplifier 1614 that is separated from an integrated circuit containing the Ethernet physica! layer (PHY) 1604,

[0109] In some embodiments, the common-mode suppression amplifier 1614 may comprise a bandpass filter. For example, in a configuration that the Ethernet physica! layer (PHY) 1604 uses inductors. AC coupling may be used on the input terminals to the Ethernet physica! layer (PHY) 1604 and on a fixed input reference, resulting in the common-mode rejection (CIVlRR) function being operative as a bandpass filter. The common-mode suppression amplifier 1614 may have some bandpass functionality that does not suppress the common-mode at Sow frequencies at the output connection 1610 of the Ethernet physical layer (PHY) 1604 due to AC coupling and, at very high frequencies, due to the finite bandwidth of the amplifier 1614. Accordingly, the common- mode suppression circuit 1602 does not directly couple to the Ethernet physical layer (PHY) 1604 but rather sets common-mode DC voltage and operates to suppress the common-mode noise above a predetermined frequency. [0110] In other embodiments, the common-mode suppression amplifier 1614 may comprise iowpass filter functionality when DC coupled to the output of the PHY 1 although low-frequency noise added after the DC blocking capacitance cannot be suppressed.

[0111] In the illustrative embodiment, the common-mode suppression amplifier 1614 is coupled to the paired pins 1608 between the DC blocking capacitors 1612 and the Ethernet physical iayer (PHY) output connections 1610.

[0112] FJGURE 16 illustrates dashed lines 1620 depicting AC coupling of the network connector 1608 to the common-mode suppression circuit 1802. The sense line 1620 for sensing common-mode noise is coupled to the opposing side of the DC blocking capacitors 1612 with respect to the common-mode suppression amplifier 1614 to facilitate sensing the common-mode noise emitted out to the network line. To ensure suppression of noise closest to the network connector 1606, the interface 1602 is configured to sense on the opposite side of the DC blocking capacitors 1612 from the Ethernet physical layer (PHY) 1604 thereby suppressing the common-mode noise before the noise can be emitted to the line.

[0113] Referring to FIGURE 17A, a schematic block and circuit diagram illustrates an embodiment of a network system 1700 comprising a network interface 1702 coupled between a Ethernet physical layer (PHY) module 1704, a network connector 1706, and a T connect integrated circuit 1720. [0114j The system 1700 includes a network device comprising the network interface 1702 coupled between the Ethernet physical layer (PHY) module 1704 and a network connector 1706 that is operative at a voltage substantially higher than the voltage at which the PHY module 1704 operates. The interface 1702 is configured to pass signals from a relatively high voltage technology at the network connector 1706 to a relatively low voltage technology at the PHY module 1704, The interface 1702 senses common- mode noise in a high voltage technology region 1722 adjacent to the network connector 1706 suppresses the common-mode noise in a low voltage technology region 1724 adjacent to the PHY module 1704.

[0115] The illustrative network system 1700 may further comprise networks 1730 coupled between the paired pins 1708. Networks 1730 may be used to facilitate PHY operation in interfaces that do not contain a transformer and to comply with return loss specifications in the integrated circuit 1720.

[0116] The network interface 1702 is shown AC coupled into the Ethernet physical layer (PHY) 1704. A pin interface includes two pins 1708 tied to the output of the Ethernet physical layer (PHY) that function to suppress common-mode noise. The pin connections 1708 include one set of pins coupled to L lines in the integrated connect circuit 1720 that connect to the T connect circuit. The pin connections 1708 also include a set of pins coupled to TRD lines in the integrated circuit 1720 that couple to a common- mode suppressing circuit. The interface 1702 also has an inductor-resistor-capacitor network 1730 shown adjacent to the blocking capacitors 1712,

[0117] In various implementations, common-mode noise may be sensed either at the pins 1708 or on the other side of the direct-current blocking capacitors 1712, shown as the L1-L8 pins, to suppress noise at the network line. The L1-L8 pins are T connect input pins, for example that couple to the drains of transistors such as the transistors M1- MA shown in FIGURE 19. Inductors on the SCL/SKL pins are the inductors shown in the sources of the transistors M1-M4. Common-mode noise can be sensed closest to the network line by tapping into the interface 1702 on lines that couple the T connect to the network connector 1706. for example lines connected to the L1-L8 pins of the integrated circuit 1720. Tapping the interface 1702 in this manner enables access directly to pins on the network connector 1706 such as an RJ45 connector so that common-mode noise

is sensed very dose to the network line. The common-mode noise is thus sensed at the network Sine and signals are passed internaiiy to the integrated circuit 1720 to a common-mode suppression amplifier in the integrated circuit 1720 which suppresses the common-mode noise at the TRD pins. The configuration enables the interface 1702 to be implemented with different technologies including a Sow voltage technoiogy interna! to the integrated circuit 1720 and a high voltage technology on a separate die. For example, different technologies may be used because trie capacitors function as a coupling network and block high DC voltage so that the capacitors would suitably be implemented in a high voltage die. Signals are sensed at the high voltage region and passed from the high voltage technology on the L1-L8 lines down to a low voltage technology at the TRD lines of the integrated circuit 1720. Output signals from the Ethernet physical layer (PHY) 1704 enable usage of low voltage technology and increased bandwidth to perform common-mode suppression. The T connect integrated circuit 1720 may include a DC-DC converter which has noise that passes through the T connect and exits the line 1706. The common-mode sense circuit 1702 can better suppress the noise if the common-mode noise is sensed on the line side of the DC blocking capacitors 1712.

[0118] FIGURE 17B is a schematic biock and circuit diagram illustrating a further embodiment of a network system 1700. In an illustrative implementation, the low voltage technology region 1724 comprises an integrated circuit 1720 configured in fine-line geometries. A common-mode suppression amplifier 1714 may be fabricated in the low voitage technology region 1724 and adapted to suppress the common-mode noise. The iow voltage region 1724 enables power efficient operation including usage of low-voltage devices. Separation of the common-mode sensing from common-mode suppression further enables division of the interface 1702 into Sow voltage and high voltage regions.

[0119] The interface 1702 may comprise at least one pair of pins 1708 coupled to output connections 1710 of the Ethernet physicaS layer (PHY) 1704 and a common-mode suppression amplifier 1714 coupled between the paired pins 1708,

[0120] A control device 1716 coupled to the common-mode suppression amplifier 1714 and the Ethernet physical layer (PHY) 1704 may be adapted to control the common-mode suppression amplifier 1714, enabling the Ethernet physical layer (PHY) 1704 to set a direct current (DC) value of common-mode voltage and suppress high- frequency common-mode signal components on the paired pins 1708. The control device 1716 may be adapted to sample common-mode voltage at the Ethernet physical iayer (PHY) output connections at regular intervals and adjust input to the common- mode suppression amplifier to approximate the common-mode voltage. Capacitors 1718

coupled to the input Sine to the common-mode suppression amplifier 1714 may be implemented on a high voltage semiconductor die to facilitate blockage of high DC voltage.

[0121] Referring to FIGURES 18A and 1 SB, two schematic circuit and block diagrams illustrate example implementations of a transformer function for usage in a power-over- Ethernet application. FIGURE 18A shows a transformer-based design 1800 whereby power is supplied to an Ethernet physicai layer (PHY) 1804 through a transformer 1806 and the transformer 1806 has an integrated choke that suppresses common-mode noise from the PHY 1804. The integrated choke functions in combination with the transformer 1806 to suppress common-mode noise that creates noise emission.

[0122] FIGURE 18B shows a direct connect design 1820 whereby power is supplied to the Ethernet physicai layer (PHY) 1804 through the direct connect circuit, A T connect circuit 1822 may be implemented to suppress the common-mode noise. The illustrative implementation of the direct connect design 1820 has a choke function 1824 integrated with the T connect 1822. The T connect element 1822 separates a power potential from an Ethernet signal. The choke function 1824 may be integrated into a circuit in combination with the T connect element 1822 so that the T connect performs at least power separation and common-mode noise suppression as elements of a global function. Goals of the choke function include high noise rejection and an equivalent common-mode impedance in a range of less than about an ohm at 100MHz that typically can be attained only by a very high-gain amplifier, In an illustrative implementation, performance of the transformer/choke for common-mode noise rejection (CiVlRR) is approximately 43dB for CMRR (1MHz-30MHz) and about 43-20* log i0 (f/30)dB for CMRR (3OM H z- 100M Hz). Equivalent common-mode resistance for CMRR (1 MHz-SOMHz) is about 0.2ω. Equivalent common-mode resistance for CMRR (30MHz- 100MHz) is about 0.6ω at 100MHz.

[0123] One difficulty with the global integrated circuit architecture arises from a wide difference in voltage at which the different functions optimally operate. Power is supplied over the network so that high voltage signals are supplied at the network connector. The interface separates and supplies the high power suppiy voltages to the PHY element which, in turn, is desired to operate on low voitage : high-speed technology which is much more power efficient than high-voltage technology and generates much less noise. Accordingly, the implementations depicted in F)GUREs 16, 17A, and 17B have the common-mode noise suppression operation separated from the T connection functionality including pins added at any suitabie location in the interface to enable sensing of common-mode noise at any position the noise may be emitted. Independent

positioning of the pins and the common-mode suppression amplifier facilitates efficient processing and reduction or elimination of noise emissions. The pins may be located in high-voltage regions for sensing of noise emissions and the amplifier may be positioned in low-voltage, high-speed regions to enable the amplifier to operate at high speeds and thereby improve common-mode noise suppression.

[0124] The transformer depicted in FJGURE 18A performs various functions in addition to separation of power and Ethernet signals such as filtering. The implementations depicted in FSGUREs 16, 17A, and 17B are adapted to perform similar functionality, for example through inclusion of various filters including the common-mode suppression filtering,

[0125] Referring to FIGURE 19, a schematic circuit diagram iliustrates an embodiment of a T connect integrated circuit 1900 that includes a common-mode suppression circuit 1902 in combination with a T connect circuit 1904 that separates power from Ethernet signals in a power-over-Ethernet (POE) application. In the implementation, inductive/resistive degeneration increases differentia! resistance. The T connect integrated circuit 1900 includes an additional common-mode amplifier 1906 for suppressing common-mode noise. The common-mode suppression circuit 1902 includes an amplifier 1906 for common-mode resistance reduction and an amplifier 1008 for insertion loss control. The illustrative integrated circuit 1900 meets differential resistance specifications easily with minimum insertion loss and conveniently attains desired functionality within a single integrated circuit. A high differentia! resistance specification competes against a specification for low common-mode resistance. The implementation also has difficulty in attaining sufficient common-mode loop bandwidth,

[0128] Referring to FIGURE 20, a schematic block and circuit diagram depicts an embodiment of a system architecture 2000 for the purpose of describing a further difficulty with integrating common-mode rejection with T connect functionality. In the illustrative configuration, for example called a Type B configuration, power is delivered separately from the Ethernet physical layer (PHY) signal so that integrating common- mode rejection into the circuit does not suppress noise from the PHY. In contrast, in a common or Type A configuration power is delivered on the same lines as the PHY signal. Accordingly, since alternative connection schemes may be used, one which supplies power on the same iines as the Ethernet signal and one delivering power on different lines from the Ethernet signal, an integrated circuit that combines T connect and comrnon-rnode suppression would be unable to address both alternatives, possibly calling for design of a second circuit, in a power-over-Ethernet (POE) system which uses a single T connect integrated circuit for alternative A and B configurations, a

condition may result for the B configuration that power can be delivered on non-signal ϋπes. Power ts not delivered on the Ethernet signal lines so that the integrated circuit suppresses common-mode noise on a line that does not carry the Ethernet signal,

[0127] Separating the common-mode rejection functionality from the T connect functionality as shown in FIGURES 16, 1?A. and 17B enables a much simpler design configuration and enables a single design to be used for both Alternative A and Alternative B implementations. The separated implementation avoids requirement for a high efficiency boosting power supply and may be Sβss sensitive to parasitics for the common-mode rejection (GSvIRR) amplifier, although the implementation way have a higher power consumption in the Approach A configuration.

[0128] According to an embodiment of a network device, an active Electro-Magnetic Interference (EMI) suppression circuit is coupled in parallel to transmit and receive differential signal lines connecting an Ethernet physical layer (PHY) module and a network connector, actively suppressing EMI in a network communications system that replaces a traditional transformer with an active direct connect interface,

[0129] In an iliustrative architecture of a common-mode suppression circuit, a common-mode suppression amplifier is coupled to output lines of an Ethernet physical iayer (PHY). An active common mode suppression circuit is coupled in parallel to transmit and receive differential signal lines connecting an Ethernet physical layer (PHY) module and a network connector. In a transformer-less configuration, the circuit can replace electromagnetic interference (EMI) suppression chokes that are included in modern Ethernet transformers.

[0130] Referring to FIGURE 21, a schematic block and circuit diagram illustrates an embodiment of a network device 2100 including a common mode suppression circuit 2102. The common mode suppression circuit 2102 is an active device that is coupled in parallel to transmit and receive differential signal lines 2104T, 2104R connecting an Ethernet physical iayer (PHY) module 2106 and a network connector 2108.

[0131] The common mode suppression circuit 2102 may be described functionally as a shunt choke or choke. The common mode suppression circuit (CMS) 2102 is connected in parallel to the same wires 2104T, 2104R as the Ethernet PHY 2106 whereby the shunt choke terminology is descriptive of the parallel connection. The common mode suppression circuit 2102 operates as a functional biock, coupled in parallel to the signal lines 2104T, 2104R, that supplies a very low common mode impedance termination. Accordingly, substantially all common mode noise in the system is absorbed by the common mode suppression circuit 2102.

[0132] The common mode suppression circuit 2102 performs aspects of a traditional choke 2202 that may be used in conjunction with an Ethernet PHY 2206 as shown in FIGURE 22. The Ethernet PHY 2206 has signal lines coupled to a traditional transformer 2210. The choke 2202 is depicted as horizontal windings coupled to the transformer 2210, The common mode suppression circuit 2102 depicted in FJGURE 21 performs aspects of the choke functionality in active circuitry. The common mode suppression circuit 2102 is configured to interface to standard Ethernet PHY blocks that are traditionally used with transformer-based network devices. Standard Ethernet PHY blocks have C!ass~A drivers that use the transformer center-tap 2212 for direct current (DC) biasing. Accordingly, the standard Ethernet PHY, and not the active choke shunt as may be otherwise be desired, has control of common mode DC voltage at signal lines 2104T and 2104R.

[0133] An Ethernet physical layer (PHY) generally has a Ciass A driver, specifically a driver that operates in a Class A mode whereby differential mode current varies to define a signal while common-mode current component is maintained constant. The Ciass A driver conventionally uses a transformer center-tap for direct current (DC) biasing. In a typica! implementation output common mode DC voltage of the PHY can vary in a range up to the supply voltage Vcc. for example Vcc can be 3.3V, 2,5V, 1,8V, or any voltage desired by the Ethernet PHY manufacturer. The PHY output voltage swing Vout_swing, which is derived from the common mode DC voltage, can also vary greatly, for example from 0.85V to 5.0V depending on supplied power and Ethernet type, for example IObaseT or Fast Ethernet (100baseT} t or Gigabit Ethernet (1000baseT).

[0134] A system with a Class A-B capability typically imposes a power supply voltage specification of more than 5V if the output common mode DC voltage is allowed to a 3.3V ievei. For example, in an implementation of a network device that does not include a Class A output stage on the choke but rather has a more traditional Class A-B output stage, a sufficient and appropriate power supply for the CMS block is greater than 5V because the output swing alone extends from 0.85V to 5.0V, Furthermore, additional headroom above the output swing is also needed in the Ciass AB type design Ciass AB and Class B designs operate off both the ground rail and the power supply or Vcc rail, in contrast, the Class A design is only attached to the ground rail. In the Class A design, no connection couples Vcc to the Ciass A output stage and large voltage swings are more easily tolerated,

[0135] Referring again to FIGURE 21, an example of typical constraints imposed by usage of the Ethernet PHY 2106 include an external load at high frequency is limited by R τ , for example 50ω, Ethernet common mode termination plus parasitic capacitance at

the node. The R τ Ethernet common mode termination, depicted as R τ resistors at input ϋnes to the Ethernet PHY 2106, in combination with parasitic capacitors that typically exist in the system add on the order of 2OpF of shunt loading, In a specific design example, common mode rejection ratio may be specified to a frequency of 100MHz. Consequently, a suitable common mode noise suppression circuit may be specified to inciude a reasonably high loop gain at 100MHz. The specification is addressed by implementing a reasonably high loop gain in the specified frequency range. The common mode noise suppression circuit design includes a fundamental trade-off between loop stability and common mode rejection ratio (CMRR) performance. Accordingly, the shunt choke 2102 is configured to have suifabie high frequency performance to address the loading due to the common mode resistance and parasitic capacitance, in the illustrative example, the loading by a resistance of R τ , for example 5OD, and parasitic capacitance of 2OpF results in a frequency behavior including a pole at 160MHz in combination with a performance specification imposed on the choke of suitable performance up to 100MHz. Thus, in the illustrative example, the design challenge is to configure the common mode suppression circuit 2102 to have very good rejection at 10OiVIHz when limited by a 160MHz poie

[0138] With regard to stability, an analog dosed loop can have stable and nonstable operating zones. For example in a configuration with a poie at 160MHz, good common mode rejection performance imposes specification of a high gain at 100MHz, contrary to a specification to attain loop stability. In an illustrative design, stability criteria may be addressed by enabling the output stage to roil-off while the input stage maintains high gain,

[0137] Referring to FIGURE 23, a schematic circuit and block diagram illustrates an example of system noise coupling paths for emissions that may arise in a network device 2300. The network device 2300 comprises an active common mode suppression circuit 2302 that is configured to absorb common mode noise by forming a low impedance path from an Ethernet Physical layer (PHY) module 2306 output to ground. The Ethernet PHY module 2306 has a Class A driver where output common mode level of the Ethernet PHY module 2306 can vary up to V C c-

[0138] Overall choke functionality addresses highly resonant circuits in all directions including a T connect circuit 2320 with blocking capacitors C 8 , supply inductors L Sl and other sources, In an illustrative example, blocking capacitors C 8 may be selected with a suitable capacitance, for example 68nF, and supply inductors L 5 , in an example configuration selected with inductance Ls, for example 22OuH. The output load condition is highly variable. Thus, the choke 2302 is configured for suitable performance in the

megahertz to gigahertz range. Pin wires, supply inductors, and parasitic capacitances al! may form noise coupling paths to be addressed by the shunt choke 2302.

[0139] Arrows are superimposed on FIGURE 23 showing possible sources of common mode noise. Noise can possibiy propagate from the Vcc power supply path 2330, from the Ethernet PHY 2306, from the ground path 2332, and board and system noise coupling 2334 which is capacitive coupiJng to the line. The board and system noise coupling 2334 is an indirect coupling. Noise coupling paths also may inciude a path 2336 through a DC-DC converter 2322 through the Tconnect biock 2320. The function of the choke 2302 is to operate as a noise absorber that chokes common mode noise and prevents transmission of common mode noise to the Ethernet twisted pair cable that in turn becomes electro-magnetic interference (EMI) emission. The shunt choke 2302 absorbs the common mode noise by forming a very iow impedance path from the Ethernet PHY output terminals to ground so that any common mode noise follows a path of least resistance through the choke 2302 to ground, thereby diverting the noise from the signa! line. Supply Vcc is typically a dominant source of noise, although the noise sourced in relatively variable.

[0140] The shunt choke 2302 can be designed by taking info consideration what noise sources are present, locations of the noise paths, and characteristics, source impedances and worst case conditions of the noise sources. [0141] Referring to FIGURE 24, in an illustrative embodiment a communication device 2400 may be specified to include a Class A driver that operates a common mode suppression circuit coupled to Vcc and ground lines supplying the Ethernet physical iayer (PHY). The communication device is a network device 2400 comprising an interface 2402 coupled in parallel to transmit and receive differential signal lines 2404T 1 2404R connecting an Ethernet physical layer (PHY) module 2406 and a network connector operative at a voltage substantially higher than the PHY module 2406. The interface 2402 comprises a two-stage amplifier gain loop 2408 whereby common mode noise is suppressed, in an example embodiment by at least 4OdB in a frequency range from 100 kHz to 30 MHz. The two-stage amplifier gain loop 2408 comprises a Class A output stage 2410 coupled between the Ethernet PHY and a first stage preamplifier 2412 that is capacitively-coupled at input and output terminals,

[0142] FIGURE 24 illustrates a circuit diagram of the common mode suppression circuit 2402 with additional detail of the circuit and further description of the signal path. Transmit and receive signal Sines TRD+ and TRD- are coupled to output terminals of an Ethernet PHY integrated circuit chip. Transistors 2414P, 2414N in the Ciass A output

stage 2410 include NMOS transistors 2414M coupled between ground and the TRD pins, in the illustrative common mode suppression circuit 2402, no active devices are coupled between the power source Vcc and the output lines. The Class A design is a one-sided, open-drain configuration. The illustrative common mode suppression circuit 2402 includes capacitors that operate as common mode sampling capacitors 2416, Signal cm_Jn is a common mode signal is input to the preamplifier 2412. The preamplifier 2412 drives the output stage 2410, The loop 2408 is closed by the capacitors 2416, Preamplifier 2412 is also coupled into a Sow frequency bias loop or direct current (DC) controi loop 2418 which includes a preamplifier DC (PREDC) amplifier 2420 that functions as a reference amplifier and sets the reference DC voltage. Preamplifier 2412 passes an output signal to a preamplifier output node (PRE_OUT) which is separated from an output stage input node (OSJN) by a signal path capacitor 2422 on a capacitiveiy-coupied signal path. A resistor 2424 and variable capacitors 2428 form a compensation network 2428 and passes to a node ncp, ncn between transistors 2414P, 2414N.

[0143] The illustrative network device 2400 thus comprises an interface 2402 coupled in parallel to transmit and receive differential signal lines 2404T, 2404R connecting an Ethernet physical layer (PHY) module 2406 and a network connector operative at a voltage substantially higher than the PHY moduie 2406. The interface 2402 comprises a two-stage amplifier gain loop 240S 1 a preamplifier loop 2430 coupled to the two-stage amplifier gain loop 2408, a low frequency bias loop 2418 coupled to the preamplifier ioop 2430, a DC filter 2432 coupled to the low frequency bias loop 2418, and common mode sampling capacitors 2416 coupled from an input terminal to the preamplifier ioop 2430 to transmit and receive data (TRD+/-) lines to the Ethernet PHY 2406. The DC filter 2432 and the common mode sampling capacitors 2416 are configured to set iow frequency bias bandwidth.

[0144] The shunt architecture 2402 is not in a series path of the transmit/receive differential signals but rather is in a parallel path with the signals. The parallel or shunt structure facilitates noise elimination. The communication signal includes two component signal types, a common mode signal and a differentia! signal. The differential signal is the desired, information-carrying signal that is sought to be communicated on the signal line. The common mode signal is the noise signal is desired to be prevented from passing down the line. The series connection is susceptible to the risk that both the common mode and the differential signals are processed, resulting in possible distortion of the desired differential component. In

contrast, the parallel shunt configuration avoids processing of the differentia! mode signal, improving differential distortion performance at Sower cost.

[0145] The active common mode suppression circuit 2402 is configured to terminate common mode impedance over the Ethernet signal frequency range, for example typically in a range from about 100 kHz to 100MHz range.

[0148] In some embodiments, the active common mode suppression circuit 2402 can be configured to terminate common mode impedance over an Ethernet signal frequency range whereby common mode noise is suppressed by at ieast 4OdB from 100 kHz to 30 MHz. The active common mode suppression circuit 2402 forms a loop that creates a second-order roll-off in common mode noise suppression at frequencies above 1O kHz.

[0147] In some embodiments, the active common mode suppression circuit 2402 is configured in a Class A architecture that matches Ethernet PHY iine drivers whereby the Ethernet PHY controls output line signal common mode direct current (DC) voltage. The Class A architecture enabies complete control on the output (line signal TRD+/-) common mode DC voltage by the Ethernet PHY 2406.

[0148] The active common mode suppression circuit 2402 and the Ethernet PHY 2408 may be manufactured using the same fabrication process and voltage. Accordingly, the common mode noise suppression circuit 2402 may be fabncated in the same low voitage process as the Ethernet PHY 2406 In contrast, a Class AB type of design may impose a 5 volt fabrication process of more than 5V in contrast to typical 3,3V technologies. The iiiustrative configurations may be suitable for any current or future fabrication processes, voltages, and technoiogies,

[0149] The two-stage amplifier gain loop 2408 enables high common mode suppression performance. For example in some particular configurations, the active common mode suppression circuit 2402 may comprise a two-stage amplifier gain loop 2408 whereby common mode noise is suppressed by at least 4Qd8 ( for example from 10OkHz to 30 MHz.

[0150] An example implementation of the common mode suppression circuit 2402 may be configured so that at zero decibels (dB) on the magnitude axis, nothing is rejected or suppressed. A small amount of peaking at about 3dB occurs at a frequency of about 5 kHz that is essentially immaterial to functionality, A sharp second order roil-off may begin at about 10 kHz and at approximately 100 kHz, the signal may be reduced substantially by approximately -4OdB or more so that at 100 kHz the common mode noise is rejected by 4βdB by the iiiustrative common mode suppression circuit 2402.

From 100 kHz to about 10 MHz, the signal may remain below -4OdB then begins to rise and at about 100MHz, Various standards of performance may be desired but in one embodiment, suppression is most intended for a range from 100 kHz to 100 MHz. Typically, the greatest conductive electromagnetic interference (EMI) difficulty arises in the 100 kHz to 30 MHz range, the range for which performance is optimized in the illustrative common mode suppression circuit 2402. The illustrative common mode suppression circuit 2402 exceeds a rejection specification of 4OdB in the selected range, in summary, a particular implementation may reject from 0 to 4OdB in a band between 10kHz to 10OkHz, have rejection greater than 4OdB in a band from 100kHz to 30MHz, and have over 3OdB rejection from 30MHz to 100MHz.

[0151] In some embodiments, the active common mode suppression circuit 2402 comprises a Ciass A output stage 2410 coupled between the Ethernet PHY 2406 and a first stage preamplifier 2412. The first stage preamplifier 2412 and the Class A output stage 2410 form a two-stage amplifier gain loop 2408. The first stage preamplifier 2412 is completely AC-coupled to the system at both input (CMJN) and output (PREjDUT) terminals The preamplifier 2412 is capacitivβiy-cαupled to the TRD ioop and is capacitiveiy-coupled to the output stage 2410 because neither the range of magnitude of the output common mode nor the voltage Seve! at the TRD node is known. Therefore the two-stage gain ioop 2408 is enabled to float. On the output side of the loop 2408, the common mode suppression circuit 2402 supplies both a bias controi whtch is a separate low frequency bias {DC} control signal, and an alternating current (AC) signal. The AC signal is capacitiveiy-coupled on a separate path, depicted as an output stage bias (OS_B!AS) path, which sets DC biasing for the output stage 2410, The preamplifier 2412 floats and is capacitiveiy-coupled with respect to the TRD+ and TRD- signal lines. The preamplifier 2412 has a dedicated low frequency bias or DC control ioop 2418 for both input and output signals.

[0152] The illustrative preamplifier loop 2430 is designed so that both the AC signal and DC bias are controlled at the same node CMJN, the node at which the DC amplifier 2420 loops back to the input terminals of the preamplifier 2412, [0153] In some embodiments, the network device 2400 may be configured with the active common mode suppression circuit 2402 comprising a two-stage amplifier gain ioop 2408, a preamplifier loop 2430, a low frequency bias ioop 2418, a DC fiiter 2432, and common mode sampling capacitors 2416 coupled from an input terminal (CMJM) to the preamplifier loop 2430 to transmit and receive data (TRD+/-) lines to the Ethernet PHY 2406. The DC filter 2432 and the common mode sampling capacitors 2416 can be configured to set low frequency bias loop bandwidth. A low frequency bias or DC controi

loop amplifier 2420 for the preamplifier 2412 may be designed so that a very low DC loop bandwidth is set by the DC filter 2432 by selection of resistor R D C and capacitor C DC and common mode sampling capacitors 2418 on the node Cmjn. Accordingly, the two- stage amplifier gain loop 2408 progresses from control by the DC amplifier 2420 to the AC portion of the circuit at the output stage 2410 at increasing frequency with a transition at about 10kHz between the iow frequency bias by the DC ioop 2418 and high frequency bias at the output stage 2410. Essentially no common mode rejection is present below about 10 kHz because the iow frequency bias of the DC loop 2418 takes over at lower frequencies. Thus, the active common mode suppression circuit 2402 is configured to transition from direct current (DC) contro! to alternating current (AC) control at a sufficiently iow frequency that AC performance begins at approximately 10kHz, attaining excellent AC performance beginning at 1OkHz

[0154] The DC filter 2432 may be configured to create resonance in the common mode suppression transfer function in a range approximateiy between 100 kHz and 30 MHz, enabling very high common mode noise suppression by at least approximateiy 40 dB and substantially reducing conductive emissions in a band approximately between 100 kHz and 30 MHz. The DC filter 2432 is a resistor-capacitor circuit in the DC loop 2418 coupled to the output terminal of the PREDC amplifier 2420, The Rιχ;C DC circuit that forms the DC filter 2432 in combination with common mode sampling capacitors 2416 comprise a complete AC impedance at node CMJN. The DC filter 2432 and capacitors 2416 set resonance to create the very sharp roll-off in the frequency response to attain common mode rejection of 40 dB to δO dB in the bandwidth of interest, 100 kHz- 30 MHz.

[0155] Low frequency bias or DC control bias at multiple nodes including CMJN node at the input terminal to the preamplifier loop 2430, PREJDUT node at the output terminal of the preamplifier 2412, and OSJN node at the input terminal to the output stage 2410 can all be set independently. Independent setting of DC bias at the multiple nodes enables independent system optimization at each of the nodes to any desired DC level because the nodes are AC decoupled. OSJN node is the bias node for the output stage Class A amplifier output terminal and the DC level set in the OSJN bias path is controlled independently of any other node. At the PR E JDUT node at the output of the preamplifier 2412, the DC level is controlled by the DC_REF path on the PREDC amplifier 2420 and can be set for maximum performance of the preamplifier 2412, The nodes are decoupled because bias for maximum performance of the preamplifier 2412 may not match bias for maximum performance of the output stage 2410. Input bias of

the preamplifier 2412 is set by the Cm_ref node to enable optimization to any bias that produces maximum performance without dependence on the other nodes,

[0156] In some embodiments, an output stage bias loop 2434 coupied between the preamplifier loop 2430 and the Class A output stage 2410 may be configured to set DC current bias in the Class A output stage 2410. The output stage bias loop 2434 is separate from the preamplifier ioop 2430 and operates to set the DC current bias in the class A output stage 2410 through the OSJ3SAS path, enabling very good controi on the DC current through the output stage 2410.

[0157] The two stages of the two-stage amplifier gain loop 2408 comprise the Class A output stage 2410 and the preamplifier loop 2430, The Class A output stage 2410 is configured with separate DC bias and AC signal paths for output bias control. The preamplifier loop 2430 is configured with an AC-coupled output terminal. A programmable ioop compensation technique may be implemented to manage a large variety of output ioad conditions. Because the common mode suppression circuit 2402 is designed for usage with various Ethernet PHY components, the capacttive ioading at the output to the Ethernet PHY is not under controi of the common mode suppression circuit design. The Ethernet PHY capacitive loading may be very smaSi or highly capacitive. for example a range from 5pF to 25pF or even larger ranges. Thus, the common mode suppression circuit 2402 may be configured with a variable compensation ioop that assists operation across a wide range of frequencies and output loading,

[0158] Loop compensation capacitors 2426 may be coupled to the Class A output stage 2410 reduce ioading at the transmit and receive data (TRD+/-) nodes, in another configuration, the compensation capacitors may be connected directly to the output nodes TRD+/-. Connecting the loop compensation capacitors 2426 at the NCP-NCN node as depicted may be desirabie to avoid increasing loading on the Ethernet PHY 2406, enabling a iow capacitance design at the cost of a simple change in ioad size.

[0159] The output stage 2410 may be configured to roli-off at frequency bands at which the preamplifier ioop 2430 remains at high gain.

[0160] Low differentia! capacitance at the output of the common mode suppression circuit 2402 is implemented to avoid degrading of Ethernet signaling performance as well as to maintain good return loss performance.

[0161] The output stage 2410 may be configured with a selected Unity Gain Bandwidth (UGBW) and the preamplifier loop configured with a UGBW at approximately four times the output stage UGBW whereby the output stage output signal rolls-off at frequency bands at which the preamplifier loop remains at high gain In the illustrative

example, the common mode suppression circuit 2402 is terminated with a common mode impedance R τ , for example 50Q 1 with Ethernet Sine termination and approximately 20 pF of capacitive load, setting the primary pole for the loop at 160 MHz. The common mode suppression circuit design enables a compensation technique to cause the output stage to roll-off faster than the preamplifier stage even in presence of Miller compensation in which a capacitor added across an inverting amplifier appears much larger from the input of the amplifier. The compensation technique maintains sufficient common mode noise suppression performance at 100 MHz frequency. The common mode suppression circuit design enables the output stage to roll-off while the input stage remains at high gain.

[0162] In some embodiments, the common mode suppression circuit 2402 may further comprise an output stage gate reference node (OS_GATE) coupled to the Class A output stage 2410 that is configured to be software programmable to accommodate very large signal swings to a V C c range in 10Base-T to 1G008ase-T designs with variable output DC control, in an illustrative embodiment, the output DC control is set by an inductor L 5 or the Ethernet PHY Vcc- The output node can have a large signal swing, for example in a range of approximately 0 85V to 5 OV. Therefore the output stage 2410 is designed to tolerate such signal swings.

[0163] The low frequency bias loop 2418 may be configured to set both input and output common mode voitage of the preamplifier Soop 2430 whereby input common mode control is set by a sum of preamplifier gain and low frequency bias ioop gain and output common mode control is set by low frequency bias loop gam,

[0164] Biasing for the overall system may be designed to enable excellent noise rejection from the power supply paths. For example referring to FiGlIRE 23, noise may be passing through the power supply Vcc path 2330 and through inductors L s , for example 22OuH, and the integrated circuit chip for the interface may also generate a system power supply Vcc. Accordingly, the common mode suppression circuit 2302 may be designed with very good power supply rejection capability to prevent passing power supply noise to the output stage. Thus biasing of the overall system is designed to enable excellent noise rejection from the power supply as well as other noise sources.

[0165] Referring again to FIGURE 24, the common mode suppression circuit 2402 may be designed to absorb common mode noise from Ethernet signaling patrs TRD+ and TRD-, preventing noise to pass to the signal line from Ethernet equipment, thereby controlling electromagnetic interference (EMI) emissions 1 as well as preventing noise passing in from the signal line to impact Ethernet equipment (EIVI! immunity). Thus, the

illustrative common mode suppression circuit 2402 can be designed for EM! emission control to avoid passing noise generated in the interface and the Ethernet PHY 240$ to pass out to the signal line, and for Ey! immunity to prevent noise on the signal Sine from passing to the interface and Ethernet PHY 2406. [0166] The illustrative common mode suppression circuit 2402 may be configured to operate by passing signals from a reiatively high voltage technology at a network connector to a reiatively low voltage technology at an Ethernet physical layer (PHY) module 2408. The common mode suppression circuit 2402 forms a low impedance pathway from an output terminal of the PHY module 2406 to ground that absorbs a common mode noise portion of the signals while enabling a differential portion of the signals to pass. The common mode suppression circuit 2402 also suppresses common mode noise using a two-stage amplifier gain loop 2408,

[0167] The common mode suppression circuit 2402 may further be designed to apply a second order roll-off in a range from approximately 10 kHz to 100 kHz and suppress common mode noise by at least 4OdB in a range from approximately 100 kHz to 30MHz and by at least 3OdB in a range from approximately 30MHz to 100 MHz.

[0168] Referring to FIGURE 25, a schematic block and circuit diagram illustrates an embodiment of a common mode suppression circuit 2502 including a programmable output stage 2510. In an illustrative common mode suppression circuit the output stage 2S10 may be software programmable to meet different EM immunity requirements and specifications for different applications. For example, the multiple independent bias nodes in the common mode suppression circuit effectively result in formation of four output stage amplifiers 2514A-D that are under software control. Some applications may call for different levels of EMi rejection capability. The four output stage amplifiers 2514A-D comprise four segments. The multiple segments enable absorption of more electromagnetic interference (EMl). Different applications of the network device may be configured for different absorption capability. The multiple segments may be individually programmed using programmable switches 2516 The four segments are ali connected to the transmit and receive Sines TRD+/~. [0169] The illustrative common mode suppression circuit 2502 has a two-stage architecture with a preamplifier 2512 and the Class A output stage 2510 that enables a design to be constructed in the same process and voltage as the Ethernet PHY 1 for example 3.3V or 2.5V.

[0170] The illustrative preamplifier 2512 may be completely AOcoupied. The output common mode can vary largely based on the choice of inductive termination.

Accordingly, common mode noise can be reduced by AC coupling the input stage formed by the preamplifier 2512. The class A driver has separate DC and AC paths for output bias control. Accordingly, the preamplifier output is also AC coupled. A separate DC feedback loop is connected around the preamplifier 2512 that conflicts with the AC common-mode rejection loop.

[0171] The illustrative output stage 2510 may be constructed with three blocks including a choke output block (CHOUT) 2514A, a plurality of choke adder blocks (CHADDn) 2514B-D, and a choke pad block (PAD) 2518. The output stage 2510 may be implemented with a wide output swing specification at a final output node, for example between 0.85V and 2.5V,

[0172] The current control capability of the output stage 2510 may be implemented to source and sink large common mode noise currents according to various EMi immunity testing standards, in an illustrative embodiment, the output stage can be designed for current in a range from 12mA to 3OmA in a programmable range of 12/18/24/3OmA. A default may be implemented as 12mA per node. The output device is a fixed electrostatic discharge (ESD) device. Additional amplifiers 2514A-D are summed into the source node.

[0173] Stability of the output stage 2510 can be implemented with Miller compensation in the input device. Class A stage gain drops as common mode load impedance becomes resistive 25ω. The preamplifier 2512 maintains a wide bandwidth and supplies high frequency gain.

[0174] The illustrative common mode suppression circuit enables tuning of the circuit for both low frequency and high frequency performance under various external impedance/resonance constraints. The common mode suppression circuit facilitates replacement of a transformer with transformer equivalent specification.

[0175] A system and method operate to supply a voltage power feed on differentia! cable pairs to network attached powered devices (PD). This voltage power feed from power source equipment (PSE) to PDs substantially addresses the above-identified needs, as well as others, More specifically, various embodiments provide a PSE network device operable to provide a network signal that may include both data and balanced power signals. This PSE network device includes a network connector and an integrated circuit The network connector physically couples the PSE network device to the network. The integrated circuit further includes a power feed circuit. This power feed circuit is operable to draw and balance a plurality of power signals from an isolated power supply. This power feed circuit then may combine and pass the received data

signals and power signal as a single network signal A PSE controller electrically couples to the integrated circuit but is not necessarily part of the integrated circuit. The PSE controller is operable to govern the production and distribution of the power portion of the network signal. [0176] Repiacing the magnetic transformer of prior systems while maintaining the functionality of the transformer has been subsumed into the embodiments of the illustrative system, in order to subsume the functionality of the transformer, the circuits provided by embodiments of the illustrative system, which may take the form of ICs or discrete components, are operable to handle these functions. These functions may include, in the case of an Ethernet network application;

1) coupling of a maximum of 57V to the IC with the possibility of 1V peak- peak swing of a 10/100/1 DOOM Ethernet signaling, (2.8Vp m p for MAU device);

2) splitting or combining the signal; 57V DC to the 802.3af Power Control unit and AC data signal to the PHY (TX and RX), while meeting the high voltage stress.

3) coupling Sower voltage (5v and 3.3v) PHY transceiver to high voltage cable (57V)

4) supplying power of 3,3V or 12V through DC-DC peak converter;

5) withstanding systern-ieveS lighting strikes: indoor lighting strike (ITU K.41); outdoor lighting strike (IEC 60590}

5) withstanding power cross @6GHz (IEC 60590} 7) fully supporting IEEE 802.3af Specification

[0177] Other network protocols may allow different voltage (i.e., a 110 voit circuit coupling to the IC) data rates (i.e., 1 GBPS or higher), power rating. [0178] In a solid-state implementation, common mode isolation between the earth ground of the device and the cable is not necessarily required. Fixed common mode offsets of up to 1500V are possible in traditional telephony systems. Embodiments of the illustrative system deliver power via cable and the earth ground is used solely for grounding of the device chassis. As there is no DC electrical connection between the earth and PoE ground, large voltage offsets are allowable. The PSE side has a data connection which may be optically or capaciiively isolated. The PSE power supply is isolated as well. This isolation will be described with reference to FIGURE 3OB.

[0179] Second, another transformer function provides surge and voltage spike protection from lightning strike and power cross faults. Wires inside the building comply with the !TU recommendation K, 41 for lightning strikes. Lines external to the building

must comply with IEC60950, Lightning strike testing as specified in these Standards consists in a common mode voltage surge applied between ail conductors and the earth or chassis ground. As embodiments of the illustrative system have no DC connection to earth ground, minimal stress wii! occur across the device, thus simplifying the circuits required by embodiments of the illustrative system.

[0180] In the case of 802.3,af, power Is delivered via the center tap of the transmit transformer and receive signal transformers for transformer based designs. The embodiments of the illustrative system may take up to 400ma DC from the common mode of the signal pair without disturbing the AC (1 MHz-100 MHz) differential signals on the transmit/receive pairs,

[0181] Embodiments of the illustrative system are operable to support PoE side applications as well. As several functions are integrated together, the entire IC ground will track the Ethernet Sine ground. This means that the IC potential will vary significantly (1500V) from the chassis ground. As no power is necessary from the local supply, the voltage drop will occur across an air gap.

[0182] FIGURE 26A provides a typical prior art network interface card 2630 for a PD that includes network connector 2632, magnetic transformer 2634 ; Ethernet PHY 2636, power converter 2638, and PD controller 2640, Typically, these elements are all separate and discrete devices. Embodiments of the illustrative system are operable to eliminate the magnetic network transformer 2634 and replace this discrete device with a power feed circuit. This power feed circuit may be implemented within an integrated circuit (IC) or as discrete components. Additionally, embodiments of the illustrative system may incorporate other functional specific processors, or any combination thereof into a single IC. [0183] FIGURE 26B provides a typical PSE prior art device. Here, power sourcing switch 2650 includes a network connector 2632, magnetically coupled transformer 2652, Ethernet physical layer 2654, PSE controller 2656 ; and multi-port switch 2658. Typically these elements are all separate and discreet devices. Embodiments of the illustrative system are operable to eliminate the magnetically coupled transformer 26502 and replace this transformer with discreet devices that may be implemented within SCs or as discreet devices.

[0184] Although the description herein may focus and describe a system and method for coupling high bandwidth data signals and power distribution between the tC and cable that uses transformer-less ICs with particular detail to the 802.3af Ethernet standard, these concepts may be applied in non-Ethernet applications and non 802, 3af

applications. Further, these concepts may be applied in subsequent standards that supersede the 802,3af standard.

[0185] Embodiments of the illustrative system may provide solid state (nonmagnetic) transformer circuits operable to couple high bandwidth data signals and power signals with new mixed-signal SC technology in order to eliminate cumbersome, real- estate intensive magnetic-based transformers 2634 and 2652 as pictured in FJGUREs 26A and 268.

[0186] Modern communication systems use transformers 2834 and 2652 to provide common mode signal blocking, 1500 voit isolation, and AC coupling of the differentia! signature as wei! as residual lightning or electromagnetic shock protection. These functions are replaced by a solid state or other Sike circuits in accordance with embodiments of the illustrative system wherein the circuit may couple directly to the itne and provide high differential impedance and low common mode impedance. High differential impedance allows separation of the PHY signal form the power signal. The low common mode impedance removes the need for a choke. This ailows power to be tapped from the line. The local ground plane may float in order to eliminate the need for 1500 voit isolation. Additionally through a combination of circuit techniques and lightning protection circuitry, it is possible to provide voltage spike or lightning protection to the network attached device. This eliminates another function performed by transformers in traditional systems or arrangements, it should be understood that the technology may be applied anywhere where transformers are used and should not be limited to Ethernet applications.

[0187] Specific embodiments of the illustrative system may be applied to various powered network attached devices or Ethernet network appliances. Such appliances inciude, but are not limited to VoIP telephones, routers, printers, and other like devices known to those having skill in the art. Such exemplary devices are illustrated in FSGURE 1B.

[0188] FIGURE 27A is a functional block diagram of a network interface 2660 that includes network connector 2632, non-magnetic transformer and choke power feed circuitry 2662, network physical layer 2636, and power converter 2638. Thus, FIGURE 27A replaces magnetic transformer 2634 with circuitry 2662. in the context of an Ethernet network interface, network connector 2632 may be a RJ45 connector operable to receive a number of twisted pairs. Protection and conditioning circuitry may be located between network connector 2632 and non-magnetic transformer and choke power feed circuitry 2662 to provide surge protection in the form of voltage spike

protection, lighting protection, externa! shock protection or other like active functions known to those having ski!! in the art. Conditioning circuitry may take the form of a diode bridge or other iike rectifying circuit. Such a diode bridge may couple to individual conductive iines 1-8 contained within the RJ45 connector. These circuits may be discrete components or an integrated circuit within non-magnetic transformer and choke power feed circuitry 2682.

[0189] In an Ethernet application, the 802.3af standard (PoE standard) provides for the delivery of power over Ethernet cables to remotely power devices. The portion of the connection that receives the power may be referred to as the powered device (PD) The side of the link that provides the power is referred to as the power sourcing equipment (PSE). Two power feed options allowed in the 802.3af standard are depicted in FIGURE 28A. Sn the first alternative, which will be referred to as alternative A, LAN switch 2670, which contains PSE 2676 feeds power to the Ethernet network attached device (PD) 2672 along the twisted pair cable 2674 used for the 10/100 Ethernet signal via the center taps 2680 of Ethernet transformers 2682. On the iine side of the transfer, transformers 2684 deliver power to PD 2678 via conductors 1 and 2 and the center taps 2686 and return via conductors 3 and 6 and the center taps 2686 In the second alternative, conductors 4, 5, 7 and 8 are used to transmit power without transformers. Conductors 4, 5, 7 and 8 remain unused for 10/100 Ethernet data signal transmissions. FIGURE 28B depicts that the network interface of FIGURE 27A and power sourcing switch of FIGURE 27S may be used to implements these alternatives and their combinations as well.

[0190] Returning to FIGURE 27A, conductors 1 through 8 of the network connector 2732, when this connector takes the form of an RJ45 connector, couple to non-magnetic transformer and choke power feed circuitry 2762 regardless of whether the first or second alternative provided by 802.3af standard is utilized. These alternatives will be discussed in more detail with reference to FiGUREs 28A and 2SB Non-magnetic transformer and choke power feed circuitry 2862 may utilize the power feed circuit and separates the data signal portion from the power signal portion. This data signal portion may then be passed to network physical iayer 2836 white the power signal is passed to power converter 2838.

[0191] In the instance where network interface 2860 is used to couple the network attached device or PD to an Ethernet network, network physical layer 2836 may be operable to implement the 10 Mbps, 100 Wbps. and/or 1 Gbps physical iayer functions as well as other Ethernet data protocols that may arise. The Ethernet PHY 2836 may additionally couple to an Ethernet media access controller (MAC). The Ethernet PHY 2836 and Ethernet MAC when coupled are operable to implement the hardware layers of

an Ethernet protocol stack. This architecture may also be applied to other networks. Additionally, in the event that a power signa! is not received but a traditional, non-power Ethernet signa! is received the nonmagnetic power feed circuitry 2862 will stiil pass the data signal to the network PHY. [0192] The power signal separated from the network signal within non-magnetic transformer and choke power feed circuit 2862 by the power feed circuit is provided to power converter 2838. Typically the power signal received will not exceed 57 voits SELV (Safety Extra Low Voitage). Typicai voltage in an Ethernet application will be 48- volt power. Power converter 2838 may then further transform the power as a DC to DC converter in order to provide 1.8 to 3.3 volts, or other voltages as may be required by many Ethernet network attached devices.

[0193] FIGURE 27B is a functional block diagram of a power-sourcing switch 2764 that includes network connector 2732, Ethernet or network physical iayer 2754, PSE controller 2756, multi-port switch 2758, and non-magnetic transformer and choke power supply circuitry 2766. FIGURE 278 is similar to that provided in FfGURE 26B 5 wherein the transformer has been replaced with non-magnetic transformer and choke power supply circuitry 2768. This power-sourαng switch may be used to supply power to network attached devices in place of the power source equipment disclosed in FfGURE 26B. [0194] Network interface 2760 and power soυrcing switch 2764 may be applied to an Ethernet application or other network-based applications such as, but not limited to, a vehicle-based network such as those found in an automobile, aircraft, mass transit system, or other like vehicle. Examples of specific vehicle-based networks may include a local interconnect network (LIN), a controller area network (CAN), or a flex ray network. Ai! of these may be applied specifically to automotive networks for the distribution of power and data within the automobile to various monitoring circuits or for the distribution and powering of entertainment devices, such as entertainment systems, video and audio entertainment systems often found in today's vehicles. Other networks may include a high speed data network, low speed data network, time-triggered communication on CAN (TTCAN) network, a J 1939-com pliant network, ISO11898-compliant network, an 1SO1 1519~2~comp!iant network, as well as other like networks known to that having skill in the art. Other embodiments may supply power to network attached devices over alternative networks such as but not limited to a HosrtePNA local area network and other like networks known to those having skill in the art. The HomePNA uses existing phone wires to share a single network connection within a home or building. Alternatively,

embodiments of the illustrative system may be applied where network data signals are provided over power lines.

[0195] Non-magnetic transformer and choke power feed circuitry 2762 and 2766 eliminate the use of magnetic transformers with integrated system solutions that provide the opportunity to increase system density by replacing magnetic transformers 2634 and 2652 with solid state power feed circuitry in the form of an IC or discreet component.

[0196] FiGURE 29A provides an illustration of an embodiment wherein the nonmagnetic transformer and choke power feed circuitry 2962, network physical layer 2936. power distribution management circuitry 2954, and power converter 2938 are integrated into a single integrated circuit as opposed to being discrete components at the printed circuit board level. Optional protection and power conditioning circuitry 2990 may be used to interface the IC to the network connector.

[0197] The Ethernet PHY may support the 10/100/1000 Mbps data rate and other future data networks such as a 10000 ivibps Ethernet network. The non-magnetic transformer and choke power feed circuitry 2962 will supply the line power minus the insertion loss directly to the power converter 2938. This will convert the power first to a 12v supply, then subsequently to the lower supply levels. This circuit may be implemented in the 0,18 or 0.13 micron process or other like process known to those having skill in the art. [0198] The non-magnetic transformer and choke power feed circuitry 2962 implements three main functions: 802.3.af signaling and load compliance, local unregulated supply generation with surge current protection and signal transfer between the line and integrated Ethernet PHY. As the devices are directly connected to the line, the circuit may be required to withstand a secondary lightning surge. [0199] In order for the PoE to be 802.3af standard compliant the PoE may be required to be abie to accept power with either power feeding schemes illustrated in FIGURE 28A and 28B and handle power polarity reversal. A rectifier, such as a diode bridge, or a switching network, may be implemented to ensure power signals having an appropriate polarity are delivered to the nodes of the power feed circuit. Any one of the conductors 1,4.7 or 3 of the network RJ45 connection can forward bias to deliver current and any one of the return diodes connected can forward bias provide a return current path via one of the remaining conductors. Conductors 2, 5, 8 and 4 are connected in a similar fashion.

[0200] The non-magnetic transformer and choke power feed circuitry when applied to PSE may take the form of a single or multiple port switch in order to supply power to

sϊngie or multipie devices attached to the network FIGURE 27B provides a functional block diagram of power soυrcing switch 2764 operable to receive power and data signals and then combine these with power signals, which are then distributed via an attached network. In the case where power sourcing switch 2764 is a gateway or router, a high- speed upiiπk couples to a network such as an Ethernet network or other like network. This data signal is relayed via network PHY 2754 and then provided to non-magnetic transformer and choke power feed circuitry 2766. The PSE switch may be attached to an AC power suppiy or other internal or external power supply in order to provide a power signal to be distributed to network-attached devices that couple to power soυrcing switch 2764. Power controller 2756 within or coupled to non-magnetic transformer and choke power feed circuitry 2766 may determine, in accordance with !EEE standard 802.3af, whether or not a network-attached device, in the case of an Ethernet network- attached device, is a device operable to receive power from power supply equipment. When it is determined in the case of an 802.3af compliant PD is attached to the network, power controller 2756 may supply power from power supply to non-magnettc transformer and choke power feed circuitry 2766, which is then provided to the downstream network- attached device through network connectors, which in the case of the Ethernet network may be an RJ45 receptacle and cable.

[0201] The 802.3af Standard is intended to be fully compliant with all existing non- line powered Ethernet network systems. As a result, the PSE is required to detect via a well defined procedure whether or not the far enά is PoE compliant and classify the amount of needed power prior to applying power to the system. Maximum allowed voltage is 57 volts to stay within the SELV (Safety Extra Low Voltage) limits,

[0202] In order to be backward compatible with non-powered systems the DC voltage applied will begin at a very low voltage and only begin to deliver power after confirmation that a PoE device is present. In the classification phase ; the PSE applies a voltage between 14.5V and 20.5V, measures the current and determines the power class of the device, In one embodiment the current signature is applied for voltages above 12.5V and below 23 Volts. Current signature range is 0-44mA. [0203] The norma! powering mode is switched on when the PSE voltage crosses 42 Volts At this point the power MOSFETs are enabled and the large bypass capacitor begins to charge.

[0204] The maintain power signature is applied in the PoE signature block - a minimum of 10mA and a maximum of 23.5kohms may be required to be applied for the PSE to continue to feed power. The maximum current allowed is limited by the power

class of the device (class 0-3 are defined). For class 0. 12.95W is the maximum power dissipation allowed and 400ma is the maximum peak current Once activated, the PoE will shut down if the applied voltage falls below 30V and disconnect the power MOSFETs from the line. [0205] The power feed devices in normal power mode provide a differentia! open circuit at the Ethernet signal frequencies and a differential short at lower frequencies. The common mode circuit will present the capacitive and power management load at frequencies determined by the gate control circuit.

[0206] FIGURE 3OA provides a functional block diagram of a specific network attached appliance 3092. in this case, the network attached appliance is a VOiP telephone. Network connector 3032 takes form of an Ethernet network connector, such as RJ45 connector, and passes Ethernet signals to power feed circuitry 3062 and PD controller 3040. Non-magnetic transformer and choke power feed circuitry 3062 separates the data signal and power signal. An optional connection to an external isolated power supply allows the network attached device to be powered when insufficient power is available or when more power is required than can be provided over the Ethernet connection. The data signal is provided to network physical layer 3036, Network physical layer 3036 couples to a network MAC to execute the network hardware layer. An application specific processor, such as VOIP processor 3094 or related processors, couples Io the network MAC. Additionally, the VOIP telephone processors and related circuitry (display 3096 and memory 3098 and 3099) may be powered by power converter 3038 using power fed and separated from the network signal by nonmagnetic transformer and choke power feed circuitry 3062. in other embodiments, other network appliances, such as cameras, routers, printers and other like devices known to those having skii! in the art are envisioned.

[0207] FIGURE 6B provides a functional block diagram of a specific network attached PSE device 3093. in this embodiment, PSE network device 3093 is an Ethernet router. Network connector 3032 may take the form of Ethernet network connector such as an Rj-45 connector, and is operabie to distribute Ethernet signals that include both power and data as combined by the integrated circuits within PSE 3093. PSE 3093 includes an integrated circuit 3066 which serves as a nonmagnetic transformer and choke circuit. Various embodiments of the nonmagnetic transformer and choke circuitry will be discussed in further detai! with references to FJGUREs 31 A- 31 B and 32A-32D. PSE network device 3093 also includes PSE controller 3056, Ethernet PHY 3054, isolated power supply 3097, an Ethernet switch 3058, and an optional uplink 3095.

[0208] The 1500 volt isolation between earth ground and the PSE network device may be achieved through various means. The data connections may be capacitiveiy isolated, optically isolated or isolated using a transformer. The power connection is isolated using one or more isolated power supplies [0209] The PSE devices may be a single port or tnulti-port. As a single port this device can aiso be applied to a mid-span application. Data is provided to Ethernet physical layer 3054 either from network devices attached to network connector 3032 or data received from an externa! network via internet switch 3058 and uplink 3095 Ethernet switch 3058 could be an application specific processor or related processors that are operable to couple PSE 3093 via uplink 3095 to an external network.

[0210] PSE devices may be integrated into various switches and routers for enterprise switching applications. However, in non-standard networks e.g. automotive etc., these PSE devices may be integrated into controlier for the attached devices, in the case of multimedia or content distribution, these PSE devices may be incorporated into a controiler/set-top box that distributes content and power to attached devices.

[0211] Nonmagnetic transformer and choke circuitry 3066 receives data from Ethernet physical layer 3054. Additionally, power is supplied to the nonmagnetic transformer and choke circuitry 3086 from isolated power supply 3097. In one embodiment this is a 48-voit power supply. However, this power distribution system may be applied to other power distribution systems, such as 110 voit systems as well, PSE controller 3056 receives the power signal from isolated power supply 3097 and is operable to govern the power signal content within the Ethernet signal supplied by nonmagnetic transformer and choke circuitry 3066. For example, PSE controller 3056 may limit the Ethernet power signal produced by nonmagnetic transformer and choke circuitry 3066 based on the requirements of an attached PD. Thus PSE controller 3056 is operable to ensure that attached network PDs are not overloaded and are given a proper power signal. Power supply 3097 aiso supplies as shown a power signal to Ethernet PHY 3054, Ethernet switch 3058

[0212] The Ethernet switch and optional uplink 95 may be powered by isolated power suppiy 3097 or an optional power suppiy 3097A. When powered by isolated power suppiy 3097, data ground isolation may be provided at uplink 3095 by ground isolation module 3099A, When the optional power suppiy 3097A is utilized, the data connection may be isolated using an isolation moduie that uses optical isolation, capacitive isolation or transformers for isolation.

[0213] Isolated power supply 3097 may be attached to an AC power supply or other interna! or externa! power supply in order to provide a power signal to be distributed to network-attached devices that couple to PSE 3093. PSE controller 3056 may determine, in accordance with IEEE standard 802.3af, whether or not a network-attached device, in the case of an Ethernet-attached device, is a device operable to receive power from power supply equipment. When it is determined that an 802.3af compliant PD is attached to the network, PSE controller 3056 may supply power from power supply 3097 to nonmagnetic transformer and choke circuitry 3066, which is then provided to the downstream network-attached device through network connectors 3032. [0214] The 802, 3af Standard is intended to be fully compliant with all existing non- line powered Ethernet systems. As a result, the PSE network device is required to detect via a wel! defined procedure whether or not the far end network attached device is POE compliant and classify the amount of needed power prior to applying power to the system. Maximum allowed voltage is 57 volts to stay within the SELV (Safety Extra Low Voltage) limits,

[0215] In order to be backward compatible with non-powered systems the DC voltage applied wii! begin at a very low voltage and only begin to deliver power after confirmation that a POE device is present. During classification the PSE network device applies a voltage between 14.5V and 20.5V, and measures the current to determine the power class of the device.

[0216] The PSE network device enters a norma! power supply mode after determining that the PD is ready to receive power, At this point the power MOSFETs are enabled. During the normal power supply mode, a maintain power signature is sensed by the PSE to continue supplying power. The maximum current allowed is limited by the power class of the network attached device,

[0217] The power feed devices in normal power mode provide a differential open circuit at the Ethernet signal frequencies and a differential short at lower frequencies. The common mode circuit will present the capacitive and power management load at frequencies determined by the gate control circuit [0218] In detection/classification and disconnect modes, the power transistors within the IC may be disabled to prevent the loading of the PSE detection circuitry.

[0219] Additional circuits may be used to implement specific functions in accordance with various embodiments of the illustrative system. Various embodiment of power feed circuits within a PSE are provided in FIGURES 31A-31B. FIGURE 31A contains a power feed circuit 3120 located within non-magnetic transformer and choke power feed

circuitry 2966 of FIGURE 298. The Ethernet network (network) power signal produced compiles with alternative A. FIGURE 31 B depicts a power feed circuit located within non-magnetic transformer and choke power feed circuitry 3166 that produces a power signal that complies with alternative B. Other embodiments are possible and will be discussed with reference to FIGURES 33A-33E wherein the various embodiments may comply with alternative A and/or alternative 8 of 802.3af as well as the POE plus standard for higher power applications. The resultant Ethernet signal may be provided via a network connector 3132, such as the RJ45 connector.

[0220] Power is supplied to differential transistor pairs within the non-magnetic transformer and choke power feed circuitry 3066 from power supply 3097. Power supply 3097 may couple to the 48 volt node and ground node within power feed circuit 3120 of FIGURES 31 A and 31 B. Active control circuits 3125 and 3126 may sense the source voltage at the individual transistors via circuit pathways 3107 and 3108. Additionally. active control circuits 3125 and 3126 may sense the drain voltage along line from nodes HP, UN, L2P and L2M This allows the active control circuit 3125 and 3126 to generate control signals 310S, 3106, 3111 and 3112 which are applied to the gates of the transistors. For example, control signals 3105 and 3106 may be applied to the gates of differential transistors M2 and M1 respectively. By sensing these voltages, the active control circuits may balance the power supplied by any individual transistor. Comparing the differential voitage seen as the source of transistors M1 and M2, shown as signals 3107 and 3108 respectively allows active control circuit 3125 to adjust the gate currents 3105 and 3106 to balance the current passed by transistors M1 and M2. in other instances, should an open circuit condition result or a failure of an individual transistor or pathway occur, the active control circuits may allow the remaining transistor and circuit elements to pass a reduced power signal without overloading the remaining circuit elements. Previous solutions would have resulted in an overload condition or power delivery shutdown.

[0221] Individual power signals are provided on U P, U N, L2P, L2N and may combine with data signals supplied on lines 3101 , 3102, 3103 and 3104 by PHY 3128 and 3127. The combined Ethernet signal that contains both data and power is provided over twisted pairs (1, 2) and (3, 6) of the RJ-45 connector in accordance with Alternative A on 802.3af standard.

[0222] The power signal is provided at the input nodes V48 and Gnd of active power control modules 3130 and 3132. UN and L1 P on the receive side and on the transmit side L2N and L2P of the power feed circuit provide the power signal to the network connector. The differentia! transistor pairs are shown as pairs M1 and M2 in active

power control module 3130 and as M3 and SV14 in active power control module 3132. individual Ethernet power signals pass through differentia! transistor pairs M1 or M2 on the receive side and M3 and M4 on the transmit side. The transistors shown may be MOSFET transistors, bipolar transistors, or other like transistors known to those having skill in the art. The power signai received from the power suppiy input nodes pass through sense impedance such as resistor R1 and R2 on the receive side or R3 and R4 on the transmit side. The voltage drop across these impedances is used as an input to the active controi circuits to baiance these circuits.

[0223] Active control circuits 3125 and 3126 may ensure that the power signals passed through the transistors are of equai magnitude or balanced based on other criteria. Active controi circuits 3125 and 3126 are operable to provide common mode suppression, insertion loss control, and current balancing by controlling the gate by control signals 3105. 3106, 3111 and 3112 which ar& applied to the gates of differential transistors M1. fv!2, M3 and M4. Additionally, the active control circuits may provide temperature and ioad contra!, or other signai conditioning functions,

[0224] FSGURE 32 is a schematic diagram that illustrates a power feed circuit 3280 operable to support the power distribution scheme, PoE plus. Power is supplied to differential transistor pairs within the non-magnetic transformer and choke power feed circuitry from an isolated power supply coupled to the 48 volt node (Vdd) and ground node (gnd). These power signals are then distributed to four differential transistor power circuits 3281 3283, 3285 and 3287. As each of these circuits operates in a similar manner, the operation of differential transistor power circuit 3281 will be discussed in detail. Power signals (i.e currents) are drawn through resistors r3 and r4. The currents drawn then pass through differential transistor pair M1 and M2. Although impedances are shown as being purely resistive, these impedances may be a resistor and inductor in parallel or series or other iike complex impedances known to those having skilled tn the art. To ensure that the currents drawn through the differential transistor pair (i e. transistors M1 and M2) are of equai magnitude amplifier A3 may sense the voltage at the source or drain of transistors M1 and M2 to produce a differential component of the feedback signals 3285 and 3286 which are applied by amplifier A3 to the gates of transistors M1 and M2 To ensure that the rectified power signals passed within differential transistor power circuits 3281 and 3283 are of equal magnitude amplifier A9 senses and compares the voltages at node N3 between impedances R5 and R6 of circuit 3281 and node H4 between impedances R11 and R12 of circuit 3283, Inequalities between these voltages wil! indicate an imbalance in the power passed by circuit 3281 as compared to the power passed by circuit 3283. Outputs 3250 and 3252

of amplifier A9 is provided to amplifier A5 which aiso receives input 3239 as measured between impedances R1 and R2. Amplifier A5 is included to provide a fixed OC offset between nodes cnn1 and Vdd.

[0225] Amplifier A3 applies individual control signals (i.e. 3105 and 3108} to the gates of transistors M1 and M2 in order to equalize power feed through the differential transistors within the pair and within pairs. Although not shown, combining circuitry may combine the communication signa! with the power signal and then relay this portion to a coupied Ethernet PHY.

[0226] FIGURES 33A through 33E iliustrate various configurations of common mode suppression and active power control circuits that are compliant with Alternative A, Alternative B, and/or a higher power PoE option (i.e. "PoE plus" operable to deliver power simultaneously over 4 twisted pairs) , and that may support various data rates up to and including gigabyte Ethernet, FIGURE 33A is a 2 twisted pair Alternative A embodiment operable to support 10/10OiVI Ethernet signaling. FIGURE 33A shows an embodiment where the upper power feed circuit 3320 utilizes a single pair of active power control circuits 3330 and 3332 that supply power over two twisted pairs (i.e. (1 , 2) and (3, 6) where twisted pairs (4, 5) and (7, 8) are not used for power and/or data). Thus this first embodiment is compiiant with alternative A. FIGURE 33B is a two twisted pair alternative B embodiment operable to support 10/10OM Ethernet signaling. The second embodiment is complaint with Alternative 8 where Ethernet data signals are provided on twisted pairs (1, 2) and (3, 6) whiie power is provided on twisted pairs (4, 5) and (7, 8), individual twisted pairs in this embodiment are used only to supply power or data but not both.

[0227] FIGURE 33C is a two twisted pair Alternative A embodiment operable to support 10/100/1000!Vi Ethernet signaling, FiGURE 33C increases the data supply with a PHY 3338 operable support gigabyte Ethernet. In this instance twisted pairs (1, 2) are used to supply power and data from power supplied by active power control 3330.

Similarly active power control 3332 provides power over twisted pair (3, 6). Additionally, in order to support increased data rates (i.e. gigabit Ethernet), twisted pairs (1. 2), (3, 6), (4, 5} and (7, 8) all are used to suppiy data as well. This involves the addition of common mode suppression circuits 3340 and 3342 and associated blocking capacitors

C2 through C9 in order to suppiy Ethernet data.

£0228] FIGURE 33D is a four twisted pair operable to support 10/100M Ethernet signaling, in FIGURE 33D the ability to deiiver power over the Ethernet connection is increased by having the ability to deiiver power with additional active power control

modules circuits 3334 and 3336 over the twisted pairs (4, 5) and (7, 8). it should be noted that power oniy is provided over twisted pairs (4, 5) and (7, B). This effectively allows the power supply under Alternative A or Alternative B to be doubted (i.e. PoE plus) by simultaneously delivering power on ail four twisted pairs. [0229] FIGURE 33E is a four twisted pair operable to support 10/100/1 DOOM Ethernet signaling. FIGURE 33E increases both the ability to deiiver power and data. This is achieved by supplying power and data on each Ethernet twisted pair. Active power controi modules 3330, 3332, 3334 and 3336 supply power to twisted pairs (1, 2), (3, 8), (4, 5) and (7, 8) respectively. As shown in FIGURE 33D 1 data is supplied via each twisted pair as previously discussed.

[0230] FIGURE 34 provides a logic flow diagram that illustrates processing associated with at ieast partially powering a network attached device such as an Ethernet device from an Ethernet or network power signal fed through a network or Ethernet connection. This method involves at Step 3490 drawing a number of power signals or currents from at ieast one isolated power source, A first embodiment may draw power that is supplied on two2 twisted pairs to the network, while a second embodiment may draw power on four twisted pairs. The power supply has been previously illustrated as a single power supply 309? in FIGURE 3OB. However, the currents may be drawn from multiple power supplies. For example, the power associated with twisted pairs (1 , 2) and (3, 6) may be drawn from a first power supply while power associated with twisted pairs {4 ; 5) and {7, 8) may be drawn from a second power supply This would offer improved redundancy for PoE applications. The circuitry associated with embodiments of the illustrative system would still be able to balance the current drawn from the isolated power supplies. In the event of a failure of one power supply, the circuitry may adjust the currents of the remaining power supply accordingly to ensure power is provided by the PSE device.

[0231] In step 3492, the currents (i.e. individual power signals) are passed through differential impedances to provide a first differentia! input (i e. the source or drain voltages within a differential transistor pair as sensed in step 3494). Additionally a second differential input results in step 3496 by comparing the average power passed by the power signal of each differential transistor pair. This correlates to comparing the average differentia! drain voltage between differential transistor pairs

[0232] The first and second differential inputs may be combined in step 349S to produce and feed a control signal to the gates of individual transistors. These control signals may be unique to each differentia! transistor. The Ethernet power signal may

then be passed to the network in Step 3499 in order to feed power to an Ethernet or network attached device,

[0233] An illustrative system implements an improved approach to distributing power in a network environment that addresses limitations imposed by magnetic transformers while maintaining the benefits thereof This approach substantially addresses the above- identified needs, as well as others, fvtore specifically, various embodiments provide power feed circuitry within a power over Ethernet (PoE) device that detects fault conditions within power and data distribution Sines coupled to the power feed circuitry. This circuitry includes network interface circuitry coupled to the network in order to exchange both data and power signals. The power interface circuitry also communicatively couples to at least one isolated power supply in order to draw power. The power may then be distributed via the attached network interface circuitry. A fault detection module couples to the power interface circuitry and the network interface circuitry. This fault detection moduie senses fault conditions associated with the power interface circuitry, network interface circuitry, and associated distribution lines in order to better draw and distribute power signals using the power feed circuitry.

[0234] FIGURE 35 illustrates one embodiment of a power feed circuit having a separate fault detection module 3590 in accordance with an embodiment of the illustrative system. Fault detection module 3590 is shown as being separate from active control circuits 3525, However, this functionality may be incorporated within the active control circuits as discussed previously. Fault detection module 3590 may receive the same inputs as are provided to active control circuits 3525 or may sample the control signals 3505 and 3506 generated by active control circuits 3525B as shown here. By comparing signals 3505 &nd 3506 a disparity between the power passed by differentia! transistors M1 and M2 may be determined. An imbalance or difference between the control signals 3505 and 3506 may be used to indicate a fault condition. After identifying the fault condition, fault detection module 3590 may supply an input to active control circuits 3525 that determines how power is to be passed by transistors M1 and M2.

[0235] FIGURE 36 illustrates another embodiment of a power feed circuit having a separate fault detection module in accordance with an embodiment of the illustrative system. Here current mirroring circuit 3692 is used to sample the gate current provided to differention transistor ml The mirrored signal is then processed my fault detection module 3890 to identify fault conditions as determined by comparing the mirror gate signals provided to various differential transistors.

[0236] FIGURE 37 provides a logic flow diagram that illustrates processing associated with at ieast partially powering a network attached device such as an Ethernet device from an Ethernet or network power signal fed through a network or Ethernet connection. This method involves at Step 3700 drawing a number of power signals or currents from at ieast one isolated power source, A first embodiment may draw power that is suppiied on two twisted pairs to the network, while a second embodiment may draw power on four twisted pairs. The power supply has been previously illustrated as a single power supply 309? in FIGURE 3OB. However, the currents may be drawn from multiple power supplies. For example, the power associated with twisted pairs (1, 2) and (3, 6) may be drawn from a first power supply while power associated with twisted pairs (4, 5) and (7, 8) may be drawn from a second power supply. This would offer improved redundancy for PoE applications. The circuitry associated with embodiments of the illustrative system would stii! be able to balance the current drawn from the isolated power supplies, in the event of a failure of one power suppiy : the circuitry may adjust the currents of the remaining power supply accordingly to ensure power is provided by the PSE device.

[0237] In step 3702, the currents (i.e. individual power signals) are passed through impedances to provide a first input (i.e. the source or drain voltages within a differentia! transistor pair as sensed in step 3704). Additionally a second input results in step 3706 by comparing the average power passed by the power signal of each differentia! transistor pair. This correlates to comparing the average differential drain voltage between differentia! transistor pairs. Additionally, these voltages and currents may be examined to determine fault conditions within individual transistors or distribution lines.

[0238] The first and second inputs may be combined in step 3708 to produce and feed a control signal to the gates of individual transistors. These control signals may be unique to each differentia! transistor. The Ethernet power signal may then be passed to the network in Step 3700 in order to feed power to an Ethernet or network attached device.

[0239] In summary, the embodiments of the illustrative system provide power feed circuitry within a power over Ethernet (PoE) device that detects fault conditions within power and data distribution Sines coupled to the power feed circuitry. This circuitry includes network interface circuitry coupled to the network in order to exchange both data and power signals. The power interface circuitry also communicatively couples to at ieast one isolated power supply in order to draw power. The power may then be distributed via the attached network interface circuitry. A fault detection module couples to the power interface circuitry and the network interface circuitry. This fault detection

module senses fault conditions associated with the power interface circuitry, network interface circuitry, and associated distribution lines in order to better draw and distribute power signals using the power feed circuitry.

[0240] Terms "substantially", "essentially" : or "approximately 1 ', that may be used herein, relate to an industry-accepted tolerance to the corresponding term. Such an industry-accepted tolerance ranges from less than one percent to twenty percent and corresponds to, but is not limited to, component va!ues ; integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. The term "coupled", as may be used herein, includes direct coupling and indirect coupling via another component, element, circuit, or module where, for indirect coupling, the intervening component element circuit, or module does not modify the information of a signal but may adjust its current ievei, voltage ievei, and/or power ievei, Inferred coupling, for example where one element is coupled to another element by inference, includes direct and indirect coupling between two elements in the same manner as "coupled".

[0241] While the present disclosure describes various embodiments, these embodiments are to be understood as illustrative and do not limit the claim scope. Many variations, modifications, additions and improvements of the described embodiments are possibie. For example, those having ordinary skill in the art wili readily implement the steps necessary to provide the structures and methods disclosed herein, and will understand that the process parameters, materials, and dimensions are given by way of example only. The parameters, materials, and dimensions can be varied to achieve the desired structure as well as modifications, which are within the scope of the claims. Variations and modifications of the embodiments disclosed herein may also be made while remaining within the scope of the following claims. For example, various aspects or portions of a network interface are described including several optional implementations for particular portions. Any suitable combination or permutation of the disclosed designs may be implemented.