Title:
NEURAL ELECTRONIC CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/155910
Kind Code:
A1
Abstract:
Provided is a neural electronic circuit for realizing a neural network capable of dealing with multiple-bit data while reducing the size of the electronic circuit. The neural electronic circuit is provided with: storage units (MC) that each store a logarithmic weighting coefficient, which represents, in multiple bits, a value resulting from logarithmizing a weighting coefficient corresponding to input data to be inputted, and that outputs the logarithmic weighting coefficient on a bit-by-bit basis; first electronic circuit units (Pe) that each output a multiplication result of the input data and the weighting coefficient; and a second electronic circuit units (Act) that each realize an addition/application function of adding the multiplication results, applying an activation function to the addition result, and outputting output data. In the neural electronic circuit, logarithmic input data, which represents, in multiple bits, a value resulting from logarithmizing the input data, is received on a bit-by-bit basis, logarithmic addition is calculated by adding the logarithmic input data and the logarithmic weighting coefficient outputted from the storage unit, a multiplication result is calculated by linearizing the logarithmic addition result, and the logarithmized output data is outputted.
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Inventors:
TAKAMAEDA SHINYA (JP)
UEYOSHI KODAI (JP)
MOTOMURA MASATO (JP)
UEYOSHI KODAI (JP)
MOTOMURA MASATO (JP)
Application Number:
PCT/JP2019/002455
Publication Date:
August 15, 2019
Filing Date:
January 25, 2019
Export Citation:
Assignee:
UNIV HOKKAIDO NAT UNIV CORP (JP)
International Classes:
G06N3/063
Foreign References:
| JPH07210534A | 1995-08-11 |
Attorney, Agent or Firm:
INTECT INTERNATIONAL PATENT OFFICE et al. (JP)
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