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Title:
NEURAL NETWORK ARITHMETIC CIRCUIT USING NON-VOLATILE SEMICONDUCTOR MEMORY ELEMENT
Document Type and Number:
WIPO Patent Application WO/2019/049741
Kind Code:
A1
Abstract:
A neural network arithmetic circuit for outputting output data (y) in accordance with the results of a multiply-add operation performed on input data (x0-xn) and connection weight coefficients (w0-wn), wherein the neural network arithmetic circuit is provided with arithmetic units (PU0-PUn) each comprising a non-volatile semiconductor memory element (RP) and cell transistor (T0) connected in series between data lines (BL0, SL0), a non-volatile semiconductor memory element (RN) and cell transistor (T1) connected in series between data lines (BL1, SL1), and a word line (WL0-WLn) connected to the gates of the cell transistors (T0, T1), connection weight coefficients (w0-wn) are stored in the RPs and Rns, a word line selection circuit (30) sets WL0-WLn to a selected state or non-selected state in accordance with xo-xn, and a determination circuit (50) determines the values of the currents flowing through BL0 and BL1 and accordingly outputs the output data (y).

Inventors:
KOUNO, Kazuyuki
ONO, Takashi
NAKAYAMA, Masayoshi
MOCHIDA, Reiji
HAYATA, Yuriko
Application Number:
JP2018/031899
Publication Date:
March 14, 2019
Filing Date:
August 29, 2018
Export Citation:
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Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
International Classes:
G11C11/54; G06G7/60; G06N3/063
Attorney, Agent or Firm:
NII, Hiromori et al. (6F Tanaka Ito Pia Shin-Osaka Bldg., 3-10, Nishi Nakajima 5-chome, Yodogawa-ku, Osaka-cit, Osaka 11, 〒5320011, JP)
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