Title:
NEURAL NETWORK CIRCUIT DEVICE, NEURAL NETWORK PROCESSING METHOD, AND NEURAL NETWORK EXECUTION PROGRAM
Document Type and Number:
WIPO Patent Application WO/2020/158760
Kind Code:
A1
Abstract:
In a neural network circuit device (50), an intermediate layer comprises a noise convolution computation circuit (100) for computing noise convolution. The noise convolution computation circuit (100) comprises: a noise generation circuit (110) that generates noise nc; an addition circuit (120) that accepts an input value X for executing a 1×1 convolution, and adds the noise nc generated by the noise generation circuit (110) to the input value X; and a multiplication circuit (130) that accepts a weighting W, and multiplies the noise-including noise convolution computation value, from the addition circuit (120), by the weighting W.
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Inventors:
NAKAHARA HIROKI (JP)
Application Number:
PCT/JP2020/003049
Publication Date:
August 06, 2020
Filing Date:
January 28, 2020
Export Citation:
Assignee:
TOKYO INST TECH (JP)
International Classes:
G06T1/40; G06N3/063
Other References:
MUNAKATA, ATSUKI: "A CNN with a Noise Addition for Efficient Implementation on an FPGA", IEICE TECHNICAL REPORT VLD2018-72-VLD2018-92 VLSI DESIGN TECHNOLOGIES, vol. 118, no. 430, 23 January 2019 (2019-01-23), pages 19 - 24, ISSN: 0913-5685
Attorney, Agent or Firm:
ISONO INTERNATIONAL PATENT OFFICE, P.C. (JP)
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