Title:
NEURAL NETWORK CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/189895
Kind Code:
A1
Abstract:
Provided is a further optimized neural network circuit device. A synapse circuit 11 is formed of a pair of cross-coupled inverters 21, 22 and stores a synaptic coupling weight in a non-volatile manner. The inverter 21 is a series connection of an MTJ element 31 and a MOS transistor 32, and the inverter 22 is a series connection of an MTJ element 33 and a MOS transistor 34. In response to the input of a first pre-spike pulse, the voltage at a connection node SN is output as a voltage signal Vpre. A neuron circuit is formed of a pair of MOS transistors and a pulse generator, wherein the pair of MOS transistors have a floating gate and a plurality of control gates capacitively coupled to the floating gate. A first post-spike pulse is output when the sum of voltages of the voltage signal Vpre has become greater than or equal to a certain level.
Inventors:
MA YITAO (JP)
ENDOH TETSUO (JP)
ENDOH TETSUO (JP)
Application Number:
PCT/JP2019/014353
Publication Date:
October 03, 2019
Filing Date:
March 29, 2019
Export Citation:
Assignee:
UNIV TOHOKU (JP)
International Classes:
G06N3/063; G11C11/54; G11C11/16; H01L21/8239; H01L27/105; H01L43/08
Domestic Patent References:
| WO2015041305A1 | 2015-03-26 |
Foreign References:
| JP2010146514A | 2010-07-01 | |||
| JPH07161942A | 1995-06-23 |
Attorney, Agent or Firm:
DORAIT IP LAW FIRM (JP)
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