Title:
NEURAL NETWORK CIRCUIT AND NEURAL NETWORK INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/200088
Kind Code:
A1
Abstract:
The purpose of the present invention is to provide an efficient and versatile neural network circuit while significantly reducing the size and cost of the circuit. The neural network circuit comprises: memory cells 1 which are provided in the same number as that of pieces of input data I, and each of which performs a multiplication function by which each piece of input data I consisting of one bit is multiplied by a weighting coefficient W; and a majority determination circuit 2 for performing an addition/application function by which the multiplication results of the memory cells 1 are added up, an activation function is applied to the addition result, and a piece of one-bit output data is outputted. Each of the memory cells stores the weighting coefficient, which is either "1" or "0," or "NC," whereby the memory cell outputs "1" when the piece of input data I is equal to the value stored therein, "0" when the value of the input data I is not equal to the value stored therein, or "NC" when "NC" is stored therein. The majority determination circuit 2 outputs "1" or "0" on the basis of the total number of memory cells 1 outputting "1" and the total number of memory cells 1 outputting "0."
Inventors:
MOTOMURA MASATO (JP)
Application Number:
PCT/JP2017/018836
Publication Date:
November 23, 2017
Filing Date:
May 19, 2017
Export Citation:
Assignee:
UNIV HOKKAIDO NAT UNIV CORP (JP)
International Classes:
G06N3/063
Foreign References:
| JPH0896138A | 1996-04-12 | |||
| JP2015534172A | 2015-11-26 |
Attorney, Agent or Firm:
INTECT INTERNATIONAL PATENT OFFICE et al. (JP)
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