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Patent Searching and Data


Title:
NEURAL NETWORK COMPUTATION CIRCUIT USING SEMICONDUCTOR STORAGE ELEMENT
Document Type and Number:
WIPO Patent Application WO/2019/049654
Kind Code:
A1
Abstract:
A neural network computation circuit comprising an in-area word line multiple selection circuit for logically segmenting a plurality of word lines of a memory array (10) into a plurality of word line areas and making a given word line selected or unselected for each of the word line areas. The in-area word line multiple selection circuit comprises a first latch (31) and a second latch (32) for each of the word lines.

Inventors:
NAKAYAMA, Masayoshi
KOUNO, Kazuyuki
HAYATA, Yuriko
ONO, Takashi
MOCHIDA, Reiji
Application Number:
JP2018/030862
Publication Date:
March 14, 2019
Filing Date:
August 21, 2018
Export Citation:
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Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
International Classes:
G06N3/063; G06G7/60; G11C11/54
Foreign References:
JPH0628331A1994-02-04
US5371834A1994-12-06
JPH0454685A1992-02-21
JPH05282269A1993-10-29
Attorney, Agent or Firm:
NII, Hiromori et al. (6F Tanaka Ito Pia Shin-Osaka Bldg., 3-10, Nishi Nakajima 5-chome, Yodogawa-ku, Osaka-cit, Osaka 11, 〒5320011, JP)
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