NEURAL NETWORK COMPUTATION CIRCUIT USING SEMICONDUCTOR STORAGE ELEMENT

Title:

NEURAL NETWORK COMPUTATION CIRCUIT USING SEMICONDUCTOR STORAGE ELEMENT

Document Type and Number:

WIPO Patent Application WO/2019/049654

Kind Code:

A1

Abstract:

A neural network computation circuit comprising an in-area word line multiple selection circuit for logically segmenting a plurality of word lines of a memory array (10) into a plurality of word line areas and making a given word line selected or unselected for each of the word line areas. The in-area word line multiple selection circuit comprises a first latch (31) and a second latch (32) for each of the word lines.

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Inventors:

NAKAYAMA MASAYOSHI
KOUNO KAZUYUKI
HAYATA YURIKO
ONO TAKASHI
MOCHIDA REIJI

Application Number:

PCT/JP2018/030862

Publication Date:

March 14, 2019

Filing Date:

August 21, 2018

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Assignee:

PANASONIC CORP (JP)

International Classes:

G06N3/063; G06G7/60; G11C11/54

Foreign References:

JPH0628331A	1994-02-04
US5371834A	1994-12-06
JPH0454685A	1992-02-21
JPH05282269A	1993-10-29

Attorney, Agent or Firm:

NII, Hiromori et al. (JP)

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