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Title:
NEURAL NETWORK COMPUTATION CIRCUIT USING SEMICONDUCTOR STORAGE ELEMENT, AND OPERATION METHOD
Document Type and Number:
WIPO Patent Application WO/2019/049686
Kind Code:
A1
Abstract:
A combining weight coefficient used in neural network computation is stored in a memory array (20), a word line (22) corresponding to the input data of a neural network is driven by a word line drive circuit (24), and a bit line to which is connected a combining weight coefficient to be computed by a column selection circuit (25) is connected to a computation circuit (26), with a sum total of cell currents flowing in the bit line (23) determined by the computation circuit (26). The determination result of the computation circuit (26) is preserved in an output-holding circuit (27), and is set to the word line drive circuit (24) as input to a neural network of the next layer. A control circuit (29) indicates, on the basis of information held in a network configuration information-holding circuit (28), to the word line drive circuit (24) and the column selection circuit (25) that the word line (22) and the bit line (23) used in neural network computation be selected.

Inventors:
HAYATA, Yuriko
KOUNO, Kazuyuki
NAKAYAMA, Masayoshi
MOCHIDA, Reiji
ONO, Takashi
SUWA, Hitoshi
Application Number:
JP2018/031298
Publication Date:
March 14, 2019
Filing Date:
August 24, 2018
Export Citation:
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Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
International Classes:
G06N3/063; G06G7/60; G11C11/54
Foreign References:
JPH0628331A1994-02-04
US5371834A1994-12-06
JPH0454685A1992-02-21
JPH05282269A1993-10-29
Attorney, Agent or Firm:
NII, Hiromori et al. (6F Tanaka Ito Pia Shin-Osaka Bldg., 3-10, Nishi Nakajima 5-chome, Yodogawa-ku, Osaka-cit, Osaka 11, 〒5320011, JP)
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