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Title:
NEURAL NETWORK COMPUTATION CIRCUIT USING NON-VOLATILE SEMCONDUCTOR STORAGE ELEMENT
Document Type and Number:
WIPO Patent Application WO/2019/049842
Kind Code:
A1
Abstract:
Provided is a neural network computation circuit capable of outputting output data according to the result of a multiply-accumulate operation performed on input data and connection weight coefficients, said circuit comprising a computation unit having: storage elements RP and transistors T0 connected in series between data lines BL0, SL0; storage elements RN and transistors T1 connected in series between data lines BL1, SL1; and word lines connected to the gates of the transistors T0, T1. Connection weight coefficients w0-wn are stored in the storage elements RP, RN, a word line selection circuit (30) sets word lines WL0-WLn to either the selected or non-selected state according to input data x0-xn, and an assessment circuit (50) assesses current values flowing through the BL0, BL1, whereby output data is outputted. A current application circuit (100) has a function of adjusting the current values flowing through the BL0, BL1 and adjusts the connection weight coefficients without overwriting the storage elements RP, RN.

Inventors:
MOCHIDA, Reiji
KOUNO, Kazuyuki
HAYATA, Yuriko
ONO, Takashi
NAKAYAMA, Masayoshi
Application Number:
JP2018/032676
Publication Date:
March 14, 2019
Filing Date:
September 03, 2018
Export Citation:
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Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
International Classes:
G06N3/063; G06G7/60; G11C11/54
Foreign References:
US5256911A1993-10-26
JPH05264645A1993-10-12
US5155802A1992-10-13
US20080172385A12008-07-17
JPH06131487A1994-05-13
JPH0628331A1994-02-04
Attorney, Agent or Firm:
NII, Hiromori et al. (6F Tanaka Ito Pia Shin-Osaka Bldg., 3-10, Nishi Nakajima 5-chome, Yodogawa-ku, Osaka-cit, Osaka 11, 〒5320011, JP)
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