Title:
NEUROMORPHIC SYSTEM USING MEMORY ARRAY WITH CROSS-POINT STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2022/163883
Kind Code:
A1
Abstract:
An object of the present invention is to provide a neuromorphic system including a synaptic unit capable of causing a gradual change in resistance for analog information processing, and an operating method therefor. In order to achieve the above object, an aspect of the present invention may provide a neuromorphic system comprising: an input signal unit for generating an input signal; a synapse unit comprising a plurality of synaptic units that receive a signal of the input signal unit and pass a current according to a set weight; an output signal unit for generating an output signal in response to receiving a current generated from the synapse unit; and a controller unit for controlling the input signal unit, the synapse unit, and the output signal unit, wherein the input signal unit comprises a digital-to-analog converter (DAC), the synaptic units include a plurality of memory cells which are connected to each other and are each capable of selectively storing a logic state, wherein the plurality of memory cells are arranged in a cross-point structure including an input electrode line and an output electrode line which cross each other, so as to form one or more memory arrays, the output signal unit includes an analog-to-digital converter (ADC), and the controller unit generates an analog input signal from the input signal unit through the DAC, allows the generated analog input signal to be applied to the plurality of memory cells included in the synapse unit to flow a current, and generates, as an output signal from the output signal through the ADC, a sum of currents flowing from the plurality of memory cells.
Inventors:
KIM JUN-SUNG (US)
YOON SANG-HOON (KR)
YOON SANG-HOON (KR)
Application Number:
PCT/KR2021/001221
Publication Date:
August 04, 2022
Filing Date:
January 29, 2021
Export Citation:
Assignee:
KIM JUN SUNG (US)
International Classes:
G06N3/063; G06N3/04; G11C11/54; G11C13/00
Foreign References:
| JP6818116B1 | 2021-01-20 | |||
| KR20210000987A | 2021-01-06 | |||
| KR101997868B1 | 2019-07-09 |
Other References:
LOAI DANIAL, EVGENY PIKHAY, ERIC HERBELIN, NICOLAS WAINSTEIN, VASU GUPTA , NIMROD WALD, YAKOV ROIZIN, RAMEZ DANIEL, SHAHAR KVATINS: "Two-terminal floating-gate transistors with a low-power memristive operation mode for analogue neuromorphic computing. ", NATURE ELECTRONICS ARTICLE., vol. 2, 9 December 2019 (2019-12-09), XP055955431
GUO X.; BAYAT F. MERRIKH; PREZIOSO M.; CHEN Y.; NGUYEN B.; DO N.; STRUKOV D. B.: "Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells", 2017 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), IEEE, 30 April 2017 (2017-04-30), pages 1 - 4, XP033130561, DOI: 10.1109/CICC.2017.7993628
GUO X.; BAYAT F. MERRIKH; PREZIOSO M.; CHEN Y.; NGUYEN B.; DO N.; STRUKOV D. B.: "Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells", 2017 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), IEEE, 30 April 2017 (2017-04-30), pages 1 - 4, XP033130561, DOI: 10.1109/CICC.2017.7993628
Attorney, Agent or Firm:
IAM PATENT FIRM (KR)
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