BACKGROUND

Field

Integrated circuit processing.

Description of Related Art

Dielectric oxides based on a lanthanide oxide (Ln ₂ 0 ), where Ln is a lanthanide metal are promising materials as gate insulators in state-of-the-art high-speed transistors, as well as ultrathin gate interlayers in the integration of new channel materials. However, most current lanthanide precursors lack the desired high volatility, high reactivity and long term thermal stability necessary for ALD processing.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a synthesis scheme for forming an amidine ligand operable to complex with a lanthanide to form an ALD precursor.

Figure 2 illustrates a synthesis scheme for forming an ALD precursor including a lanthanide complexed with amidine ligands of Figure 1.

Figure 3 shows a schematic of a representative deposition system.

Figure 4 illustrates a schematic representation of a method of depositing a silicon nitride film or layer on a substrate by an ALD process.

Figure 5 shows a cross-sectional side view of an embodiment of a semiconductor device structure including a silicon carbide dielectric film.

Figure 6 is an interposer implementing one or more embodiments.

Figure 7 illustrates an embodiment of a computing device.

DETAILED DESCRIPTION

A lanthanide composition is disclosed that in one aspect is suitable as a precursor for a dielectric material in integrated circuit processing such as a precursor for an atomic layer deposition (ALD) of thin conformal films of lanthanide oxides and sulfides for device applications. A method of forming a lanthanide composition is also disclosed as is a method of forming a dielectric film on an integrated circuit device.

In one embodiment, a lanthanide composition as the general formula of General Formula I:

wherein Ri is selected from a Ci-C ₆ alkyl, a dialkylamino group and an organic amido group, R ₂ and R ₃ are individually selected from a Ci-C ₆ alkyl (i.e., R ₂ and R ₃ may or may not be the same) and Ln is a lanthanide selected from yttrium (Y), ytterbium (Yb) and lutetium (Lu). In another embodiment, R ₂ and R ₃ are individually selected from Ci-C ₂ alkyl and may be symmetrical (R ₂ and R ₃ are the same) or unsymmetrical (e.g., R ₂ is a methyl and R ₃ is an ethyl. When R ₂ is a methyl and R ₃ is an ethyl, the lanthanide composition of General Formula I has the following formula:

The composition may be referred to as an organic-lanthanide complex including two lanthanides (Y, Yb, Lu) and an organic ligand or ligands.

Examples of Ci-C ₆ alkyls include straight or branched chain alkyls (e.g., methyl, ethyl, propyl, isopropyl). In one embodiment, Ri is a methyl. Examples of dialkylamino groups include Ci-C ₆ dialkylamino groups where such alkyl may or may not be similar. Specific examples include, but are not limited to dimethyl amino, diethyl amino, and methyl- ethyl amino. Representative organic amido groups include those having the formula - CONH ₂ , -CONHR ₃ , and -CONR ₃ R4, where R ₃ and R ₄ are each independently a Ci-C ₆ alkyl (i.e., R ₃ and R4 may or may not be the same). In one embodiment, the composition having the formula of General Formula I may be used as a precursor in an atomic layer disposition (ALD) process to form a dielectric material, particularly a dielectric material having a dielectric constant greater than a dielectric constant of silicon dioxide (a high-k dielectric material). Generally, an ALD process is a self-limiting thin film growth process in which a heated substrate may be exposed to one or more precursors to form a thin film from the precursor(s). The heated substrate may be exposed to one or more co-reactants in addition to the one or more precursors. For example, the heated substrate may be exposed to the co-reactant(s) in a separate operation from the exposure to the one or more precursors. In some embodiments, the exposure to the precursor(s) and/or co-reactant(s) may be repeated (e.g., additional precursor and/or co- reactant may be added in a sequential manner). The precursor(s) and/or co-reactant(s) both may be in a gas phase when exposed to the heated substrate. The ALD process may also be characterized as self-limiting because a reaction stops after all reactive sites of a precursor are reacted. The ALD process may also be characterized by highly conformal and uniform, self- limited film growth, which allows for control of ultrathin (e.g., less than 300 A) film deposition at relatively low temperatures (80-450°C, depending on precursor characteristics).

To form a thin film of a lanthanide oxide or sulfide on a semiconductor substrate via deposition processes, selected materials may be used including precursors, co-reactants, and/or gases. The precursors generally are comprised of the lanthanide (e.g., Y, Yb, Lu) complexed with an organic compound that may be referred to as a ligand. To form the organic-metal complex, the ligand needs to have certain bonding abilities that allow it to coordinate with a lanthanide. The number of ligands coordinated with a selected lanthanide depends on the coordination number of the lanthanide. For example, a complex may include numerous ligands for each lanthanide atom, depending on the coordination number of the lanthanide.

Ligands suitable to complex with lanthanides such as Y, Yb and Lu include the one illustrated in General Formula II below,

wherein Ri is as described above with respect to General Formula I as selected from a Ci-C ₆ alkyl, a dialkylamino group and an organic amido group where R is a Ci-C ₆ alkyl, and R ₂ and R are as described above with respect to General Formula I as selected from Ci-C ₆ alkyl. In one embodiment, R ₂ is a methyl group and R is an ethyl group. A resulting ligand may be referred to as an amidinate ligand complex and where R is a dialkylamino, a resulting ligand may be referred to as a guanidinate. Ligands of General Formula II provide a low molecular weight environment for lanthanide metals allowing such ligands to be used as stabilizing scaffolds for lanthanides in ALD applications. When complex with a lanthanide (Y, Yb, Lu) to form the composition of General Formula I, the composition is suitable as a volatile, thermally stable precursor compatible with generally milder co-reactants such as water and hydrogen sulfide.

In one embodiment, a low molecular weight amidinate ligand (an amidine) where Ri is a methyl group, R ₂ is a methyl group and R is an ethyl group may be synthesized by a process illustrated in the synthesis scheme of Figure 1. Representatively, with reference to Figure 1, N-methylacetamide is used as a starting material. N-methylacetamide also may be referred to as N-methyl ethanamide. Other starting materials that may be used include N- methyl propanamide and N-methyl butanamide, by way of example and not limitation. In the synthesis, N-methylacetamide may be subjected to O-alkylation with methyl triflate to yield the corresponding activated imine, as illustrated. O-alkylation or O-alkylating may be referred to as methylation. Methyl triflate also may be referred to as methyl

trifluoromethanesulfonate and has the formula CF ₃ S0 ₂ OCH ₃ . Methyl triflate is a powerful methylating reagent. Other methylating reagents may be used, such as methyl

fluorosulfonate, which has the formula FS0 ₂ OCH ₃ . The O-alkylation may be carried out at a temperature of approximately 0 to 30°C for approximately 10 minutes to 48 hours in ether, tetrahydrofuran, methylene chloride, or toluene, for example. Other solvents may include dichloroethane, bromobenzene, or fluorobenzene, by way of example and not limitation.

An activated imine, as illustrated, may be used in-situ as a convenient intermediate to introduce a variety of N-alkyl amines, effectively allowing the construction of unsymmetrical amidines with different Nl -alkyl groups. In Synthesis Scheme I, ethyl amine is substituted for the methoxy group to provide an Nl -ethyl group, as illustrated. Other N-alkyl amines may include methyl amine, propyl amine, and butyl amine, by way of example and not limitation. The N-alkyl amine reaction may be carried out at a temperature of approximately 0 to 30°C for approximately 10 minutes to 48 hours in ether, tetrahydrofuran, methylene chloride, or toluene, for example. Other solvents may include dichloroethane, bromobenzene, or fluorobenzene, by way of example and not limitation.

Deprotonation with common bases may allow the isolation of the free amidine, as illustrated in the synthesis scheme of Figure 1. Common bases may include sodium hydroxide, potassium hydroxide, and ammonium hydroxide, by way of example and not limitation. The deprotonation may be carried out at a temperature of approximately 0 to 30°C for approximately 10 minutes to 48 hours in ether, tetrahydrofuran, methylene chloride, or toluene, for example. Other solvents may include dichloroethane, bromobenzene, or fluorobenzene, by way of example and not limitation.

Figure 2 illustrates a synthesis scheme using the amidine ligand of the synthesis scheme of Figure 1 to form a complex with one or more lanthanides to provide an amidinate having the formula of General Formula I where Ri is a methyl group, R ₂ is methyl group and R is an ethyl group. Representatively, the amidine is initially depronated at -78°C in TFIF and then warmed to room temperature and stirred for 1 hour. The reaction releases C4H10 as by-product, shown in Figure 2. The lithiated amidine is then added under inert atmosphere (nitrogen or argon) to a suspension of a lanthanide salt, for example, LnCl that has been pre- cooled to -78°C. The reaction releases LiCl as a by-product, as shown in Figure 2. The mixture is stirred at -78°C for 10 min and allow to warm for 12 hours. The reaction is then filtered from the LiCl byproduct and the solvent is removed under vacuum and the residue sublimed at 180°C to yield a pure solid (yield: 50-70%).

The method of forming a lanthanide oxide or sulfide composition using a precursor having a formula of General Formula I can be performed by atomic layer deposition (ALD) process. Figure 3 shows a schematic of a representative deposition system. System 100 includes chamber 102 having an interior volume suitable to accommodate a substrate, such as a semiconductor wafer. Chamber 102 includes stage 115 on which a substrate can be supported. Figure 3 shows substrate 120 such as a wafer on stage 115 in a device side up configuration.

Connected to an interior volume of chamber 102 are a number of process gas sources, including gas source 104 of, for example, a lanthanide oxide or sulfide precursor having the formula of General Formula I; gas source 106 of, for example, a first co-reactant of water (for a lanthanide oxide) or hydrogen sulfide (for a lanthanide sulfide); and gas source 108 of, for example, a second co-reactant, a purge gas or other gas source. Also connected to chamber 102 is plasma activator 110 and/or plasma activator 112. Remote plasma activator 110 is separate from and communicates with chamber 102 while plasma activator 112 may be operated directly in chamber 102 (e.g., a capacitively coupled plasma electrode). In one example, a plasma activator such as remote plasma generator 110 and/or plasma generator 112 includes a plasma or ionization source for activating gas source 114, such as a hydrogen or other gas source(s) for introduction of an activated species into chamber 102 (plasma source to include ions, electrons, protons and radicals of the activated gas). The plasma source may be described in terms of energy density related to factors such as an energy applied to the gas source at the plasma activator (e.g., to establish a concentration of activated species in the plasma source) and the distance of plasma activator from a substrate surface in chamber 102. Energy density is one variable associated with a plasma source. Typical plasma densities can be in a range from 0.1 W/cm ² to 1.0 W/cm ² . Other variables include the duration or exposure time of the substrate (or reactants) to the plasma source and when a plasma source is introduced. For an ALD process, in one embodiment, the plasma source may be introduced during more than one of the pulses of an ALD process (e.g., during the purge pulse, co-reactant pulse or both) in a plasma-enhanced ALD (PEALD) process.

Similarly, a plasma source may be introduced with the precursor and co-reactant(s) in a CVD process in plasma-enhanced CVD (PECVD) process.

System 100 also includes an example of a heat source (shown as heat source 116) that may be used to heat an interior of chamber 102 to a desired temperature for a reaction between a substrate and the precursor or the precursor and co-reactant(s). Figure 3 shows temperature source 116 disposed within chamber 102 (in this case, within a stage within the chamber). It is to be appreciated that a suitable reactor may include hotwall or coldwall chambers. Figure 3 also shows evacuation source 118 connected to an interior chamber 102 to evacuate excess or non-reactive constituents or process gases (e.g., precursor, co-reactant) from the chamber. Evacuation source 118 may be connected to a vacuum pump or other source (not shown).

Figure 4 illustrates a schematic representation of a method of depositing a lanthanide oxide or sulfide film or layer on a substrate by an ALD process. In one embodiment, the method begins by placing a substrate in a chamber of an ALD system such as system 100 of Figure 3 (block 210, Figure 4). The substrate may be a silicon wafer at a point, for example,in a process to form a plurality of transistors thereon such as at a point of forming a gate dielectric on a defined channel region of such devices. The substrate may be heated within the reactor to a temperature between around 80°C and around 450°C. A

representative pressure within the reactor may range from 0.1 Torr to 10 Torn In one embodiment, lanthanide composition having a formula of General Formual I is introduced (e.g., pulsed) into the chamber in a gaseous state and deposited on the substrate (block 215, Figure 4). The pulsing can be between 0.5 and 30 seconds.

The chamber of the ALD system is then purged in preparation for introducing a ca- reactant (block 220, Figure 4). Examples of purge gases include, but are not limited to, nitrogen (N ₂ ), helium (He) and Argon (Ar) or other non-reactive gases. Purging can be between about 0.5 seconds and 40 seconds. A co-reactant is then introduced into the chamber (block 225, Figure 4). In one embodiment, the co-reactant is water for a lanthanide oxide film or hydrogen sulfide for a lanthanide sulfide film. A representative deposition pulse for a co-reactant includes, but is not limited to, a pulse duration of between around 0.5 seconds and 20 seconds, a flow rate of up to 10 SLM, a reactor pressure between around 1 Torr and 760 Torr, a temperature between around 80°C and 450°C. It should be noted that the scope of embodiments includes any possible set of process parameters that may be used to carry out the embodiments described herein.

The chamber of the system is then purged again (block 230, Figure 4). The chamber may be purged for about 0.5 seconds to 10 seconds. The sequence of precursor

pulse/purge/co-reactant pulse/purge is repeated until a target lanthanide oxide or lanthanide sulfide film having a targeted or desired film thickness is achieved on the substrate (block 245, Figure 4)

Figure 5 shows a cross-sectional schematic side view of an example semiconductor structure configured with a lanthanide oxide dielectric. This example case includes a metal oxide semiconductor (MOS) transistor formed on a substrate. As will be appreciated, the transistor may be a planar configuration, or a non-planar configuration where the depicted side-view cross-section is taken parallel along a body or fin surrounded by dielectric material on the substrate. As will be further appreciated, any number of

semiconductor devices may employ a lanthanide oxide dielectric or insulator material as described herein, and the disclosure is not intended to be limited to any particular type of integrated circuit.

Any number of suitable substrates can be used to implement substrate 300 on which the transistor is formed, including bulk substrates, semiconductors-on-insulator substrates (XOI, where X is a semiconoductor material such as silicon, germanium, or

germanium-enriched silicon), and multi-layered structures, including those substrates upon which fins or nanowires can be formed prior to a subsequent gate patterning process. In some specific example cases, substrate 300 is a germanium or silicon or SiGe bulk substrate, or a germanium or silicon or SiGe on oxide substrate.

As can be seen, a gate stack is formed over a channel region of the device, and includes gate dielectric layer 302, gate electrode 304, and optional hardmask 306. Spacers 310 are formed adjacent to the gate stack. Gate dielectric 302 is, for example, a lanthanide oxide (e.g., Y ₂ 0 , Yb ₂ 0 or Lu ₂ 0 ) formed by an ALD process including a lanthanide composition or precursor having the formula of General Formula I. In another embodiment, gate dielectric 302 is lanthanide oxide in combination with another dielectric material or materials such as a group 13 oxide (e.g., aluminum oxide, gallium oxide, indium oxide) or silicon dioxide. The lanthanide oxide and the other dielectric material(s) may be deposited sequentially by ALD repeating a deposition of one after another until a desired film thickness is reached. In general, the thickness of gate dielectric 302 should be sufficient to electrically isolate gate electrode 304 from the source and drain contacts. In some specific example embodiments, high-k gate dielectric layer 302 may have a thickness in the range of 5 A to around 100 A thick (e.g., 10 A). In some embodiments, additional processing may be performed on high-k gate dielectric layer 302, such as an annealing process to improve the quality of the high-k material.

Gate electrode 304 is disposed on gate dielectric layer 302 in Figure 5. Gate electrode 304 can be, for example, poly silicon, silicon nitride, silicon carbide, or a metal layer (e.g., tungsten, titanium nitride, tantalum, tantalum nitride) although other suitable gate electrode materials can be used as well. A material of gate electrode 304, which may be a sacrificial material that is later removed for a replacement metal gate (RMG) process, has a representative thickness in the range of about 10 A to 500 A (e.g., 100 A), in some example embodiments. Optional gate hard mask layer 306 can be used to provide certain benefits or uses during processing, such as protecting gate electrode 304 from subsequent etch and/or ion implantation processes. Hard mask layer 306 may be formed using typical hard mask materials, such as such as silicon dioxide, silicon nitride, and/or other conventional insulator materials. The gate stack can be formed as conventionally done or using any suitable custom techniques (e.g., conventional patterning process to etch away portions of the gate electrode and the gate dielectric layers to form the gate stack).

With further reference to Figure 5, the example device also includes source/drain regions 312, which may be p-type or n-type. As will be appreciated, the composition, doping, and geometry of source/drain regions 312 will vary depending on factors such as the composition of substrate 300, polarity of the device, the use of grading for lattice matching/compatibility, and the overall desired thickness of the total source/drain deposition. Numerous material system and doping configurations can be implemented, as will be appreciated. In some example embodiments, source/drain regions 312 are implemented with doped silicon or silicon germanium. Liners and/or buffer layers may be provided as well, as sometimes done. In the example embodiment shown, source/drain regions 312 are implemented with a raised configuration and include source/drain extensions 312A or so- called tip regions in relatively close proximity to the channel region so as to impart a larger hydrostatic stress on the channel. Other embodiments may include tip regions implemented with a diffusion-based process where the tip regions generally do not induce a strain on the channel region.

As will be appreciated, any number of other transistor configurations may be implemented. For instance, the channel may be strained or unstrained, and the source/drain regions may or may not include tip regions formed in the area between the corresponding source/drain region and the channel region. In this sense, whether a transistor structure has strained or unstrained channels, or source/drain tip regions or no source/ drain tip regions, is not particularly relevant to various embodiments of the present invention, and the claimed invention is not intended to be limited to any particular such structural features. Rather, any number of transistor structures and types can benefit from employing a low-k dielectric as described herein.

As can be further seen, the device includes insulator layer 314 that has been deposited and then planarized down to hard mask 306. Insulator layer 314 may be formed, for example, using low-k dielectric (insulator) materials. In such applications, insulator layer 314 may be referred to as an interlayer dielectric (ILD), and provides electrical insulation between the source/drain and gate electrodes, as well as between neighboring devices. An ILD may also be used to provide structural support.

The example embodiment of Figure 5 further includes contact resistance reducing metal 316, which in some embodiments include silver, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum or nickel-aluminum, and/or other such resistance reducing metals or alloys. Contact plug metal 318, which in some embodiments includes aluminum or tungsten, although any suitably conductive contact metal or alloy can be used, such as silver, nickel-platinum or nickel-aluminum or other alloys of nickel and aluminum, or titanium, using conventional deposition processes. Metalization of the source/drain contacts can be carried out, for example, using a silicidation process (generally, deposition of contact metal and subsequent annealing). Figure 6 illustrates interposer 400 that includes one or more embodiments. Interposer 400 is an intervening substrate used to bridge a first substrate 402 to second substrate 404. First substrate 402 may be, for instance, an integrated circuit die. Second substrate 404 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 400 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, interposer 400 may connect an integrated circuit die to ball grid array (BGA) 406 that can subsequently be connected to second substrate 404. In some embodiments, first and second substrates 402/404 are attached to opposing sides of interposer 400. In other embodiments, first and second substrates 402/404 are attached to the same side of interposer 400. In further embodiments, three or more substrates are interconnected by way of interposer 400.

Interposer 400 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 408 and vias 410, including but not limited to through-silicon vias (TSVs) 412. Interposer 400 may further include embedded devices 414, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on interposer 400.

In accordance with embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 400.

Figure 7 illustrates computing device 500 in accordance with one embodiment.

Computing device 500 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a

motherboard. The components in computing device 500 include, but are not limited to, integrated circuit die 502 and at least one communication chip 508. In some implementations communication chip 508 is fabricated as part of integrated circuit die 502. Integrated circuit die 502 may include CPU 504 as well as on-die memory 506, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).

Computing device 500 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die.

These other components include, but are not limited to, volatile memory 510 (e.g., DRAM), non-volatile memory 512 (e.g., ROM or flash memory), graphics processing unit 514 (GPU), digital signal processor 516, crypto processor 542 (a specialized processor that executes cryptographic algorithms within hardware), chipset 520, antenna 522, display or a touchscreen display 524, touchscreen controller 526, battery 528 or other power source, a power amplifier (not shown), global positioning system (GPS) device 544, compass 530, motion coprocessor or sensors 532 (that may include an accelerometer, a gyroscope, and a compass), speaker 534, camera 536, user input devices 538 (such as a keyboard, mouse, stylus, and touchpad), and mass storage device 540 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

Communications chip 508 enables wireless communications for the transfer of data to and from computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chip 508 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device 500 may include a plurality of communication chips 508. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second

communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Processor 504 of computing device 500 includes one or more devices, such as transistors or metal interconnects, that are formed in accordance with embodiments presented above to include a high-k lanthanide dielectric. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communication chip 508 may also include one or more devices, such as transistors or metal interconnects, that are formed in accordance with embodiments presented above to include a high-k lanthanide dielectric.

In further embodiments, another component housed within computing device 500 may contain one or more devices, such as transistors or metal interconnects, that are formed in accordance with implementations presented above to include a high-k lanthanide dielectric.

In various embodiments, computing device 500 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 500 may be any other electronic device that processes data.

EXAMPLES

Example 1 is a lanthanide composition including the formula:

wherein Ri is selected from a Ci-C ₆ alkyl, a dialkyl amino group and an organic amido group, R-2 and R are individually selected from a C1-C6 alkyl and Ln is selected from yttrium, ytterbium and lutetium.

In Example 2, Ri in the lanthanide composition of Example 1 is a methyl.

In Example 3, Ln in the lanthanide composition of Example 1 or 2 is yttrium.

In Example 4, Ln in the lanthanide composition of Example 1 or 2 is ytterbium.

In Example 5, Ln in the lanthanide composition of Example 1 or 2 is lutetium.

In Example 6, R ₂ in the lanthanide composition of any of Examples 1-5 is a methyl and R ₃ is an ethyl.

Example 7 is a method of forming a lanthanide composition including condensing a lanthanide salt with a ligand including the formula:

wherein Ri is selected from a Ci-C ₆ alkyl, a dialkyl amino group and an organic amido group, R ₂ and R ₃ are individually selected from a Ci-C ₆ alkyl.

In Example 8, the lanthanide salt in the method of Example 7 includes a lanthanide selected from yttrium, ytterbium and lutetium.

In Example 9, the lanthanide salt in the method of Example 8 includes a lanthanide halide.

In Example 10, Ri in the method of Example 7 is a methyl.

In Example 11, R ₂ in the method of Example 10 is a methyl and R ₃ is an ethyl.

Example 12 is a method of forming a dielectric film on a integrated circuit device including placing an integrated circuit device substrate in a deposition chamber; depositing a film including a lanth nide composition including the formula:

wherein Ri is selected from a Ci-C ₆ alkyl, a dialkyl amino group and an organic amido group, R ₂ and R ₃ are individually selected from a Ci-C ₆ alkyl and Ln is selected from yttrium, ytterbium and lutetium.

In Example 13, Ri in the method of Example 12 is a methyl.

In Example 14, the lanthanide composition in the method of Example 12 or 13 includes a precursor in an atomic layer deposition process and the method further includes depositing a co-reactant.

In Example 15, the co-reactant in the method of Example 14 includes water.

In Example 16, the method of Example 15 further includes forming a lanthanide oxide.

In Example 17, the lanthanide oxide in the method of Example 16 is formed as a gate dielectric.

In Example 18, the co-reactant in the method of Example 14 includes hydrogen sulfide.

In Example 19, Ln in the method of any of Examples 12-18 is yttrium.

In Example 20, Ln in the method of any of Examples 12-18 is ytterbium.

In Example 21, Ln in the method of any of Examples 12-18 is lutetium.

In Example 22, R ₂ in the method of Example 13 is a methyl and R is an ethyl.

The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope, as those skilled in the relevant art will recognize.

These modifications may be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.