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Title:
NITRIDE SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/097813
Kind Code:
A1
Abstract:
This nitride semiconductor device (100) is provided with: a substrate (110); a drift layer (120) and a block layer (130) which are provided in said order above the substrate (110); a gate opening section (140) penetrating the block layer (130) and reaching the drift layer (120); an electron transit layer (150) and an electron supply layer (150) which are provided in said order above the block layer (130) and along the inner surface of the gate opening section (140); a gate electrode (170) provided to cover the gate opening section (140); a source opening section (160) penetrating the electron supply layer (151) and the electron transit layer (150) and reaching the block layer (130); a source electrode (180S) provided in the source opening section (160); and a drain electrode (180D) provided on the back surface side of the substrate (110), wherein in a plan view, at least a portion of a contour (143a) of an end portion (143) in the longitudinal direction of the gate opening section (140) follows a circular arc or an elliptical arc.

Inventors:
SHIBATA, Daisuke
TAMURA, Satoshi
HIRASHITA, Nanako
Application Number:
JP2018/032357
Publication Date:
May 23, 2019
Filing Date:
August 31, 2018
Export Citation:
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Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
International Classes:
H01L21/337; H01L21/338; H01L29/12; H01L29/778; H01L29/78; H01L29/808; H01L29/812
Domestic Patent References:
WO2017138505A12017-08-17
Foreign References:
JP2011138916A2011-07-14
JP2013062442A2013-04-04
Attorney, Agent or Firm:
NII, Hiromori et al. (6F Tanaka Ito Pia Shin-Osaka Bldg., 3-10, Nishi Nakajima 5-chome, Yodogawa-ku, Osaka-cit, Osaka 11, 〒5320011, JP)
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