Title:
NOISE CONTROL IN PROCESSOR-IN-MEMORY ARCHITECTURES
Document Type and Number:
WIPO Patent Application WO/2022/027371
Kind Code:
A1
Abstract:
Runtime hardware configuration based on multiple electronic noise models is provided to control electronic noise emitted by a processor-in-memory architecture which may be harvested as entropy for a random number generator. Outside of PIM runtime, one or more noise models calibrates parameters of the noise model based on runtime feedback from the PIM; a configuration solver determines a runtime hardware configuration for the PIM to satisfy per-layer randomness requirement (s) of a learning model; the configuration solver transmits the runtime hardware configuration to a noise control module; the noise control module receives real-time runtime feedback regarding the PIM; the noise control module determines, based on the real-time runtime feedback, configuration instructions of the PIM for runtime conditions to approach configuration parameters of the runtime hardware configuration; and the noise control module performs runtime hardware configuration by outputting determined configuration instructions to one or more hardware modules of the PIM.
Inventors:
NIU DIMIN (US)
GUAN TIANCHAN (CN)
ZHENG HONGZHONG (US)
GUAN TIANCHAN (CN)
ZHENG HONGZHONG (US)
Application Number:
PCT/CN2020/107219
Publication Date:
February 10, 2022
Filing Date:
August 05, 2020
Export Citation:
Assignee:
ALIBABA GROUP HOLDING LTD (CN)
International Classes:
G11C11/4096; G06F7/58
Foreign References:
| US20180039484A1 | 2018-02-08 | |||
| CN110633667A | 2019-12-31 | |||
| US20170337690A1 | 2017-11-23 | |||
| US20200219553A1 | 2020-07-09 |
Attorney, Agent or Firm:
BEIJING TSINGYUANHUI INTELLECTUAL PROPERTY LAW FIRM (CN)
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