NOISE EQUALIZING CIRCUIT

WIPO Patent Application WO/2013/031874

A1

Provided is a noise equalizing circuit that is required for terminating an EMC analysis in a practical time by use of a low-cost calculation process at an upstream stage of a system design. This invention is characterized in that the invention is a noise equalizing circuit comprising: one or more energy sources; conduction paths constituted by cables or the like and serving as propagation paths along which the energies from the energy sources propagate; electromagnetic-field-coupled paths established by the couplings of the electric and magnetic fields occurring between the local electronic device or cables and other electronic devices, cables or the like; and GND ports connected to the system, each of the ports being expressed by a noise voltage source or noise current source and an internal impedance. This noise equalizing circuit can be used to determine an external impedance that varies with the distance from an externally connected load or an external device and cable or the like, whereby the noise of the whole system can be analyzed (see FIG. 1).

JP4891145	Robot, radio wave detection device, radio wave detection method and radio wave detection processing program
JP2000214191	SIMULATION DEVICE AND METHOD AND PROGRAM RECORDING MEDIUM

TORIGOE MAKOTO (JP)
FUNATO HIROKI (JP)
SUGA TAKASHI (JP)
OSAKA HIDEKI (JP)
TSUCHIE YOSHIYUKI (JP)
FUKUMASU KEISUKE (JP)
YOKOTA HITOSHI (JP)

PCT/JP2012/071953

March 07, 2013

August 30, 2012

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HITACHI LTD (JP)
TORIGOE MAKOTO (JP)
FUNATO HIROKI (JP)
SUGA TAKASHI (JP)
OSAKA HIDEKI (JP)
TSUCHIE YOSHIYUKI (JP)
FUKUMASU KEISUKE (JP)
YOKOTA HITOSHI (JP)

G01R29/08; G06F17/50; G01R29/26

JPH07302278A	1995-11-14
JP2009098891A	2009-05-07
JP2005165871A	2005-06-23

HIRAKI Yusuke et al. (JP)
Yusuke Hiraki (JP)

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