Title:
NOISE FILTER CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2003/056711
Kind Code:
A1
Abstract:
A noise filter circuit that is integrally molded on a semiconductor substrate and improves the precision of filtering out noise components. The noise filter circuit comprises a high−pass filter for detecting noise components included in an input signal, a pulse generation circuit for generating a pulse signal matching with a detected noise component, an analog delay circuit (252) for delaying the input signal, and an output circuit for filtering out the noise component included in this delayed signal according to the output timing of the pulse signal. The analog delay circuit (252) makes switches (51−56) on by turns to retain the voltage of an input signal at their respective points in each of the capacitors (81−86), and switches (61−66) on to fetch this retained voltage before updating it, thereby delaying the output timing of the input signal.
Inventors:
MIYAGI HIROSHI (JP)
Application Number:
PCT/JP2002/012898
Publication Date:
July 10, 2003
Filing Date:
December 10, 2002
Export Citation:
Assignee:
TOYOTA JIDOSHOKKI KK (JP)
NIIGATA SEIMITSU CO LTD (JP)
MIYAGI HIROSHI (JP)
NIIGATA SEIMITSU CO LTD (JP)
MIYAGI HIROSHI (JP)
International Classes:
H04B1/10; H03H19/00; H03K5/1252; H03H11/26; (IPC1-7): H04B1/10; H03H19/00; H03H11/26
Foreign References:
| JPH09186617A | 1997-07-15 | |||
| JPH0248830A | 1990-02-19 | |||
| JPH11260093A | 1999-09-24 | |||
| JPS62123819A | 1987-06-05 | |||
| JPH01136404A | 1989-05-29 | |||
| JPH09284096A | 1997-10-31 |
Attorney, Agent or Firm:
Osuga, Yoshiyuki (Nibancho Bldg. 8-20, Nibanch, Chiyoda-ku Tokyo, JP)
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