Ramon Mangaser Karthik Gopalakrishnan Andy Huei Chu Pradeep Jayaraman

[0001] This application claims priority to provisional application U.S. 63/232,343 filed August 12, 2021, the entire contents of which are incorporated herein by reference.

BACKGROUND

[0002] Modem single-ended data transmission systems offer benefits of density that are critical at a system level compared to differential signaling. Systems will continue to push single ended schemes to retain this benefit as we migrate to higher speeds and modulations. The challenges for link performance (e.g., meeting bit error targets, power, area) also greatly increase with the need for higher speed.

[0003] Many of these systems are burst mode in nature. In other words, they remain in a low power state (referred as an idle state) while not in use and transition to an active state (i.e., normal transmission or reception of data) when needed. As the physical interface circuit (PHY) enters into an active mode from an idle state, the power delivery networks (PDNs) deal with this burden of sudden changes in loading. A sudden demand for power looks like a step excitation to the PDNs, and causes typical networks to resonate at their natural frequencies. This resonant noise becomes a big source of error that links have to deal with.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 illustrates in block diagram form a data transmission system known in the prior art;

[0005] FIG. 2 illustrates in partial block diagram and partial schematic form a data transmission system according to some embodiments;

[0006] FIG. 3 illustrates a set of timing diagrams useful for understanding the operation of the data transmission system of FIG. 2;

[0007] FIG. 4 illustrates a graph showing an example of the height and width of the data eye measured at various data noise frequencies when the data transmission system of FIG. 2; and

[0008] FIG. 5 illustrates in partial block diagram and partial schematic form a data transmission system useful in a multiple-level data transmission systems according to some embodiments. [0009] In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0010] A data transmission system includes a first circuit, a second circuit, and a reference voltage generation circuit. The first circuit includes a transmitter powered by a first power supply voltage and having an input for receiving a data output signal, and an output. The second circuit includes a receiver powered by a second power supply voltage and having a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal. The reference voltage generation circuit forms the reference voltage by mixing a first signal generated by the first circuit based on the first power supply voltage and a second signal generated by the second circuit based on the second power supply voltage.

[0011] A data transmission system includes a transmitter, a receiver, and a reference voltage generation circuit. The transmitter is powered by a first power supply voltage and has an input for receiving a data output signal, and an output. The receiver is powered by a second power supply voltage and has a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal. The reference voltage generation circuit includes a driver and a voltage divider. The driver is powered by the first power supply voltage and has an input for receiving a predetermined signal, and an output. The voltage divider is powered by the second power supply voltage and is coupled to the output of the driver and to the second input of the receiver for providing the reference voltage thereto.

[0012] A method includes transmitting a data signal from a transmitter of a first integrated circuit operating with a first power supply voltage, said first integrated circuit having a first voltage reference terminal. The data signal is received in a receiver of a second integrated circuit operating with a second power supply voltage. The second integrated circuit has a second voltage reference terminal. The receiving includes comparing said data signal to a voltage on said second voltage reference terminal to provide a received data signal. A shared reference voltage is generated on said first and second voltage reference terminals based on noise in both said first power supply voltage and said second power supply voltage.

[0013] FIG. 1 illustrates in block diagram form a data transmission system 100 known in the prior art. Data transmission system 100 is a single-ended system and includes an integrated circuit 110, an integrated circuit 120, and a transmission medium 130.

[0014] Integrated circuit 110 includes a driver 111 and a comparator 112. Driver 111 has an input for receiving a signal to be output labelled “DATAOUTA”, an output connected to a terminal of integrated circuit 110, and has a power supply input for receiving a more-positive power supply voltage labelled “VDDA” that in conjunction with a more-negative power supply voltage designated “VSSA” but not shown in FIG. 1, forms the overall power supply voltage for integrated circuit 110. Comparator 112 has a positive input connected to the integrated circuit terminal of integrated circuit 110, a negative input for receiving a reference voltage labelled “VREFA” associated with integrated circuit 110, and an output for providing a signal labelled “DATAINA”.

[0015] Integrated circuit 120 includes a driver 121 and a comparator 122. Driver 121 has an input for receiving a signal to be output labelled “DATAOUTB”, an output connected to a terminal of integrated circuit 120, and has a power supply input for receiving a more-positive power supply voltage labelled “VDDB” that in conjunction with a more-negative power supply voltage designated “VSSB” but not shown in FIG. 1, forms the overall power supply voltage for integrated circuit 120. Comparator 122 has a positive input connected to the integrated circuit terminal of integrated circuit 120, a negative input for receiving a reference voltage labelled “VREFB” associated with integrated circuit 130, and an output for providing a signal labelled “DATAINB”.

[0016] Transmission medium 130 has a left end connected to the terminal of integrated circuit 110, and a right end connected to the terminal of integrated circuit 120. Transmission medium 130 can be, for example, an integrated circuit trace along a bus in a computer motherboard connected a microprocessor with its associated memory.

[0017] Each of drivers 111 and 121 are shown with a resistor indicating they have a drive strength that matches the characteristic impedance of transmission medium 130 and a termination resistance, not shown in FIG. 1, at the inputs to comparators 112 and 122. Moreover, the link is bidirectional, such that sometimes data is transmitted from integrated circuit 110 to integrated circuit 120, and sometimes it is transmitted from integrated circuit 120 to integrated circuit 110. A typical implementation of data transmission system 100 is a graphics double data rate, version 6 (gDDR6) synchronous dynamic random-access memory (SDRAM) and a physical interface of a graphics processor having a gDDR6 memory controller. As technology has advanced, the speed of operation of gDDR memory has increased, such that a typical gDDR6 data transfer speed at low-to-high and high-to-low transitions of a memory clock having a frequency of several GHz. At speeds this high, it is necessary for the memory controller to train the link by providing precise timing delays so that the data can be captured near the center of a “data eye”, i.e., a time period and a voltage range in which the data can be reliably captured at the high clock speeds.

[0018] The reference voltages at each end of transmission medium 130 can be calibrated to provide data eyes that are as large as possible. Each end of the communication link is susceptible to noise which is reflected on VREFA and VREFB. However, the noise sources at the ends of transmission medium 130 are independent of each other because the power distribution networks are likewise independent. These independent noise sources tend to affect the drivers and the receivers differently, causing the data eyes to shrink by shrinking both the eye-height and the eyewidth.

[0019] FIG. 2 illustrates in partial block diagram and partial schematic form a data transmission system 200 according to some embodiments. Data transmission system 200 includes generally an integrated circuit 210, an integrated circuit 230, and a transmission medium 250.

[0020] Integrated circuit 210 includes a transceiver 211, a data strobe receiver 214, a latch 217, a data strobe driver 218, a voltage divider 220, and a buffer 223. Transceiver 211 includes a transmitter 212 and a receiver 213. Transmitter 212 has an input for receiving the DQUTA signal, an output connected to a first terminal of integrated circuit 210, and a power supply input for receiving a more-positive power supply voltage labelled “VPHY-A” that in conjunction with more-negative power supply voltage VSSA forms the overall power supply voltage for integrated circuit 210. Receiver 213 has a positive input connected to the first integrated circuit terminal, a negative input for receiving reference voltage VREFA, an output, and a power supply input for receiving VPHY-A. Data strobe receiver 214 includes a resistor 215 and a comparator 216. Resistor 215 has a first terminal for receiving VPHY-A, and a second terminal connected to a second terminal of integrated circuit 210. Comparator 216 operates as a data strobe receiver and has a positive input connected to the second integrated circuit terminal, a negative input for receiving reference voltage VREFA, an output, and a power supply input for receiving VPHY-A- Latch 217 is a clocked D-type latch having a D input connected to the output of receiver 213, a clock input connected to the output of comparator 216, and a Q input for providing the DINA signal. Transmitter 218 has an input for receiving an alternating pattern of Is and 0s labelled “1010”, and an output connected to the second integrated circuit terminal.

[0021] Voltage divider 220 includes a resistor 221, and a circuit element 222. Resistor 221 has a first terminal for receiving VPHY-A, and a second terminal connected to a third terminal of integrated circuit 210 and forming voltage VREFA- Circuit element 222 has a first terminal connected to the second terminal of resistor 221, and a second terminal connected to ground. In some embodiments, circuit element 222 is implemented by a tunable current source 224 having a first terminal connected to the second terminal of resistor 221, and a second terminal connected to ground. In other embodiments, circuit element 222 is implemented by a tunable resistor 225 having a first terminal connected to the second terminal of resistor 221, and a second terminal connected to ground. In still other embodiments, circuit element 222 is implemented by a combination of a tunable current source and a tunable resistor. Buffer 223 is an optional buffer shown in dashed line and has an input connected to the second terminal of resistor 221, and an output connected to the negative inputs of receivers 213 and 216.

[0022] Integrated circuit 230 includes a transceiver 231, a data strobe receiver 234, a latch 237, a data strobe transmitter 238, and a driver 239. Transceiver 231 includes a transmitter 232 and a receiver 233. Transmitter 232 has an input for receiving the DQUIB signal, an output connected to a first terminal of integrated circuit 230, and has a power supply input for receiving a more-positive power supply voltage labelled “ VPHY-B” that in conjunction with more-negative power supply voltage VSSB forms the overall power supply voltage for integrated circuit. Receiver 233 has a positive input connected to a first terminal of integrated circuit 230, a negative input for receiving reference voltage VREFB, and an output. Data strobe receiver 234 includes a resistor 235 and a comparator 236. Resistor 235 has a first terminal for receiving VPHY-B, and a second terminal forming reference voltage VREFB connected to a second terminal of integrated circuit 230. Receiver 236 has a positive input connected to the second terminal of integrated circuit 230, a negative input for receiving reference voltage VREFB, and an output. Latch 237 is a clocked D-type latch having a D input connected to the output of receiver 233, a clock input connected to the output of comparator 236, and a Q output for providing the DINB signal. Transmitter 238 has an input for receiving an alternating pattern of Is and 0s labelled “1010”, and an output connected to the second terminal of integrated circuit 230. Driver 239 has an input for receiving a logic high voltage labelled “1”, an output connected to a third terminal of integrated circuit 230 and the negative inputs of receivers 233 and 236 and forming voltage VREFB, and a power supply input for receiving VPHY-B-

[0023] Transmission medium 250 interconnects integrated circuit 210 and integrated circuit 230 and includes a set of conductors 251-253. Conductor 251 has a first end connected to the first terminal of integrated circuit 210, and a second end connected to the first terminal of integrated circuit 230. Conductor 252 has a first end connected to the second terminal of integrated circuit 210, and a second end connected to the second terminal of integrated circuit 230. Conductor 253 has a first end connected to the third terminal of integrated circuit 210, and a second end connected to the third terminal of integrated circuit 230.

[0024] As will be described more fully below, driver 239 and voltage divider 220 are connected together by conductor 253 to form a reference voltage generation circuit 260.

[0025] Data transmission system 200 bidirectionally interconnects integrated circuit 210 and integrated circuit 230 over transmission medium 250. In the example shown in FIG. 2, integrated circuit 230 is a data processor with an integrated DDRx memory controller and a physical layer interface circuit, and integrated circuit 210 is a DDRx memory. The design of data transmission system 200 will vary based on the type of DDRx memory used. For DDR1, as shown in FIG. 1, integrated circuit 230 uses the data (DQ) signals to send and receive data from integrated circuit 210 based on transitions of a single-ended data strobe signal (DQS). Other generations of DDRx memory will contain modifications of data transmission system 200. In another example, integrated circuit 230 is a graphics processing unit (GPU) with an integrated gDDR memory controller and a physical layer interface circuit, and integrated circuit 210 is a gDDR memory such as a gDDR6 SDRAM or a subsequent gDDR version. According to the gDDR6 standard, the data (DQ) terminals are bidirectional terminals, but the clock signal is a unidirectional, differential signal in which the processor provides differential write clock signals (WCK t and WCK c) during both read and write cycles. In yet another example, integrated circuit 230 is a central processing unit (CPU) with an integrated DDR memory controller and a physical layer interface circuit, and integrated circuit 210 is a DDR5 SDRAM. According to the DDR5 standard, the data (DQ) terminals are bidirectional terminals that are captured based on a bidirectional, differential data strobe signal. At the high speeds that gDDR6 and DDR5 memory devices are capable of operating, the data processor (GPU or CPU) performs “data eye training” in which it delays the DQ signal relative to the corresponding clock signal signal so that the clock signal arrives at the data processor aligned to the center of the data eye of the DQS signal. As noted above, however, integrated circuit 210 and integrated circuit 230 receive power from independent PDNs such the noise on the VPHY-A power supply in the first power domain that is independent of noise on the VPHY-B power supply in the second power domain. These variations operate to close the data eye, i.e., they make the height and/or width of the data eye smaller.

[0026] According to various embodiments disclosed herein, however, data transmission system 200 includes a reference voltage generation circuit 260 that forms a reference voltage used in a receiver (e.g., VREFA used in receivers 213 and 216) by mixing a first signal generated by the first circuit (e.g., VREFA generated by voltage divider 220) based on the first power supply voltage (e.g., VPHY-A) and a second signal generated by the second circuit (e.g., VREFB generated by driver 239) based on the second power supply voltage (e.g., VPHY-B). Reference voltage generation circuit 260 creates a reference voltage VREFA that carries the noise properties of both V _PH Y-A and VPHY-B- VREFA is then used in receivers 213 and 216 to receive the DQ and DQS signals, respectively, in integrated circuit 210. Mixing the power supply noise from the opposite end of the communication link to form a reference voltage used in receiving data at the given side of the communication link has the remarkable property of enlarging the DQ data eye to make data reception more robust. In other embodiments, VREF can be formed by mixing Vss noise on the PDNs of integrated circuits 210 and 230. In this case, driver 239 would receive a logic “0” at its input representative of the VSSB voltage, and voltage divider 220 could form VREFA and VREFB by reversing the order of resistor 221 and circuit element 222. In addition, driver 239 would have a pulldown drive strength that matches the resistance of resistor 221.

[0027] In addition, as will be described further below, the significantly more robust data reception enables higher overall data transmission rates by allowing the implementation of a multi-level data transmission and reception system instead of a conventional two-level system. For example, instead of conventional binary data transmission used in existing versions of the DDR and the graphics DDR standards, a four-level pulse amplitude modulation (PAM4) system can be created that allows the transmission and reception of two binary bits for each clock transition instead of just two. Thus, the data transmission bandwidth can be doubled for a given clock speed.

[0028] FIG. 3 illustrates a set of timing diagrams 300 useful for understanding the operation of data transmission system 200 of FIG. 2. Timing diagrams 300 include data eye diagrams 310, 320, 330, and 340. Each data eye diagram has a respective horizontal axis representing time in picoseconds (ps), and a respective vertical axis representing amplitude in volts. Data eye diagrams 310, 320, 330, and 340 show waveform clouds resulting from the superposition of both low-to-high transitions and high-to-low transitions and a group of data signals, e.g., a byte, for which a memory controller sets a capture delay. The left column of diagrams, i.e., data eye diagrams 311 and 331, show data signals received at integrated circuit 210, in which data eye diagram 311 shows the conventional method of generating VREF, and data eye diagram 331 shows the mixing technique of generating VREF according to the various embodiments described herein. Similarly, the right column of diagrams, i.e., data eye diagrams 321 and 341, show data signals received at integrated circuit 230, in which data eye diagram 321 shows the conventional method of generating VREF, and data eye diagram 341 shows the mixing technique of generating VREF according to the various embodiments described herein. As can be clearly seen, the data eye diagrams formed using the mixing techniques described herein exhibit sharper data eyes with greater eye-height and greater eye width.

[0029] These experimental observations shown in the graphs of FIG. 3 confirm the significant improvement in data transmission fidelity using the mixing technique disclosed herein compared to existing data transmission systems.

[0030] FIG. 4 illustrates a graph 400 showing an example of the height and width of the data eye measured at various data noise frequencies when data transmission system 200 of FIG. 2. In FIG. 4, the horizontal axis represents frequency in Hz, the left vertical axis represents eye height in millivolts (mV), and the right vertical axis represents eye width in ps. Shown in graph 400 are four waveforms of interest, including a waveform 410 showing the eye-height of a data eye using the VREF mixing techniques disclosed herein; a waveform 420 showing the eye- height of a data eye using conventional VREF generating techniques; a waveform 430 showing the eye-width of a data eye using the VREF mixing techniques disclosed herein; a waveform 440 showing the eye-height of a data eye using conventional VREF generating techniques. As can be seen from waveforms 410 and 420, the eye-height improves by as much as about 37 mV for a power supply of 0.8 volts through voltage noise frequencies up to about 500 MHz, before declining gradually until reaching a cross-over point at about 950 MHz. The eye widths show a consistent but less dramatic improvement across all voltage noise frequencies. At a voltage noise frequency of particularly interest, namely 100 MHz, the eye-height improves by 24 mV and the eye width by 0.8 ps.

[0031] FIG. 5 illustrates in partial block diagram and partial schematic form a data transmission system 500 useful in a multiple-level data transmission systems according to some embodiments. Data transmission system 500 is includes an integrated circuit 510, an integrated circuit 530, and a transmission medium 550.

[0032] Integrated circuit 510 includes a four-level pulse amplitude modulation (PAM4) receiver 511, a slicing level generator 512, and a voltage divider 520. PAM4 receiver 511 has a signal input connected to a bonding pad of integrated circuit 510, a reference input, an output for providing a decoded voltage signal labelled “DI _NA [1 :0]”, and a power supply input for receiving VPHY-A- Slicing level generator 512 has an input for receiving VREFA, a power supply input for receiving VPHY-A, and an output connected to the second input of PAM4 receiver 511 for providing three slicing levels thereto. Voltage divider 520 includes a resistor 521, and a circuit element 522. Resistor 521 has a first terminal for receiving VPHY-A, and a second terminal forming VREFA and connected to a second terminal of integrated circuit 510. Circuit element 522 has a first terminal connected to the second terminal of resistor 521, and a second terminal connected to ground. As in voltage divider 220, in some embodiments, circuit element 522 is implemented by a tunable current source having a first terminal connected to the second terminal of resistor 521, and a second terminal connected to ground. In other embodiments, circuit element 522 is implemented by a tunable resistor having a first terminal connected to the second terminal of resistor 521, and a second terminal connected to ground. In still other embodiments, circuit element 522 is implemented by a combination of a tunable current source and a tunable resistor.

[0033] Integrated circuit 530 includes a PAM4 transmitter 531 and a driver 535. PAM4 transmitter 531 has an input for receiving a two-bit output signal labelled “DOUTB [1 :0], a power supply input for receiving VPHY-B, a reference input for receiving VREFB, and an output connected to a first terminal of integrated circuit 530. Driver 535 has in input for receiving a logic high voltage level labelled “1”, an output connected to a first terminal of integrated circuit 230, and has a power supply input for receiving VPHY-B.

[0034] Transmission medium 550 includes a conductor 551 and a conductor 552. Conductor 551 has a first end connected to the first terminal of integrated circuit 530, and a second end connected to the first terminal of integrated circuit 510. Conductor 552 has a first end connected to the second terminal of integrated circuit 530, and a second end connected to the second terminal of integrated circuit 510. Driver 535 and voltage divider 520 are connected together by conductor 552 to form a reference voltage generation circuit 560. 10035] Data transmission system 500 operates in much the same way as data transmission system 200 of FIG. 2, but implements PAM4 encoding and decoding. PAM4 allows the effective doubling of data transmission throughput for a given clock frequency by encoding two bits of data as one of four voltage levels transmitted at each clock edge. According to PAM4, the voltage levels are encoded into the four levels as shown in TABLE I below:

TABLE I

[0036] To decode the voltage into the appropriate symbol and its corresponding data, slicing level generator 512 generates three slicing levels at values equal to % VPHY-A. !/2VPHY-A, and ³ /4VPHY-A. Slicing level generator 512 can generate the three slicing levels while injecting power supply noise mixed from integrated circuit 510 and integrated circuit530 based on VREFA in a variety of ways. In one example, integrated circuit 510 and integrated circuit 530 generate VREFA and VREFB at one-half the voltage of V _PH Y-A and V _PH Y-B, respectively. In this case, slicing level generator 512 incorporates a string of four equal-valued resistors between the VPHY-A power supply and ground, in which it generates the value of ³ /4VPHY-A at the connection point between the top and top-middle resistors, and ! VPHY-A at the connection point between the bottom-middle resistor and the bottom resistors. In this example, a buffer has an input for receiving VREFA and an output for driving the connection point between the top-middle and bottom-middle resistors. Because VREFA mixes noise from the PDNs of both integrated circuit 510 and integrated circuit 530, slicing level generator 512 outputs slicing levels with both of these noise components. By the use of the reference voltage with power supply noise mixed from both ends of the communication link, the data eyes will also exhibit improved eye-openings as those described above for binary signal transmission.

[0037] In some embodiments, the resistors in the resistor string could be made programmable, and could be trained to set the slicing levels at the crossover point of the levels in the data eye. For example, sometimes data eyes exhibit an asymmetry that skews the data eye center higher or lower. A calibration process could be used to make these adjustments for an even more robust data transmission and reception.

[0038] Thus, the technique disclosed herein can be used to improve data transmission bandwidth by transmitting non-binary symbols, i.e., symbols having more than two states per clock edge. It is believed that the noise- mitigation techniques may allow PAM4 reception in systems that would not otherwise be robust enough to decode the four voltage levels use in PAM4 symbols at existing clock speeds.

[0039] An integrated circuit or integrated circuits containing the reference voltage generation circuits described herein, or any portions thereof, may be described or represented by a computer accessible data structure in the form of a database or other data structure which can be read by a program and used, directly or indirectly, to fabricate integrated circuits. For example, this data structure may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool which may synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware including integrated circuits. The netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor fabrication steps to produce the integrated circuits. Alternatively, the database on the computer accessible storage medium may be the netlist (with or without the synthesis library) or the data set, as desired, or Graphic Data System (GDS) II data.

[0040] While particular embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, while the present application describes a binary (i.e., 2-level) data transmission and reception system in detail, in some embodiments, the noise mitigation can be used in data transmission systems that transmit more than one bit per clock edge, such as PAM4. Moreover, different pieces of the reference voltage generation circuit can be implemented in different parts of the integrated circuits. The reference voltage generation circuit can also have voltage dividers and/or drivers at both ends of the transmission medium, or at only one end. The disclosed technique is applicable to a wide variety of integrated circuits that use high-speed data transmission. In one particular example, one integrated circuit can be a data processor, system-on- chip (SOC), or graphics processing unit (GPU), while the other integrated circuit is a DDR or gDDR SDRAM, but the techniques described herein can be used with many other types of integrated circuits. The transmission medium can also vary between embodiments, and may include printed circuit board traces, bond wires, through-silicon vias (TSVs), and the like.

[0041] Accordingly, it is intended by the appended claims to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.