ENABLED BY NON-VOLATILE LATCHED OUTPUTS

BACKGROUND

Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, such as silicon (Si), germanium (Ge), and gallium arsenide (GaAs), to name a few. A field-effect transistor (FET) is a semiconductor device that includes three terminals: a gate, a source, and a drain. A FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow between the source and the drain. The source and drain regions of a FET device typically include doped semiconductor material. Generally, p-type doped semiconductor material has a larger hole concentration than electron concentration, where the 'p' refers to the positive charge of the hole, while n-type doped semiconductor material has a larger electron concentration than hole concentration, where the 'n' refers to the negative charge of the electron. Standard dopant used for group IV semiconductor materials, such as Si, Ge, and SiGe, includes boron (B) for p-type (acceptor) dopant and phosphorous (P) or arsenic (As) for n-type (donor) dopant. Some FETs have a fourth terminal called the body or substrate, which can be used to bias the transistor. In addition, metal-oxide-semiconductor FETs (MOSFETs) include a gate dielectric between the gate electrode and the channel region. A MOSFET device may also be known as a metal-insulator-semiconductor FET (MISFET) device or an insulated-gate FET (IGFET) device. In instances where the charge carriers of the MOSFET device are electrons, the device is referred to as an n-channel MOSFET (NMOS) device, and in instances where the charge carriers of the MOSFET device are holes, the device is referred to as a p-channel MOSFET (PMOS) device. Complementary MOS (CMOS) structures use a combination of PMOS and NMOS devices to implement digital logic and other integrated circuit functionality.

In the context of integrated circuits, memory elements, such as for flip-flops or register files, can provide a latched output with at least two stable states. The two stable states may represent a high-output (e.g., T) or a low-output (e.g., 'Ο'). Non-volatile latched outputs retain the state they were set to have even when not receiving power. Thus, a non- volatile latched output can be used for memory applications to store a bit of data (e.g., a T or a 'Ο') regardless of whether power is or is not provided. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a schematic diagram of an example integrated circuit (IC) showing two non-volatile logic circuits that include hybrid circuits employing low-threshold voltage (VT) MOSFET co-integrated with non- volatile elements, in accordance with some embodiments of the present disclosure.

Figure 2 illustrates a schematic diagram of an example hybrid circuit implementation that includes low-VT MOSFET devices co-integrated with a non-volatile element, in accordance with some embodiments of the present disclosure.

Figure 3 illustrates an example cross-sectional IC view of a portion of the example hybrid circuit of Figure 2, in accordance with some embodiments of the present disclosure.

Figures 4A-B illustrate perspective views of an example IC including non-planar transistors configured in a similar manner as the low-VT MOSFET devices of Figures 2 and 3, in accordance with some embodiments of the present disclosure.

Figure 5 illustrates a method of forming an IC including a hybrid circuit that includes low- VT MOSFET devices co-integrated with a non-volatile element, in accordance with some embodiments of the present disclosure.

Figure 6 illustrates a computing system implemented with integrated circuit structures formed using the techniques described herein, in accordance with some embodiments of the present disclosure.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. Further still, some of the features in the drawings may include a patterned and/or shaded fill, which is merely provided to assist in visually differentiating the different features. In short, the figures are provided merely to show example structures. DETAILED DESCRIPTION

In the field of logic integrated circuitry, non- volatile logic has become desirable for some applications, particularly for low-power applications due to non-volatile elements enabling power-down of the circuits thus cutting off the standby leakage. Examples of such non-volatile elements include spintronic devices and spintronic-based logic circuits, such as all- spin logic (ASL), magneto-electric spin-orbit (MESO) logic, and magnetic tunnel junction logic (mLogic). These spintronic devices and spintronic-based logic circuits have relatively low switching energies (CV ² ) due to the associated low voltages involved. However, spintronic logic and other non-volatile logic devices/circuits include non-trivial limitations. For instance, spintronic-only logic suffers from direct leakages due to the current paths between the supply voltage and ground. Accordingly, spintronic devices can have relatively high static power consumption due to direct current (DC) bias currents, such as greater than 1 microampere (μΑ) per device, which is undesirable. Further, the switching speeds of spintronic devices are generally slower relative to the switching speeds of MOSFET devices, where such spintronic switching speeds may be greater than 1 nanosecond (ns), which is also undesirable. However, using standard MOSFET or CMOS devices/circuits alone for low-power applications is also challenging, because such devices/circuits cannot be used with relatively low threshold voltages (VTs) due to leakage currents and lack of non-volatility during power gating. For instance, implementing standard CMOS with relatively low power, such as low VDD (positive supply voltage), and with relatively low VT (to deliver desired performance levels) results in unsustainable leakage current levels. In addition, MOSFET/CMOS logic alone lacks non-volatility, such that power gating cannot be implemented to address those unsustainable leakage current levels. The aforementioned issues and limitations are further exacerbated as IC elements are scaled down to include smaller and smaller critical dimensions, such as transistor devices including, for example, sub- 100 nanometer (nm) or sub-50 nm gate lengths (dimension between corresponding gate spacers).

Thus, and in accordance with various embodiments of the present disclosure, techniques are provided for forming a non- volatile hybrid logic circuit employing low-power MOSFET enabled by non-volatile latched outputs. In some embodiments, the hybrid arrangement is able to achieve both circuit-level non- volatility and relatively lower power levels, neither of which can be attained using MOSFET/CMOS or non-volatile logic/memory elements on their own. For instance, as will be apparent in light of this disclosure, the MOSFET devices described herein are configured to work at improved voltages, switching speeds, and power levels as compared to non-volatile logic devices (such as spintronic devices) that are used alone. Further, standard MOSFET/CMOS alone cannot be used with relatively low VT due to leakage currents and lack of non-volatility during power gating, for example. Accordingly, the non-volatile elements of the hybrid circuit serve as flip-flops or register files to provide non-volatile latched outputs for preserving the state of the logic circuit even when not receiving power. Thus, in some embodiments, low-VDD, low-VT MOSFET devices are operatively coupled with nonvolatile logic/memory elements (e.g., spintronic devices, ferroelectric devices, magnetoresistive devices) to enable energy efficient, low-VDD, low-VT, non-volatile operation for a logic circuit. For instance, using the techniques described herein, a MOSFET device configured for hybrid integration with a non- volatile element (such as a spintronic non-volatile logic device) can reach desired performance levels with relatively low power levels, such as a VDD of less than 200 millivolts (mV) at 3.6 μΑ of drive current, 3.6 nanoamperes (nA) of leakage current, 100 picosecond (ps) nominal delay, and 1 nanosecond (ns) RSSS delay (indicative of the slowest or weakest performance values), to provide an example configuration.

As previously described, the MOSFET elements included in the non- volatile logic circuits described herein are configured to work in conjunction with non-volatile elements in a hybrid circuit, thereby deriving benefits from both elements. However, the relatively low VDD and relatively low VT logic utilizes specific VTs (e.g., sub-200 mV) that are not used in standard scaled logic devices, thereby making such standard scaled logic devices (e.g., standard MOSFET devices) unsuitable for the hybrid circuits described herein. For instance, standard scaled MOSFET devices (e.g., with sub-100 nm gate lengths) typically utilize VTs greater than 300 mV, and even VTs up to 500 mV. Therefore, the MOSFET devices included in the non-volatile hybrid logic circuits described herein include modifications from standard configurations to effectively integrate them with the non- volatile elements. As such, the modified MOSFET devices are referred to herein as low-VT MOSFET devices (e.g., low-VT MOS or low-VT PMOS). As will be apparent in light of this disclosure, the modifications from standard MOSFET configurations provided herein ensure the desired drive current is attained for the relatively lower voltages being utilized. In some embodiments, the modifications include adjusting the work function of a portion of the gate structure, adjusting the net doping concentration in the channel region, and/or intentionally introducing significant levels of dopant of the opposite type from what is standard. These configuration modifications will be described in more detail with respect to n-channel MOSFET (NMOS) and p-channel MOSFET (PMOS) devices, and other suitable configurations will be apparent in light of this disclosure. In some embodiments, the low-VT MOSFET elements included in the hybrid circuit are included in the form of a CMOS circuit that includes both NMOS and PMOS devices. However, the present disclosure is not intended to be so limited, unless otherwise stated. For example, a given hybrid circuit may be implemented with only low-VT NMOS devices or only low-VT PMOS devices, and not both, in some embodiments.

In embodiments where one or more low-VT NMOS devices are included in the hybrid circuit, the low-VT NMOS devices may be modified from standard configurations, as previously described. In more detail, as compared to a standard NMOS device, a given low-VT NMOS as described herein may be formed: with a gate electrode having a relatively lower work function value; with a relatively lower net p-type doping concentration in the channel region; and/or with significant levels of n-type dopant intentionally included in the channel region. Further, in embodiments where one or more low-VT PMOS devices are included in the hybrid circuit, the low-VT PMOS devices may also be modified from standard configurations. In more detail, as compared to a standard PMOS device, a given low-VT PMOS device as described herein may be formed: with a gate electrode having a relatively higher work function value; with a relatively lower net n-type doping concentration in the channel region; and/or with significant levels of p- type dopant intentionally included in the channel region. The aforementioned modifications are atypical for standard NMOS and PMOS devices, as each modification leads to increased subthreshold leakage levels, which is typically undesirable. However, any combination of such modifications, while holding all other configuration details of the given MOS device the same, causes a shift in the IV curve that results in higher drive currents for lower threshold voltages, thereby increasing the device performance. In addition, the non-volatile element included in the hybrid circuit is used to store states from the MOS-based logic, thereby enabling power gating to mitigate increases in subthreshold leakage levels that would otherwise occur. In some embodiments, the VT values of the low-VT NMOS and low-VT PMOS devices described herein may be less than 200, 175, 150, 125, 100, 75, 50, or 25 mV and/or the VT values may be in the range of 0-50, 0-100, 0-150, 0-200, 50-100, 50-150, 50-200, 100-150, 100-200, or 150-200 mV, for example. Other suitable relatively low VT values, ranges, and thresholds will be apparent in light of this disclosure.

In some embodiments where a low-VT NMOS device is formed with a gate electrode having a relatively lower work function value, the relatively lower work function value being referenced is the surface of the gate electrode that is closest to the corresponding gate dielectric. In other words, in some such embodiments, that lower work function value is relevant to the surface of the portion/layer of the gate electrode that is closest to the corresponding channel region. Further, in some such embodiments where the low-VT NMOS device is formed with the gate electrode surface having a relatively lower work function value, that relatively lower work function value may be less than approximately 4.5 eV, as 4.5 eV is the approximate work function value of the relevant surface of a standard MOS gate electrode. Thus, in some such embodiments, the relatively lower work function value of the relevant gate electrode surface of the low-VT NMOS device may be at most 4.4, 4.35, 4.3, 4.25, 4.2, 4.15, 4.1, 4.05, 4, 3.9, 3.8, 3.7, 3.6, or 3.5 electron volts (eV), and/or the relatively lower work function value of the relevant gate electrode surface of the low-VT NMOS device may be in the range of 3.5-3.8, 3.5-4.0, 3.5- 4.2, 3.5-4.4, 3.8-4.0, 3.8-4.2, 3.8-4.3, 3.8-4.4, 4.0-4.1 4.0-4.2, 4.0-4.3, 4.0-4.4, 4.2-4.3, or 4.2-4.4 eV, for example. Other suitable work function values, ranges, and thresholds will be apparent in light of this disclosure. In some embodiments, the relatively lower work function value of the relevant gate electrode surface of the low-VT NMOS device may be achieved using nonstandard metals or metal alloys in the gate electrode, such as Au, Cu, Mg, Al, and/or Ni. However, standard metal/metal alloy gate electrode materials may additionally or alternatively be used, such as Ta, TaN, Ti, TiN, and/or W. As is known to those having ordinary skill in the art, a number of factors can affect the work function value of the relevant gate electrode surface, such as the materials involved, processing temperatures, thicknesses involved, and so forth, such that a number of different metals or metal alloys may be used to achieve the relatively higher work function values described herein.

In some embodiments where a low-VT NMOS device is formed with a relatively lower net p-type doping concentration in the channel region, that relatively lower concentration may be at most a net p-type doping concentration of approximately 1E18 atoms per cubic centimeter (cm), as 1E18 atoms per cubic cm of net p-type doping is the approximate minimum concentration for a standard NMOS channel region. Thus, in some such embodiments, the relatively lower net p- type doping concentration in the NMOS channel region may be at most 5E17, 1E17, 5E16, 1E16, 5E15, or 1E15 atoms per cubic cm, and/or the relatively lower net p-type doping concentration in the NMOS channel region may be in the range of 0-1E16, 0-5E16, 0-1E17, 0- 5E17, 1E15-1E16, 1E15-5E17, or 5E15-5E16 atoms per cubic cm, for example. In some such embodiments, the relatively lower net p-type doping concentration may even cross over to a net n-type doping concentration, if the electron concentration present in the channel region exceeds the hole concentration, for example. Other suitable doping concentration values, ranges, and thresholds will be apparent in light of this disclosure. Note that net doping concentration as described herein with reference to a given transistor channel region includes accounting for p- type and n-type dopants present in that given channel region. For instance, if a transistor channel region includes 2E16 atoms per cubic cm of p-type dopant and 1E16 atoms per cubic cm of n- type dopant, then the net doping concentration would be p-type in the amount of 1E16 atoms per cubic cm, as there would be a larger hole concentration than electron concentration.

In some embodiments where a low-VT NMOS device is formed with significant levels of n-type dopant intentionally included in the channel region, those significant levels of n-type dopant may be at least 1E15 atoms per cubic cm, as 1E15 atoms per cubic cm is a nominal amount of dopant to be included in a semiconductor material feature. Thus, in some such embodiments, the significant levels of n-type dopant intentionally introduced in the low-VT NMOS channel region may be at least 1E15, 5E15, 1E16, 5E16, 1E17, 5E17, or 1E18 atoms per cubic cm, and/or the significant levels of n-type dopant intentionally introduced in the NMOS channel region may be in the range of 1E15-1E17, 1E15-1E20, 1E16-1E18, 1E16-1E20, 1E17- 1E19, or 1E17-1E20 atoms per cubic cm, for example. Other suitable intentional n-type dopant values, ranges, and thresholds will be apparent in light of this disclosure. Note that in some such embodiments, p-type dopant may also be present in the low-VT NMOS channel region, such that the net doping concentration may not be the same as the included concentration of n-type dopant intentionally introduced. In other words, the n-type dopant introduced in the low-VT NMOS channel region may be introduced to lower the net p-type doping concentration, for example. However, in embodiments where the n-type dopant that is intentionally introduced exceeds the concentration of p-type dopant that is present in the channel region, the channel region will have a net n-type doping concentration. Again, such a configuration is atypical for standard NMOS devices, but it can be used to achieve relatively higher drive current for lower voltages.

In some embodiments where a low-VT PMOS device is formed with a gate electrode having a relatively higher work function value, the relatively higher work function value being referenced is the surface of the gate electrode that is closest to the corresponding gate dielectric. In other words, in some such embodiments, that higher work function value is relevant to the surface of the portion/layer of the gate electrode that is closest to the corresponding channel region. Further, in some such embodiments where the low-VT PMOS device is formed with the gate electrode surface having a relatively higher work function value, that relatively higher work function value may be greater than approximately 4.5 electron volts (eV), as 4.5 eV is the approximate work function value of the relevant surface of a standard PMOS gate electrode. Thus, in some such embodiments, the relatively higher work function value of the relevant gate electrode surface of the low-VT PMOS device may be at least 4.6, 4.65, 4.7, 4.75, 4.8, 4.85, 4.9, 4.95, 5, 5.1, 5.2, 5.3, 5.4, or 5.5 electron volts (eV), and/or the relatively higher work function value of the relevant gate electrode surface of the low-VT PMOS device may be in the range of 4.6-4.8, 4.6-5.0, 4.6-5.2, 4.6-5.5, 4.7-4.9, 4.7-5.0, 4.7-5.1, 4.7-5.3, 4.7-5.5, 4.8-5.0, 4.8-5.2, 4.8- 5.5, 5.0-5.2, 5.0-5.5, or 5.2-5.5 eV, for example. Other suitable work function values, ranges, and thresholds will be apparent in light of this disclosure. In some embodiments, the relatively higher work function value of the relevant gate electrode surface of the low-VT PMOS device may be achieved using non-standard metals in the gate electrode, such as gold (Au), copper (Cu), magnesium (Mg), aluminum (Al), and/or nickel (Ni). However, standard gate electrode materials may additionally or alternatively be used, such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), and/or tungsten (W). As is known to those having ordinary skill in the art, a number of factors can affect the work function value of the relevant gate electrode surface, such as the materials involved, processing temperatures, thicknesses involved, and so forth, such that a number of different metals or metal alloys may be used to achieve the relatively higher work function values described herein.

In some embodiments where a low-VT PMOS device is formed with a relatively lower net n-type doping concentration in the channel region, that relatively lower concentration may be at most a net n-type doping concentration of approximately 1E18 atoms per cubic cm, as 1E18 atoms per cubic cm of net n-type doping is the approximate minimum concentration for a standard PMOS channel region. Thus, in some such embodiments, the relatively lower net n- type doping concentration in the low-VT PMOS channel region may be at most 5E17, 1E17, 5E16, 1E16, 5E15, or 1E15 atoms per cubic cm, and/or the relatively lower net n-type doping concentration in the low-VT PMOS channel region may be in the range of 0-1E16, 0-5E16, 0- 1E17, 0-5E17, 1E15-1E16, 1E15-5E17, or 5E15-5E16 atoms per cubic cm, for example. In some such embodiments, the relatively lower net n-type doping concentration may even cross over to a net p-type doping concentration, if the hole concentration present in the channel region exceeds the electron concentration, for example. Other suitable doping concentration values, ranges, and thresholds will be apparent in light of this disclosure. Note that, as previously described, net doping concentration as described herein with reference to a given transistor channel region includes accounting for p-type and n-type dopants present in that given channel region. For instance, if a transistor channel region includes 2E16 atoms per cubic cm of n-type dopant and 1E16 atoms per cubic cm of p-type dopant, then the net doping concentration would be n-type in the amount of 1E16 atoms per cubic cm, as there would be a larger electron concentration than hole concentration.

In some embodiments where a low-VT PMOS device is formed with significant levels of p-type dopant intentionally included in the channel region, those significant levels of p-type dopant may be at least 1E15 atoms per cubic cm, as 1E15 atoms per cubic cm is a nominal amount of dopant to be included in a semiconductor material feature. Thus, in some such embodiments, the significant levels of p-type dopant intentionally introduced in the low-VT PMOS channel region may be at least 1E15, 5E15, 1E16, 5E16, 1E17, 5E17, or 1E18 atoms per cubic cm, and/or the significant levels of p-type dopant intentionally introduced in the low-VT PMOS channel region may be in the range of 1E15-1E17, 1E15-1E20, 1E16-1E18, 1E16-1E20, 1E17-1E19, or 1E17-1E20 atoms per cubic cm, for example. Other suitable intentional p-type dopant values, ranges, and thresholds will be apparent in light of this disclosure. Note that in some such embodiments, n-type dopant may also be present in the low-VT PMOS channel region, such that the net doping concentration may not be the same as the included concentration of p-type dopant intentionally introduced. In other words, the p-type dopant introduced in the low-VT PMOS channel region may be introduced to lower the net n-type doping concentration, for example. However, in embodiments where the p-type dopant that is intentionally introduced exceeds the concentration of n-type dopant that is present in the channel region, the channel region will have a net p-type doping concentration. Again, such a configuration is atypical for standard PMOS devices, but it can be used to achieve relatively higher drive current for lower voltages.

In some embodiments, the hybrid circuit as described herein may include a multitude of different transistor devices. As previously described, the hybrid circuit may include one or more PMOS devices and/or one or more NMOS devices, in accordance with some embodiments. For instance, the hybrid circuit may include two NMOS devices and two PMOS devices in a CMOS circuit configuration, to provide an example embodiment. Further, in some embodiments, the hybrid circuit may include transistors having a multitude of configurations, such as planar and/or non-planar configurations, where the non-planar configurations may include finned or FinFET configurations (e.g., dual-gate or tri-gate), gate-all-around (GAA) configurations (e.g., nanowire or nanoribbon), or some combination thereof (e.g., beaded-fin configurations), to provide a few examples.

In some embodiments, the hybrid circuit may include MOSFET devices including any suitable semiconductor material (e.g., in the channel region of the devices), such as group IV semiconductor material and/or group III-V semiconductor material. The use of "group IV semiconductor material" (or "group IV material" or generally, "IV") herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and so forth. The use of "group III-V semiconductor material" (or "group III-V material" or generally, "III-V") herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), and so forth. Note that group III may also be known as the boron group or IUPAC group 13, group IV may also be known as the carbon group or IUPAC group 14, and group V may also be known as the nitrogen family or IUPAC group 15, for example. For instance, in some embodiments, the techniques can be used to benefit transistors having channel region material that includes at least one of silicon (Si), germanium (Ge), tin (Sn), indium (In), gallium (Ga), arsenic (As), phosphorous (P), or aluminum (Al), to provide some examples.

In some embodiments, the non- volatile logic and/or memory element included in the hybrid circuit described herein may include one or more spintronic devices, ferroelectric devices, and/or magnetoresistive devices, such as spintronic-logic devices (e.g., ASL, MESO logic, and/or mLogic devices), ferroelectric random-access memory (F-RAM) devices, and/or magneroresistive random-access memory (MRAM) devices, respectively. For instance, in some embodiments, the non-volatile element may include at least one of a spin-torque switched magnet, spin-hall effect- switched magnet, ferroelectric field-effect transistor (FeFET), ferroelectric capacitor, magnetic tunnel junction (MTJ), resistive random-access memory (ReRAM or RRAM), or magneto-electric-switched magnet. In some embodiments, a given nonvolatile element may include one or more transistors to sense and/or amplify the state of the given non-volatile element. Note that although the non-volatile elements are referred to as such herein, such non-volatile elements may include memory and/or logic capabilities. For instance, spintronic logic devices can be used to perform the operation of storing a memory state (or a bit) even when not receiving power. Therefore, the element (which may be a device or a circuit) capable of storing a state even when not receiving power (e.g., during power gating or when the computing device in which the element is contained is powered off) is generally referred to herein as a non-volatile element.

In some embodiments, the low-VT MOSFET devices and/or the non-volatile element of the hybrid circuit may be operatively coupled to a power gating transistor or circuit to provide a clocked power supply and/or to modulate the current provided to the low-VT MOSFET devices and/or non-volatile element. Thus, in some such embodiments, the power gating transistor or circuit can be used to provide or not provide current to the low-VT MOSFET devices as desired. For instance, a control signal may be used to determine whether or not current is to be provided to the low-VT MOSFET devices. If current is provided, the low-VT MOSFET devices can then perform logic operations as desired and the output of those operations can then be provided to the corresponding non-volatile element to store the state of that low-VT MOSFET output. Current can then be shut off from the low-VT MOSFET via the power gating transistor or circuit to prevent standby leakage while retaining the output that the low-VT MOSFET produced (via the non-volatile element). In some embodiments, the non-volatile element may also receive a clocked power supply from power gate transistor or circuit. In instances where both the low-VT MOSFET devices and the non-volatile element of a hybrid circuit received clocked power supplies, those clocked power supplies may be modulated via the same power gate transistor/circuit or a different power gate transistors/circuits. In embodiments where power gate transistors are employed, they may be formed as a low-VT MOSFET device as described herein or as a standard MOSFET device, depending on the particular configuration.

Note that, as used herein, the expression "X includes at least one of A or B" refers to an X that may include, for example, just A only, just B only, or both A and B. To this end, an X that includes at least one of A or B is not to be understood as an X that requires each of A and B, unless expressly so stated. For instance, the expression "X includes A and B" refers to an X that expressly includes both A and B. Moreover, this is true for any number of items greater than two, where "at least one of those items is included in X. For example, as used herein, the expression "X includes at least one of A, B, or C" refers to an X that may include just A only, just B only, just C only, only A and B (and not C), only A and C (and not B), only B and C (and not A), or each of A, B, and C. This is true even if any of A, B, or C happens to include multiple types or variations. To this end, an X that includes at least one of A, B, or C is not to be understood as an X that requires each of A, B, and C, unless expressly so stated. For instance, the expression "X includes A, B, and C" refers to an X that expressly includes each of A, B, and C. Likewise, the expression "X included in at least one of A or B" refers to an X that may be included, for example, in just A only, in just B only, or in both A and B. The above discussion with respect to "X includes at least one of A or B" equally applies here, as will be appreciated.

Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools may indicate an integrated circuit (IC) including a hybrid circuit that includes at least one low-VT NMOS device and at least one low-VT PMOS device as described herein co-integrated with (e.g., electrically connected to or otherwise operatively coupled to) a non-volatile element as also described herein. For instance, one or more of the tools may be used to reverse engineer an IC to determine if such a hybrid circuit is present. For example, in the case of detecting a low-VT MOSFET device that includes one or more of the modifications described herein, the specific transistor device may be electrically tested at the S/D level, such as by measuring the current-voltage (IV) curve of the device and determining if it is sufficiently low (e.g., sub-300, sub-250, or sub-200 eV). In addition, doping type of low-VT MOSFET can be detected using conductive atomic-force microscopy (AFM) analysis to be either: low and opposite type to the S/D doping; or the same type as the S/D doping. Either such scenario will indicate that the low-VT adjustments described herein have been employed. Numerous configurations and variations will be apparent in light of this disclosure.

Architecture and Methodology

Figure 1 illustrates a schematic diagram of an example integrated circuit (IC) 100 showing two non- volatile logic circuits that include hybrid circuits 115 employing low-threshold voltage (VT) MOSFET co-integrated with non- volatile elements, in accordance with some embodiments of the present disclosure. In Figure 1, IC 100 illustrates an example application of the hybrid circuits described herein, as can be understood based on this disclosure. Further, the hybrid circuits 115 that are included in IC 100 are provided as examples, where each hybrid circuit 115 includes a CMOS circuit (including two NMOS devices 116 and two PMOS devices 117) and a non- volatile element 119. In some embodiments that utilize hybrid circuits described herein, not every gate requires non-volatility. In such embodiments, modified MOSFET devices (e.g., modified from standard configurations, as described herein) may be used to implement the main logic blocks in conjunction with non-volatile elements (e.g., non-volatile spintronic devices) to store states even when power is not provided, such as during power gating or power off conditions. Therefore, the hybrid circuits that combine low-VT MOSFET devices and nonvolatile elements as described herein enable higher performance and lower power consumption relative to what can be achieved individually by either MOSFET devices or non-volatile elements on their own. In some embodiments, the structures and techniques described herein may be used to benefit IC devices/circuits of varying scales, such as those having critical dimensions in the micrometer (micron) range and/or in the nanometer (nm) range (e.g., formed at the 22, 14, 10, 7, 5, or 3 nm process nodes, or beyond).

In the example embodiment of Figure 1, IC 100 includes a first logic circuit 101 and a second logic circuit 102, each of which include a multitude of transistors as shown. In some embodiments, logic circuits 101, 102 may each implement a digital logic function and/or other suitable functions as will be apparent in light of this disclosure. In this example embodiment, logic circuits 101 and 102 each include multiple low-VT transistors 116 and 117, where transistors 116 are low-VT NMOS devices and transistors 117 are low-VT PMOS devices. For instance, the low-VT NMOS devices 116 and low-VT PMOS devices 117 each include at least one modification from standard NMOS and PMOS devices, respectively, that enable the use of relatively low VDDs and relatively low VTs that are not achievable using standard scaled logic devices (e.g., scaled to include sub-100 or sub-50 nm gate lengths). Such modifications are described in more detail herein.

Continuing with example IC 100 of Figure 1, the low-VT NMOS devices 116 and low-VT PMOS devices 117 receive inputs (e.g., inputs 110) from transistors in logic circuits 101 and 102, as shown. In addition, low-VT NMOS devices 116 and low-VT PMOS devices 117 are configured in CMOS circuits as shown, where two low-VT NMOS devices 116 and two low-VT PMOS devices 117 are electrically connected to each non- volatile element 119. The output from the CMOS circuit of each hybrid circuit 115 is a MOSFET output 118, which is the input to non- volatile element 119 of each hybrid circuit 115. In such a configuration, the output from the CMOS circuit of each hybrid circuit 115 can be provided to its corresponding non-volatile element 119, such that the non- volatile element 119 can store the state determined by the logic CMOS circuit even when one or more components of hybrid circuit 115 are not receiving power (e.g., as a result of power gating or a power off condition). Non- volatile elements 119 have outputs 120 (or 120a or 120b), and in some cases, the output of a non- volatile element 119 may be connected to another logic circuit, such as is the case of output 120b going from the bottom non- volatile element 119 of the first logic circuit 101 to an input in the second logic circuit 102, as shown in the example IC 100 of Figure 1.

In addition, in the example embodiment of Figure 1, the multitude of low-VT transistors 116 and 117 of each logic circuit 101, 102 are powered by (or otherwise operatively coupled to) a clocked power supply 114. However, such clocked power supplies 114 need not be utilized, and thus, they are not present in other embodiments. In still other embodiments, the clocked power supplies 114 may be provided via a different configuration (e.g., that does not utilize a single power gate transistor 113 per logic circuit). Referring back to the example IC 100 of Figure 1, a clocked power supply 114 is provided for each of the first and second logic circuits 101, 102 by power gate transistors 113. The power gate transistors 113 may be low-VT transistors as described herein (e.g., with one or more of the modifications from standard transistors described herein) and/or they may be standard transistors (e.g., MOSFET devices without any of the modifications described herein). In the particular IC configuration 100 of Figure 1, the drain or drain region of each power gate transistor 113 is electrically connected to a power supply 112 as shown. Further, the gate of each power gate transistor 113 is controlled by an enable signal 111 that determines whether or not power from power supply 112 is provided to the remainder of the transistors in the respective logic circuits 101, 102. Thus, power gate transistors 113 can reduce power consumption by shutting off the current to the remainder of the transistors in logic circuits 101 and 102 to thereby reduce stand-by or leakage power, for example.

In some embodiments, the non- volatile elements 119 of hybrid circuits 115 may be powered by (or otherwise operatively coupled to) a clocked power supply. For instance, in the example IC 100 of Figure 1, non- volatile elements 119 that receive input from the first logic circuit 101 are powered by clocked power supply 124 as shown. The clocked power supply 124 is controlled by power gate transistor 123, which may be a low-VT transistor as described herein or may be a standard transistor, for example. In the particular IC configuration 100 of Figure 1, the drain or drain region of power gate transistor 123 is electrically connected to a power supply 122 as shown. Further, the gate of power gate transistor 123 is controlled by an enable signal 121 that determines whether or not power from power supply 122 is provided to the non- volatile elements 119 with which power gate transistor 123 is electrically connected (or otherwise operatively coupled). However, such a clocked power supply 124 need not be utilized. For instance, the non- volatile elements 119 that receive input from second logic circuit 102 do not have a clocked power supply. In still other embodiments, clocked power supplies may be provided via a different configuration (e.g., that does not utilize power gate transistor 123 as described herein). For instance, in some embodiments, the low-VT MOSFET devices 116 and 117 of hybrid circuit 115 may share the same clocked power supply. By way of example to illustrate such an embodiment, clocked power supply 114 may instead provide power to the non- volatile elements 119 that receive power from clocked power supply 124, such that power gate transistor 113 would control the power provided to the low-VT MOSFET devices 116 and 117 of first logic circuit 101 and the non- volatile elements 119 that receive input therefrom. Thus, in some embodiments, one or more of the MOSFET devices and/or one or more of the non-volatile elements included in a hybrid circuit as described herein may receive power from clocked power supplies for, e.g., power gating purposes.

Figure 2 illustrates a schematic diagram of an example hybrid circuit 215 implementation that includes low-VT MOSFET devices 216, 217 co-integrated with non- volatile element 219, in accordance with some embodiments of the present disclosure. Example hybrid circuit 215 of Figure 2 is similar to example hybrid circuit 115 of Figure 1, except that the layout is different for ease of illustration and description. Thus, the previous relevant description with respect to hybrid circuit 115 is equally applicable to hybrid circuit 215, and accordingly, the same last two digits of identifying numbers are used for similar features. For instance, hybrid circuit 215 of Figure 2 includes two low-VT NMOS devices 216 and two low-VT PMOS devices 217 in a CMOS circuit configuration that provides MOSFET output 218 to non-volatile element 219, just as hybrid circuit 115 of Figure 1 includes two low-VT NMOS devices 116 and two low-VT PMOS devices 117 in a CMOS circuit configuration that provides MOSFET output 118 to nonvolatile element 119. The inputs to the MOSFET devices 216, 217 in Figure 2 are also indicated, with such inputs including VSS 231 (e.g., the ground or negative power supply), Input-A 232, Input-B 233, and VDD 234 (e.g., the positive power supply) as shown. As can be understood based on the diagram, Input-A 232 and Input-B 233 are used to control the gates of the MOSFET devices 216, 217, while VSS 231 and VDD 234 provide power supplies. Further, the output of hybrid circuit 215 is non- volatile output 220 that may be provided even without the MOSFET devices 216, 217 receiving power (e.g., during power gating or power off events), as non- volatile element 219 can be used to store a state (e.g., high or low state) determined by MOSFET output 218, which is similar to the output of hybrid circuits 115 being non-volatile outputs 120 (or 120a or 120b). Note that Figure 2 is depicted such that it can be matched up with the corresponding cross-sectional IC view of Figure 3, as will be described in more detail below.

Figure 3 illustrates an example cross-sectional IC view of a portion of the example hybrid circuit 215 of Figure 2, in accordance with some embodiments of the present disclosure. The cross-sectional IC view in Figure 3 is an example implementation of co -integrating low-VT, low- VDD CMOS with at least one non- volatile element to form a hybrid circuit capable of achieving low-power, non- volatile logic. In more detail, all of hybrid circuit 215 is shown in the cross- sectional circuit-level view of Figure 3, except for the low-VT PMOS device 217 receiving Input-A 232, as that low-VT PMOS device 217 is formed at a different location along the Z-axis as compared to the cross-sectional view of Figure 3. Also note that the cross-sectional view is along the channel of the transistor, such that the source region, channel region, drain region, and gate stack of the transistor devices are shown. Further note that the elements from the schematic diagram of the hybrid circuit 215 of Figure 2 are indicated in Figure 3 to illustrate the correlation between the elements. Thus, the previous relevant description with respect to similarly numbered items is equally applicable to the structure of Figure 3. The techniques for forming the IC structure of Figure 3 may include any suitable semiconductor device fabrication techniques, such as lithography, etching, deposition, epitaxial growth, hardmasking, cleaning, polishing, planarizing, ion implantation, annealing, and/or any other suitable processes as will be apparent in light of this disclosure.

Substrate 300, in some embodiments, may be: a bulk substrate including group IV semiconductor material (e.g., Si, Ge, SiGe), group III-V semiconductor material, and/or any other suitable material(s) as will be apparent in light of this disclosure; an X on insulator (XOI) structure where X is one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material) and the insulator material is an oxide material or dielectric material or some other electrically insulating material, such that the XOI structure includes the electrically insulating material layer between two semiconductor layers; or some other suitable multilayer structure where the top layer includes one of the aforementioned semiconductor materials (e.g., group IV and/or group III-V semiconductor material). The use of "group IV semiconductor material" (or "group IV material" or generally, "IV") herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and so forth. The use of "group III-V semiconductor material" (or "group III-V material" or generally, "III-V") herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), and so forth. Note that group III may also be known as the boron group or IUPAC group 13, group IV may also be known as the carbon group or IUPAC group 14, and group V may also be known as the nitrogen family or IUPAC group 15, for example. In some embodiments, substrate 300 may be a bulk Si wafer, for example.

In some embodiments, substrate 300 may be doped with any suitable n-type and/or p-type dopant. For instance, in the example case of Figure 3, substrate 300 may be doped with p-type dopant (at least near the top surface of the substrate) such that the channel regions 363 of the NMOS devices 216 can be formed in that p-type doped substrate material. As can be understood, the opposite may be true (e.g., substrate 300 may be n-type doped) if the NMOS devices were formed using a well (such as well 370), in accordance with some embodiments. In the case of a Si substrate, the Si may be p-type doped using a suitable acceptor (e.g., boron) or n- type doped using a suitable donor (e.g., phosphorous, arsenic), to provide some example cases. However, in some embodiments, substrate 300 may be undoped/intrinsic or nominally doped (such as including a dopant concentration of less than 1E15 atoms per cubic cm), for example. In some embodiments, substrate 300 may include a surface crystalline orientation described by a Miller index of (100), (110), or (111), or its equivalents, as will be apparent in light of this disclosure.

Although substrate 300, in this example embodiment, is shown as having a thickness (dimension in the Y-axis direction) similar to other layers/features for ease of illustration, in some instances, substrate 300 may be much thicker than the other layers, such as having a thickness in the range of 50 to 950 microns, for example, or any other suitable thickness as will be apparent in light of this disclosure. In some embodiments, substrate 300 may be used for one or more other IC devices, such as various diodes (e.g., light -emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various radio frequency (RF) devices, various sensors, or any other suitable semiconductor or IC devices, depending on the end use or target application. Accordingly, in some embodiments, the structures described herein may be included in a system-on-chip (SoC) application, as will be apparent in light of this disclosure.

Well 370 of the example IC structure of Figure 3, in some embodiments, is used to provide a differently doped semiconductor material region for forming the PMOS device channel regions 373, as compared to the NMOS device channel regions 363 being formed using substrate 300. As previously described, the opposite configuration may also be utilized in other embodiments, where a well may be used to help form the NMOS device channel regions 363, for example. Further still, in some embodiments, well 370 need not be present. In some such embodiments, the NMOS and PMOS devices may be electrically isolated from each other using other suitable features (e.g., isolating dielectric regions), for example. Well 370 may be formed using any suitable processing. For instance, in some embodiments, well 370 may be formed by ion implantation, such that well 370 is native to substrate 300 but has a different net doping concentration. In other embodiments, well 370 may be formed by removing a portion of substrate 300 and depositing the material of well 370, for example. Well 370 may have any suitable depth (dimension in the Y-axis direction) and width (dimension in the X-axis direction), and such dimensions may be determined based on the size of the transistor devices formed therefrom, for example.

The processing to form the example IC structure of Figure 3 may continue with forming dummy gate stacks, such as in embodiments employing a gate last fabrication process flow. However, in the example structure of Figure 3, the final gate stacks (including gate dielectrics 367, 377 and gate electrodes 368, 378) are shown. Formation of a dummy gate stack may include depositing dummy gate dielectric material and dummy gate electrode material, patterning the dummy gate stack, depositing gate spacer material, and performing a spacer etch, in accordance with some embodiments. In some such embodiments, dummy gate dielectric (e.g., dummy oxide material) and dummy gate electrode (e.g., dummy poly-silicon material) may be used for a replacement gate process. Note that side-wall spacers 366, 376, referred to generally as gate spacers (or simply, spacers), would be formed on either side of the dummy gate stack, and such spacers 366, 376 can be used to help determine the channel length and/or to help with replacement gate processes, for example. As can be understood based on this disclosure, the dummy gate stack (and spacers 366, 376) can help define the channel region and source/drain (S/D) regions of each transistor device, where the channel region is below the dummy gate stack (as it will be located below the final gate stack), and the S/D regions are on either side of and adjacent to the channel region. Spacers 366, 376 may include any suitable material, such as any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure. Note that in some embodiments, as previously described, the techniques described herein need not include forming a dummy gate stack, such that a final gate stack may be formed in the first instance. Also note that in some such embodiments, spacers 366, 376 may be formed on both sides of the final gate stacks (such as is shown in Figure 3) to help electrically isolate the gate stack and/or to help with subsequent processing.

The final gate stack in this example embodiment includes gate dielectric 367 and gate electrode 368 (between gate spacers 366) for the NMOS devices 216 and gate dielectric 377 and gate electrode 378 (between gate spacers 376) for the PMOS devices 217. Such final gate stacks or structures can be formed regardless of whether a gate first fabrication process flow is employed (e.g., such that the final gate stack is formed prior to the S/D regions being formed) or a gate last fabrication process flow is employed (e.g., such that the final gate stack is formed after the S/D regions have been formed and utilizing a dummy gate stack, as previously described). The processing may include any suitable techniques. For instance, in a gate first flow, the final gate stack may be formed using the techniques described above to form the dummy gate stack. In a gate last flow, the final gate stack may be formed by depositing interlayer dielectric (ILD) material 380, planarizing and/or polishing (e.g., via chemical mechanical polishing/planarization) the structure to reveal the dummy gate stack, removing the dummy gate stack via etching, and replacing that dummy gate stack by depositing the final gate stack materials. In any such embodiments, ILD material 380 may include any desired electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure. Note that although ILD material 380 is illustrated as a single feature, it may be formed using multiple layers that may or may not be visually distinguishable (e.g., the same ILD material 380 may be used for each layer and the interfaces may not be readily identified in the end structure). Also note that although the gate dielectrics 367, 377 are only shown below their respective gate electrodes 368, 378 in the example embodiment of Figure 3, in other embodiments, a given gate dielectric may also be present on one or both sides of its corresponding gate electrode, such that the gate dielectric may also be between the corresponding gate electrode and one or both of the gate spacers, for example.

In a given final gate stack, the gate dielectrics 367, 377 may include, for example, any suitable oxide (such as silicon dioxide), high-k dielectric material, and/or any other suitable material as will be apparent in light of this disclosure. Examples of high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when high-k dielectric material is used. The gate electrodes 368, 378 may include a wide range of materials, such as polysilicon or various suitable metals or metal alloys, such as tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), and/or tantalum nitride (TaN), for example. Further, in some embodiments, the gate electrodes may include gold (Au), copper (Cu), magnesium (Mg), aluminum (Al), and/or nickel (Ni). In some embodiments, a given gate dielectric and/or gate electrode may include a multilayer structure of two or more material layers, for example. In some embodiments, a given gate dielectric and/or gate electrode may include grading (e.g., increasing and/or decreasing) the content/concentration of one or more materials in at least a portion of the feature(s). In some embodiments, one or more additional layers may be present in a given final gate stack. Numerous different gate stack configurations will be apparent in light of this disclosure.

In some embodiments, a given low-VT NMOS device 216 included in the hybrid circuits described herein may be formed with a relatively lower metal work function value for surface 369 compared to standard NMOS devices. As shown in Figure 3, surface 369 is the surface of gate electrode 368 of NMOS device 216 that is closest to gate dielectric 367, and thereby, surface 369 is also the closest surface of gate electrode 368 to channel region 373, in this example embodiment. In other words, the relevant surface 369 of gate electrode 368 is touching or in physical contact with gate dielectric 367, in this example embodiment. As can be understood, in embodiments where gate electrode 368 includes a multilayer structure, the relevant surface 369 would be of the layer that is closest to gate dielectric 367. In embodiments where a given low-VT MOS device 216 is formed with the relevant gate electrode surface 369 having a relatively lower work function value, that relatively lower work function value may be less than approximately 4.5 eV, as 4.5 eV is the approximate work function value of the relevant surface of a standard NMOS gate electrode. Thus, in some such embodiments, the relatively lower work function value of the relevant gate electrode surface 369 of the low-VT NMOS device 216 may be at most 4.4, 4.35, 4.3, 4.25, 4.2, 4.15, 4.1, 4.05, 4, 3.9, 3.8, 3.7, 3.6, or 3.5 electron volts (eV), and/or the relatively lower work function value of the relevant gate electrode surface 369 of the low-VT NMOS 216 device may be in the range of 3.5-3.8, 3.5-4.0, 3.5-4.2, 3.5-4.4, 3.8-4.0, 3.8-4.2, 3.8-4.3, 3.8-4.4, 4.0-4.1 4.0-4.2, 4.0-4.3, 4.0-4.4, 4.2-4.3, or 4.2-4.4 eV, for example. Other suitable work function values, ranges, and thresholds will be apparent in light of this disclosure. As is known to those having ordinary skill in the art, a number of factors can affect the work function value of the relevant gate electrode surface 369, such as the materials involved, processing temperatures, thicknesses involved, and so forth, such that a number of different metals or metal alloys may be used to achieve the relatively higher work function values described herein.

In some embodiments, a given low-VT PMOS device 217 included in the hybrid circuits described herein may be formed with a relatively higher metal work function value for surface 379 compared to standard PMOS devices. As shown in Figure 3, surface 379 is the surface of gate electrode 378 of PMOS device 217 that is closest to gate dielectric 377, and thereby, surface 379 is also the closest surface of gate electrode 378 to channel region 363, in this example embodiment. In other words, the relevant surface 379 of gate electrode 378 is touching or in physical contact with gate dielectric 377, in this example embodiment. As can be understood, in embodiments where gate electrode 378 includes a multilayer structure, the relevant surface 379 would be of the layer that is closest to gate dielectric 377. In embodiments where a given low- VT PMOS device 217 is formed with the relevant gate electrode surface 379 having a relatively higher work function value, that relatively higher work function value may be greater than approximately 4.5 electron volts (eV), as 4.5 eV is the approximate work function value of the relevant surface of a standard PMOS gate electrode. Thus, in some such embodiments, the relatively higher work function value of the relevant gate electrode surface 379 of the low-VT PMOS device 217 may be at least 4.6, 4.65, 4.7, 4.75, 4.8, 4.85, 4.9, 4.95, 5, 5.1, 5.2, 5.3, 5.4, or 5.5 electron volts (eV), and/or the relatively higher work function value of the relevant gate electrode surface 379 of the low-VT PMOS device 217 may be in the range of 4.6-4.8, 4.6-5.0, 4.6-5.2, 4.6-5.5, 4.7-4.9, 4.7-5.0, 4.7-5.1, 4.7-5.3, 4.7-5.5, 4.8-5.0, 4.8-5.2, 4.8-5.5, 5.0-5.2, 5.0- 5.5, or 5.2-5.5 eV, for example. Other suitable work function values, ranges, and thresholds will be apparent in light of this disclosure. As is known to those having ordinary skill in the art, a number of factors can affect the work function value of the relevant gate electrode surface 379, such as the materials involved, processing temperatures, thicknesses involved, and so forth, such that a number of different metals or metal alloys may be used to achieve the relatively higher work function values described herein.

Source/drain (S/D) regions 362 and 372 of the example IC structure of Figure 3 may be formed using any suitable techniques. For instance, in some embodiments, the S/D regions may be formed by driving dopant into the semiconductor material of the S/D regions, such as via ion implantation. In some embodiments, the material located at the S/D regions may be removed and replaced with the final S/D region material. In some embodiments, the S/D regions may be formed via cladding the S/D regions with the final S/D region material. Thus, the final S/D regions may be formed using various different processing techniques as can be understood based on this disclosure. Note that the S/D regions are referred to herein as such for ease of description, but each S/D region may be either a source region or a drain region from the perspective of a given transistor. However, in some embodiments, a given S/D region may act as both a source region and a drain region. For example, the middle S/D region 362 between the NMOS devices 216 may act as a drain region for the left-most NMOS device 216 that receives Input-A 232 at its gate structure and that same middle S/D region 362 may also act as a source region for the right-most NMOS device 216 that received Input-B 233 at its gate structure.

In some embodiments, the S/D regions 362 and 372 may include any suitable semiconductor material as will be apparent in light of this disclosure, such as monocrystalline group IV semiconductor material and/or monocrystalline group III-V semiconductor material. For instance, a given S/D region may include at least one of silicon, germanium, gallium, arsenide, indium, or aluminum. In some embodiments, a given S/D region may include n-type and/or p-type dopant. For instance, the S/D regions 362 of the NMOS devices 216 may include n-type dopant and the S/D regions 372 of the PMOS devices 217 may include p-type dopant. In some embodiments, the dopant may be included in a concentration in the range of 1E17 to 5E22 atoms per cubic cm, for example. In some embodiments, a given S/D region may include grading (e.g., increasing and/or decreasing) of the concentration of one or more materials within the region, such as the grading of a semiconductor material component concentration and/or the grading of the dopant concentration, for example. For instance, in some such embodiments, the dopant concentration included in a given S/D region may be graded such that it is lower near the corresponding channel region and higher near the corresponding S/D contact, which may be achieved using any suitable processing, such as tuning the amount of dopant in the reactant flow

(e.g., during an in-situ doping scheme), to provide an example. In some embodiments, a given S/D region may include a multilayer structure that includes at least two compositionally different material layers. In some embodiments, a given S/D region may be raised such that it extends higher than a corresponding channel region (e.g., in the vertical or Y-axis direction).

Channel regions 363 and 373 of the example IC structure of Figure 3 may be formed using any suitable techniques. For instance, in some embodiments, a given channel region may be formed from the substrate material, and thus, the given channel region would be native to the substrate material. This is the case for channel regions 363 in the example structure of Figure 3, as those channel regions 363 are native to substrate 300. However, even when channel regions are native to the substrate, modifications may occur, such as doping the substrate material to a desired net doping concentration. For instance, well 370 may be formed in such a manner that substrate 300 includes a first net doping concentration and well 370 includes a second net doping concentration. In other embodiments, a given channel region may be formed by depositing or growing material above the substrate, where such material may be formed on the substrate or formed in a feature (e.g., a trench, fin-shaped trench, well) after removing a portion of the substrate (e.g., via etch processing) to form that feature. Thus, numerous different channel region materials and configurations can be achieved.

In some embodiments, the channel regions 363, 373 may include any suitable semiconductor material as will be apparent in light of this disclosure, such as monocrystalline group IV semiconductor material and/or monocrystalline group III-V semiconductor material. For instance, a given channel region may include at least one of silicon, germanium, gallium, arsenide, indium, or aluminum. In some embodiments, the channel region may be doped (e.g., with any suitable n-type and/or p-type dopant) at a dopant concentration in the range of IE 16 to 1E22 atoms per cubic cm, for example, or the channel region may be intrinsic/undoped (or nominally undoped, with a dopant concentration less than 1E15 atoms per cubic cm), depending on the particular configuration. For example, in the case of group IV semiconductor materials, the group IV material may be p-type doped using a suitable acceptor (e.g., boron) or n-type doped using a suitable donor (e.g., phosphorous, arsenic). In another example, in the case of group III-V semiconductor material, the group III-V material may be p-type doped using a suitable acceptor (e.g., beryllium, zinc) or n-type doped using a suitable donor (e.g., silicon). In some embodiments, a given channel region may include grading (e.g., increasing and/or decreasing) of the concentration of one or more materials within the feature, such as the grading of a semiconductor material component concentration and/or the grading of the dopant concentration, for example. In some embodiments, a given channel region may include a multilayer structure that includes at least two compositionally different material layers (such as is the case for beaded-fin transistor configurations).

In some embodiments, a given low-VT NMOS device 216 included in the hybrid circuits described herein may be formed with a relatively lower net p-type doping concentration in the channel region 363 compared to standard NMOS devices. For instance, that relatively lower concentration may be at most a net p-type doping concentration of approximately 1E18 atoms per cubic cm, as 1E18 atoms per cubic cm of net p-type doping is the approximate minimum concentration for a standard NMOS channel region. Thus, in some such embodiments, the relatively lower net p-type doping concentration in the NMOS channel region 363 may be at most 5E17, 1E17, 5E16, 1E16, 5E15, or 1E15 atoms per cubic cm, and/or the relatively lower net p-type doping concentration in the NMOS channel region 363 may be in the range of 0-1E16, 0-5E16, 0-1E17, 0-5E17, 1E15-1E16, 1E15-5E17, or 5E15-5E16 atoms per cubic cm, for example. In some such embodiments, the relatively lower net p-type doping concentration may even cross over to a net n-type doping concentration, if the electron concentration present in the channel region exceeds the hole concentration, for example. Other suitable doping concentration values, ranges, and thresholds will be apparent in light of this disclosure. Note that net doping concentration as described herein with reference to a given transistor channel region includes accounting for p-type and n-type dopants present in that given channel region. For instance, if a transistor channel region includes 2E16 atoms per cubic cm of p-type dopant and 1E16 atoms per cubic cm of n-type dopant, then the net doping concentration would be p-type in the amount of 1E16 atoms per cubic cm, as there would be a larger hole concentration than electron concentration.

In some embodiments, a given low-VT NMOS device 216 included in the hybrid circuits described herein may be formed with significant levels of n-type dopant intentionally included in the channel region 363, which is atypical for standard NMOS devices. Those significant levels of n-type dopant may be at least 1E15 atoms per cubic cm, as 1E15 atoms per cubic cm is a nominal amount of dopant to be included in a semiconductor material feature. Thus, in some such embodiments, the significant levels of n-type dopant intentionally introduced in the low-VT NMOS channel region 363 may be at least 1E15, 5E15, 1E16, 5E16, 1E17, 5E17, or 1E18 atoms per cubic cm, and/or the significant levels of n-type dopant intentionally introduced in the NMOS channel region 363 may be in the range of 1E15-1E17, 1E15-1E20, 1E16-1E18, 1E16- 1E20, 1E17-1E19, or 1E17-1E20 atoms per cubic cm, for example. Other suitable intentional n- type dopant values, ranges, and thresholds will be apparent in light of this disclosure. Note that in some such embodiments, p-type dopant may also be present in the low-VT NMOS channel region 363, such that the net doping concentration may not be the same as the included concentration of n-type dopant intentionally introduced. In other words, the n-type dopant introduced in the low-VT NMOS channel region 363 may be introduced to lower the net p-type doping concentration, for example. However, in embodiments where the n-type dopant that is intentionally introduced exceeds the concentration of p-type dopant that is present in the channel region 363, the channel region 363 will have a net n-type doping concentration. Again, such a configuration is atypical for standard NMOS devices, but it can be used to achieve relatively higher drive current for lower voltages.

In some embodiments, a given low-VT PMOS device 217 included in the hybrid circuits described herein may be formed with a relatively lower net n-type doping concentration in the channel region 373 compared to standard PMOS devices. For instance, that relatively lower concentration may be at most a net n-type doping concentration of approximately 1E18 atoms per cubic cm, as 1E18 atoms per cubic cm of net n-type doping is the approximate minimum concentration for a standard PMOS channel region. Thus, in some such embodiments, the relatively lower net n-type doping concentration in the low-VT PMOS channel region 373 may be at most 5E17, 1E17, 5E16, 1E16, 5E15, or 1E15 atoms per cubic cm, and/or the relatively lower net n-type doping concentration in the low-VT PMOS channel region 373 may be in the range of 0-1E16, 0-5E16, 0-1E17, 0-5E17, 1E15-1E16, 1E15-5E17, or 5E15-5E16 atoms per cubic cm, for example. In some such embodiments, the relatively lower net n-type doping concentration may even cross over to a net p-type doping concentration, if the hole concentration present in the channel region exceeds the electron concentration, for example. Other suitable doping concentration values, ranges, and thresholds will be apparent in light of this disclosure. Note that, as previously described, net doping concentration as described herein with reference to a given transistor channel region includes accounting for p-type and n-type dopants present in that given channel region. For instance, if a transistor channel region includes 2E16 atoms per cubic cm of n-type dopant and IE 16 atoms per cubic cm of p-type dopant, then the net doping concentration would be n-type in the amount of 1E16 atoms per cubic cm, as there would be a larger electron concentration than hole concentration.

In some embodiments, a given low-VT PMOS device 217 included in the hybrid circuits described herein may be formed with significant levels of p-type dopant intentionally included in the channel region 373, which is atypical for standard PMOS devices. Those significant levels of p-type dopant may be at least 1E15 atoms per cubic cm, as 1E15 atoms per cubic cm is a nominal amount of dopant to be included in a semiconductor material feature. Thus, in some such embodiments, the significant levels of p-type dopant intentionally introduced in the low-VT PMOS channel region 373 may be at least 1E15, 5E15, 1E16, 5E16, 1E17, 5E17, or 1E18 atoms per cubic cm, and/or the significant levels of p-type dopant intentionally introduced in the low- VT PMOS channel region 373 may be in the range of 1E15-1E17, 1E15-1E20, 1E16-1E18, 1E16-1E20, 1E17-1E19, or 1E17-1E20 atoms per cubic cm, for example. Other suitable intentional p-type dopant values, ranges, and thresholds will be apparent in light of this disclosure. Note that in some such embodiments, n-type dopant may also be present in the low- VT PMOS channel region 373, such that the net doping concentration may not be the same as the included concentration of p-type dopant intentionally introduced. In other words, the p-type dopant introduced in the low-VT PMOS channel region 373 may be introduced to lower the net n-type doping concentration, for example. However, in embodiments where the p-type dopant that is intentionally introduced exceeds the concentration of n-type dopant that is present in the channel region 373, the channel region 373 will have a net p-type doping concentration. Again, such a configuration is atypical for standard PMOS devices, but it can be used to achieve relatively higher drive current for lower voltages.

As can be seen in Figure 3, each channel region 363, 373 is between a corresponding set of S/D regions 362, 372. In other words, the S/D regions are adjacent a corresponding channel region. As can be understood based on this disclosure, the channel region is at least below the gate stack, in this example embodiment. In other words, the gate stack or structure is at least above the channel region. For instance, in the case of a finned transistor configuration, the channel region may be below and between the gate stack, as the stack is formed on three sides as is known to those having ordinary skill in the art. However, if the transistor device were inverted and bonded to what will be the end substrate, then the channel region may be above the gate. Therefore, in general, the gate structure and channel region may include a proximate relationship, where the gate structure is near the channel region such that it can exert control over the channel region in an electrical manner, in accordance with some embodiments. Further, in the case of a nanowire (or nanoribbon or GAA) transistor configuration, the gate stack may completely surround each nanowire/nanoribbon in the channel region (or at least substantially surround each nanowire, such as surrounding at least 70, 80, or 90% of each nanowire). Further still, in the case of a planar transistor configuration, the gate stack may only be above the channel region.

In some embodiments, the gate length, which may be measured as the length of surface 369 or 379 in the X-axis direction in Figure 3, may be any suitable length as will be apparent in light of this disclosure. For instance, in some embodiments, the gate length may be in the range of 3-100 nm (e.g., 3-10, 3-20, 3-30, 3-50, 5-10, 5-20, 5-30, 5-50, 5-100, 10-20, 10-30, 10-50, 10- 100, 20-30, 20-50, 20-100, or 50-100 nm) or greater, for example. In some embodiments, the gate length may be less than a given threshold, such as less than 100, 50, 45, 40, 35, 30, 25, 20, 15, 10, 8, or 5 nm, or less than some other suitable threshold as will be apparent in light of this disclosure. In some embodiments, the techniques enable maintaining a desired device performance when scaling to such low thresholds, such as sub-100, sub-50, sub-40, sub-30, or sub-20 nm thresholds, as can be understood based on this disclosure. In some embodiments, the gate length may approximate the channel length. However, in other embodiments, the channel length may be less, such as in devices employing source/drain tips or extensions.

S/D contacts 364 and 374 of the example IC structure of Figure 3 may be formed using any suitable techniques. For example, the techniques may include forming one or more layers of interlay er dielectric (ILD) material 380, etching contact trenches above the S/D regions 362, 372, and depositing the S/D contact material to form the resulting S/D contacts 364, 374. In some embodiments, S/D contact formation may include silicidation, germanidation, III-V-idation, and/or annealing processes, where such processing may be performed, e.g., to form an intervening contact layer before forming the bulk contact metal structure. In the example structure of Figure 3, it can be understood that S/D contacts 364, 374 are in physical contact with and electrically connected to S/D regions 362, 372. In some embodiments, S/D contacts 364, 374 may include aluminum or tungsten, although any suitable conductive metal or metal alloy (or other suitable electrically conductive material) can be used, such as silver, nickel-platinum, or nickel-aluminum, for example. In some embodiments, one or more of the S/D contacts 364, 374 may include a resistance reducing metal and a contact plug metal, or just a contact plug, for instance. Example contact resistance reducing metals include, for instance, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel aluminum, and/or other such resistance reducing metals or alloys. Example contact plug metals include, for instance, aluminum, copper, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy may be used. In some embodiments, S/D contacts 364, 374 may employ low work-function metal material(s) and/or high work-function metal material(s), depending on the particular configuration. In some embodiments, one or more additional layers may be present in the S/D contact regions, such as adhesion layers (e.g., titanium nitride) and/or liner or barrier layers (e.g., tantalum nitride), if so desired.

The above description of the processing used to form the example IC structure of Figure 3 has been describing features formed in the front end or front-end-of-line (FEOL) of the IC (indicated as 391 in Figure 3). For instance, in this example embodiment, the MOS devices 216 and PMOS devices 217 are formed at the device level or front end of the IC as shown. The non- volatile element 319 (which is representative of the non-volatile element 219 in the hybrid circuit 215 of Figure 2) is shown as being formed above the device level in the back end or back- end-of-line (BEOL) location of the IC (indicated as 392 in Figure 3), which begins when the first metallization layer including interconnects 331, 318, and 334 is formed. Although non-volatile element 319 is shown in the example embodiment of Figure 3 as being formed at a back end location of the IC (e.g., above at least one interconnect line/level), the present disclosure is not intended to be so limited. For instance, in some embodiments, the non-volatile element 319 may be formed at a front end location of the IC, at the same device level (in the Y-axis direction) that MOS devices 216 and PMOS devices 217 are formed. In some such embodiments, at least a portion of the processing of non- volatile element 319 may be performed simultaneously with the processing of NMOS devices 216 and/or PMOS devices 217, or the processing may be performed separately. However, in embodiments where the non-volatile element 319 is formed at a back end IC location, as is the case with the example structure of Figure 3, a smaller IC footprint may be achieved for the hybrid circuit, based on the use of vertical co -integration of the components. Thus, non- volatile element 319 may be formed using any suitable techniques, where such techniques are based, at least in part, on the particular non-volatile element 319 being employed.

Non- volatile element 319 (which is representative of non-volatile element 219 from the hybrid circuit of Figure 2) may include one or more non-volatile logic and/or memory elements, in accordance with some embodiments. For instance, in some such embodiments, non-volatile element 319 may include one or more spintronic devices, ferroelectric devices, and/or magnetoresistive devices, such as spintronic-logic devices (e.g., ASL, MESO logic, and/or mLogic devices), ferroelectric random-access memory (F-RAM) devices, and/or magneroresistive random-access memory (MRAM) devices, respectively. For example, in some embodiments, the non- volatile element 319 may include at least one of a spin-torque switched magnet, spin-hall effect- switched magnet, ferroelectric field-effect transistor (FeFET), ferroelectric capacitor, magnetic tunnel junction (MTJ), resistive random-access memory (ReRAM or RRAM), or magneto-electric-switched magnet. In some embodiments, a given non- volatile element 319 may include at least one transistor to sense and/or amplify the state of the given non- volatile element. Note that although the non-volatile elements 319 (and 219 and 119) are referred to as such herein, such non-volatile elements may include memory and/or logic capabilities. For instance, spintronic logic devices can be used to perform the operation of storing a memory state (or a bit) even when not receiving power. Therefore, the element 319 (which may be a device or a circuit) capable of storing a state even when not receiving power (e.g., during power gating or when the computing device in which the element is contained is powered off) is generally referred to herein as a non-volatile element.

The example IC of Figure 3 illustrates that the S/D contacts 364 and 374 in the middle of the structure shown are electrically connected to non-volatile element 319 through interconnects 318 to provide MOSFET output 218. In some embodiments, interconnects 318 may be considered an interconnect and a via, such as where the bottom layer of feature 318 may be considered an interconnect as it runs primarily in the X-axis direction and the top layer of feature 318 may be considered a via as it runs primarily in the Y-axis direction. However, both layers of feature 318 are referred to herein as interconnects, or simply, an interconnect, for ease of description. In general, in some embodiments, interconnects 318, as well as interconnects 331, 334, and 320, may be formed using any suitable processing, such as forming one or more layers of ILD material 380, removing portions of the ILD material 380 layer(s) via etch processing, and then depositing the interconnect material to form the resulting structure shown. In some such embodiments, the processing is performed in a layer-by-layer approach moving upward in the positive Y-axis direction.

In some embodiments, interconnects 318, 331, 334, and 320 may include any suitable electrically conductive material, such as one or more metals and/or metal alloys. For instance, in some embodiments, the interconnects 318, 331, 334, and 320 may include copper and/or tungsten, to provide some examples. In the example IC structure of Figure 3, interconnect 331, which leads to and is operatively coupled with VSS 231, is electrically connected to (and in physical contact with) the left-most S/D contact 364, as shown. Further, interconnect 334, which leads to and is operatively coupled with VDD 234, is electrically connected to (and in physical contact with) the right-most S/D contact 374, as is also shown. Further still, the non- volatile output 220 from non- volatile element 319 is provided via interconnect 320, as is also shown. As can be understood based on this disclosure, non-volatile element 319 is configured to store states based on MOSFET output 218, even when the MOS devices 216 and/or PMOS devices 217 are not receiving power (e.g., during power gating or other events where those devices do not receive power), such that non- volatile element 319 can provide non-volatile output 220.

Figures 4A-B illustrate perspective views of an example IC including non-planar transistors configured in accordance with the low-VT MOSFET devices of Figures 2 and 3, in accordance with some embodiments of the present disclosure. Note that although the cross- sectional IC view of Figure 3 may be depicting the MOSFET devices 216, 217 as having planar configurations, the view may also be a cross-sectional view along a fin (such as the fin including channel region 463 in Figures 4A-B), such that the IC structure of Figure 3 may be depicting non-planar MOSFET devices 216, 217. Regardless, Figures 4A-B help illustrate how the MOSFET devices may be formed with non-planar configurations. For ease of description, the same last two digits are used to identify similar features between those in the NMOS devices 216 of Figure 3 and those in the NMOS devices of Figures 4A-B. However, the features in Figure 3 are listed in the 300s and the features in Figures 4A-B are listed in the 400s. Thus, the previous relevant description with respect to the features of Figure 3 is equally applicable to the similar features of Figures 4A-B. For example, the previous relevant description with respect to substrate 300 is equally applicable to substrate 400, the previous relevant description with respect to S/D regions 362 is equally applicable to S/D regions 462, the previous relevant description with respect to gate dielectric 367 and gate electrode 368 is equally applicable to gate dielectric 467 and gate electrode 468, and so forth. Further note that the non-planar transistor configurations and the relevant description herein related thereto is equally applicable to the low- VT NMOS devices as it is to the low-VT PMOS devices.

Note that as can be seen when comparing the IC structure of Figure 3 and the IC structures of Figures 4A-B, there are differences between the structures, such as the shape of spacers 366 compared to spacers 466, patterning/shading to help visually distinguish different features, and so forth. Generally, the patterning/shading of any of the features in the figures is not intended to limit the present disclosure in any manner. Also note that the four lines of transistors shown in Figures 4A-B are separated and electrically isolated by shallow trench isolation (STI) regions 430, where such STI material 430 may be formed using any suitable techniques, such as forming fins from the top of substrate 400 via shallow trench recess (STR) processing, depositing the STI material between the fins, and recessing the STI material, for example. In some embodiments, STI material 430 (which may be referred to as an STI layer or STI regions) may include any suitable electrically insulating material, such as one or more dielectric, oxide (e.g., silicon dioxide), and/or nitride (e.g., silicon nitride) materials. In some embodiments, the material of STI regions 430 may be selected based on the material of substrate 400. For instance, in the case of a Si substrate, the STI material 430 may be selected to be silicon dioxide or silicon nitride, to provide some examples. Note that ILD layer 480 is shown as transparent in the example structures of Figures 4A-B to allow for the underlying features to be seen; however, the present disclosure is not intended to be so limited. Further note that in some cases, ILD material 480 and STI material 430 may not include a distinct interface as shown in Figures 4A-B, particularly where, e.g., the ILD material 480 and STI material 430 are the same dielectric material (e.g., where both are silicon dioxide). As previously described, Figures 4A-B are provided to illustrate example non-planar transistor configurations that one or more of the NMOS and/or PMOS devices of a given hybrid circuit can benefit from, in accordance with some embodiments. For instance, a finned MOSFET (or FinFET) is a MOSFET transistor built around a thin strip of semiconductor material (generally referred to as a fin). The conductive channel of the FinFET device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such a FinFET design is sometimes referred to as a tri-gate transistor. Other types of FinFET configurations are also available, such as so-called double-gate FinFETs, in which the conductive channel principally resides only along the two sidewalls of the fin (and not along the top of the fin). A nanowire transistor (sometimes referred to as a gate-all-around (GAA) or nanoribbon transistor) is configured similarly to a fin-based transistor, but instead of a finned channel region where the gate is on three portions (and thus, there are three effective gates), one or more nanowires are used for the channel region and the gate material generally surrounds each nanowire. Other non-planar transistor configurations will be apparent in light of this disclosure, and such non-planar configurations may be employed to increase gate control, increase drive current, increase S/D contact area (and thereby reduce S/D contact resistance), and/or provide other benefits based on the particular configuration.

Figure 4A illustrates four different non-planar channel regions, which include native fin channel region 463, replacement material fin channel region 473, beaded-fin channel region 483, and nanowire channel region 493. Note that when a dummy gate is employed, the channel region of the transistor devices may be modified after the dummy gate has been removed via any desired processing. Such processing of a given channel region may include various different techniques, such as removing and replacing the channel region with replacement material, doping the channel region as desired, forming the channel region into one or more nanowires (or nanoribbons) for a gate-all-around (GAA) transistor configuration, forming the channel region into a beaded-fin configuration, cleaning/polishing the channel region, and/or any other suitable processing as will be apparent in light of this disclosure. For instance, finned channel region 463 is native to substrate 400 and it may or may not have been processed in any suitable manner, such as being doped in a desired manner (e.g., with intentional dopant opposite of what is typical for the type of device it is). Further, finned channel region 473 includes replacement material that is not native to substrate 400, where such replacement material may have been blanket deposited and formed into the fin shown, formed in a fin-shaped trench, or formed using some other suitable processing as is known to those having ordinary skill in the art.

To provide yet another example, nanowire channel region 493 may have been formed after a dummy gate was removed and the channel regions were exposed, by converting an original finned structure at that location into the nanowires 493 shown using, for example, any suitable techniques. For instance, the original finned channel region may have included a multilayer structure, where one or more of the layers were sacrificial and selective etch processing was performed to remove those sacrificial layers and release the nanowires 493. As shown in Figure 4A, nanowire channel region 493 includes 2 nanowires (or nanoribbons) in this example case. However, a nanowire (or nanoribbon or GAA) transistor formed using the techniques disclosed herein may include any number of nanowires (or nanoribbons) such as 1, 3, 4, 5, 6, 7, 8, 9, 10, or more, depending on the desired configuration. In some embodiments, a nanowire or nanoribbon may be considered fin-shaped where the gate stack wraps around each fin-shaped nanowire or nanoribbon in a GAA transistor configuration. To provide yet another example, beaded-fin channel region 483 is a hybrid between a finned channel region and a nanowire channel region, where the sacrificial material (shown with grey shading) that may have been completely removed to release nanowires was instead only partially removed to form the resulting beaded- fin structure 483 shown. Such a beaded-fin channel region structure may benefit from, for instance, increased gate control (e.g., compared to a finned channel region structure) while also having, for instance, relatively reduced parasitic capacitance (e.g., compared to a nanowire channel region structure). Therefore, numerous different channel region configurations can be employed in the hybrid circuits described herein.

Figure 5 illustrates a method 500 of forming an IC including a hybrid circuit that includes low-VT MOSFET devices co-integrated with a non-volatile element, in accordance with some embodiments of the present disclosure. Method 500, in this example embodiment includes providing 502 a substrate, such as substrate 300 or 400 as described herein. Method 500 continues with forming 504 at least one low-VT NMOS device as described herein above the substrate, which may or may not be native to the substrate in some manner (e.g., the channel region of the at least one low-VT NMOS device may be native to the substrate). Method 500 continues with forming 506 at least one low-VT PMOS device as described herein above the substrate, the low-VT PMOS device being electrically connected to the at least one low-VT NMOS device. Note that the at least one PMOS device may or may not be native to the substrate in some manner (e.g., the channel region of the at least one low-VT PMOS device may be native to the substrate). As can be understood based on this disclosure, in some embodiments, the at least one low-VT NMOS device and the at least one low-VT PMOS device together may form a CMOS circuit 507, and that CMOS circuit may include, in some embodiments, two low-VT NMOS and PMOS devices, for example.

Method 500 continues with forming 508 a non-volatile element as described herein that is electrically connected to the low-VT NMOS and PMOS devices and configured to store a memory state based on output from the low-VT NMOS and PMOS devices. In some embodiments, the formation of the non- volatile element may occur at the IC device level/front end/front-end-of-line or at the IC back end/back-end-of-line or some combination thereof (e.g., a portion of the non-volatile element is formed in the front end and a portion is formed in the back end). As can be understood based on this disclosure, the low-VT NMOS and PMOS devices together with the non- volatile element may form a hybrid circuit 515 as described herein (such as hybrid circuit 115 or 215). Method 500 optionally continues with forming 510 one or more power gate transistors as described herein and configured to provide a clocked power supply and/or modulate the current flow to at least one of the low-VT NMOS device(s), the low-VT PMOS device(s), or the non- volatile element. Method 500 continues with completing 512 IC processing as desired, such as forming other IC devices, forming back end interconnect or metallization lines, and/or any other suitable processing as can be understood based on this disclosure. Note that although the processes of method 500 are shown in a particular order in Figure 5, the present disclosure is not intended to be so limited. For instance, in some embodiments, 504 may be performed prior to 502, or 502 and 504 may be performed simultaneously (at least in part), or 506 may be performed prior to 502 and 504, and so forth. Numerous variations and configurations will be apparent in light of the present disclosure.

Example System

Figure 6 illustrates a computing system 1000 implemented with integrated circuit structures formed using the techniques described herein, in accordance with some embodiments of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.

Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatuses, and other structures configured for computing or processing information.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit (IC) including: an n-channel metal-oxide-semiconductor field-effect transistor (NMOS) device including a first channel region and a first gate structure at least above the first channel region; a p-channel transistor metal-oxide-semiconductor field- effect transistor (PMOS) device electrically connected to the NMOS device, the PMOS device including a second channel region and a second gate structure at least above the second channel region; and a non-volatile storage element electrically connected to the NMOS and PMOS devices. The NMOS device includes a surface of the first gate structure having a work function value of at most 4.4 electron volts (eV), net p-type doping levels of at most 1E16 atoms per cubic centimeter (cm) in the first channel region, and/or n-type dopant in a concentration of at least 1E17 atoms per cubic cm in the first channel region. The PMOS device includes a surface of the second gate structure having a work function value of at least 4.6 eV, net n-type doping levels of at most 1E16 atoms per cubic cm in the second channel region, and/or p-type dopant in a concentration of at least IE 17 atoms per cubic cm in the second channel region. In some cases, the non-volatile storage element is configured to store one of at least two available states based on output from the MOS and PMOS devices.

Example 2 includes the subject matter of Example 1, wherein the first gate structure includes a first gate electrode and a first gate dielectric, the first gate dielectric between the first gate electrode and the first channel region, the surface of the first gate structure being the surface of the first gate electrode closest to the first gate dielectric, and that surface having a work function value of at most 4.4 eV.

Example 3 includes the subject matter of Example 1 or 2, wherein the second gate structure includes a second gate electrode and a second gate dielectric, the second gate dielectric between the second gate electrode and the second channel region, the surface of the second gate structure the surface of the second gate electrode closest to the second gate dielectric, and that surface having a work function value of at least 4.6 eV.

Example 4 includes the subject matter of any of Examples 1-3, wherein the NMOS device includes net p-type doping levels of at most IE 16 atoms per cubic cm in the first channel region.

Example 5 includes the subject matter of any of Examples 1-4, wherein the NMOS device includes n-type dopant in a concentration of at least 1E17 atoms per cubic cm in the first channel region.

Example 6 includes the subject matter of any of Examples 1-5, wherein the PMOS device includes net n-type doping levels of at most 1E16 atoms per cubic cm in the second channel region.

Example 7 includes the subject matter of any of Examples 1-6, wherein the PMOS device includes p-type dopant in a concentration of at least 1E17 atoms per cubic cm in the second channel region.

Example 8 includes the subject matter of any of Examples 1-7, wherein the first and/or second channel regions includes both p-type and n-type dopants.

Example 9 includes the subject matter of any of Examples 1-8, wherein the first and/or second channel regions include monocrystalline group IV semiconductor material.

Example 10 includes the subject matter of any of Examples 1-9, wherein the first and/or second channel regions include monocrystalline group III-V semiconductor material.

Example 11 includes the subject matter of any of Examples 1-10, wherein the first and/or second gate structures include gold, copper, magnesium, aluminum, and/or nickel. Example 12 includes the subject matter of any of Examples 1-11, wherein the MOS and PMOS devices each include non-planar transistor configurations.

Example 13 includes the subject matter of any of Examples 1-12, wherein the non-volatile storage element is one of a spintronic device, a ferroelectric device, and a magnetoresistive device.

Example 14 includes the subject matter of any of Examples 1-12, wherein the non-volatile storage element is a memory device.

Example 15 includes the subject matter of any of Examples 1-12, wherein the non-volatile storage element is a part of a memory circuit.

Example 16 includes the subject matter of any of Examples 1-12, wherein the non-volatile storage element is part of a memory circuit of a microprocessor or central processing unit.

Example 17 includes the subject matter of any of Examples 1-12, wherein the non-volatile storage element is part of a memory circuit of a graphics processing unit.

Example 18 includes the subject matter of any of Examples 1-12, wherein the non-volatile storage element is a logic gate.

Example 19 includes the subject matter of any of Examples 1-12, wherein the non-volatile storage element is part of a gate-level logic circuit.

Example 20 includes the subject matter of any of Examples 1-12, wherein the non-volatile storage element is part of a field programmable gate array (FPGA).

Example 21 includes the subject matter of any of Examples 1-20, wherein the non-volatile storage element includes a spin-torque switched magnet, a spin-hall effect-switched magnet, a ferroelectric field-effect transistor, a ferroelectric capacitor, a magnetic tunnel junction, a resistive random-access memory, and/or a magneto-electric-switched magnet.

Example 22 includes the subject matter of any of Examples 1-21, further including at least one additional transistor configured sense the memory state and/or amplify the memory state of the non-volatile storage element.

Example 23 includes the subject matter of any of Examples 1-22, further including at least one additional transistor configured to modulate current supply to the NMOS and PMOS devices.

Example 24 includes the subject matter of any of Examples 1-23, further including at least one additional transistor configured to modulate current supply to the non-volatile storage element. Example 25 includes the subject matter of any of Examples 1-24, further including a complementary metal-oxide-semiconductor (CMOS) circuit that includes at least two of the NMOS devices and at least two of the PMOS devices, such that the CMOS circuit includes at least four transistors.

Example 26 is a computing system including the subject matter of any of Examples 1-25.

Example 27 is an integrated circuit (IC) including: a complementary metal-oxide- semiconductor (CMOS) circuit including at least two n-channel metal-oxide- semiconductor field-effect transistor (NMOS) devices; at least two p-channel metal-oxide-semiconductor field- effect transistor (PMOS) devices; and a non-volatile element configured to receive input from the CMOS circuit. Each NMOS device includes an n-channel region and further includes a gate electrode surface closest to the n-channel region having a work function value of at most 4.4 electron volts (eV), net p-type doping levels of at most 1E16 atoms per cubic centimeter (cm) in the n-channel region, and/or n-type dopant in a concentration of at least 1E17 atoms per cubic cm in the n-channel region. Each PMOS device includes a p-channel region and further includes a gate electrode surface closest to the p-channel region having a work function value of at least 4.6 eV, net n-type doping levels of at most 1E16 atoms per cubic cm in the p-channel region, and/or p-type dopant in a concentration of at least IE 17 atoms per cubic cm in the p-channel region. In some cases, the non-volatile element is further configured to store one of at least two available memory states based on the CMOS input.

Example 28 includes the subject matter of Example 27, wherein each NMOS device includes at least two of a gate electrode surface closest to the n-channel region having a work function value of at most 4.4 electron volts (eV), net p-type doping levels of at most 1E16 atoms per cubic centimeter (cm) in the n-channel region, or n-type dopant in a concentration of at least IE 17 atoms per cubic cm in the n-channel region.

Example 29 includes the subject matter of Example 27 or 28, wherein each PMOS device includes at least two of a gate electrode surface closest to the p-channel region having a work function value of at least 4.6 eV, net n-type doping levels of at most 1E16 atoms per cubic cm in the p-channel region, or p-type dopant in a concentration of at least 1E17 atoms per cubic cm in the p-channel region.

Example 30 includes the subject matter of any of Examples 27-29, wherein each NMOS device includes all three of a gate electrode surface closest to the n-channel region having a work function value of at most 4.4 electron volts (eV), net p-type doping levels of at most 1E16 atoms per cubic centimeter (cm) in the n-channel region, and n-type dopant in a concentration of at least IE 17 atoms per cubic cm in the n-channel region.

Example 31 includes the subject matter of any of Examples 27-30, wherein each PMOS device includes all three of a gate electrode surface closest to the p-channel region having a work function value of at least 4.6 eV, net n-type doping levels of at most 1E16 atoms per cubic cm in the p-channel region, and p-type dopant in a concentration of at least IE 17 atoms per cubic cm in the p-channel region.

Example 32 includes the subject matter of any of Examples 27-31, wherein the n-channel regions and/or the p-channel regions include both p-type and n-type dopants.

Example 33 includes the subject matter of any of Examples 27-32, wherein the n-channel regions and/or the p-channel regions include monocrystalline group IV semiconductor material.

Example 34 includes the subject matter of any of Examples 27-33, wherein the n-channel regions and/or the p-channel regions include monocrystalline group III-V semiconductor material.

Example 35 includes the subject matter of any of Examples 27-34, wherein at least one of the gate electrodes includes gold, copper, magnesium, aluminum, and/or nickel.

Example 36 includes the subject matter of any of Examples 27-35, wherein all of the MOS and PMOS devices include non-planar transistor configurations.

Example 37 includes the subject matter of any of Examples 27-36, wherein the non- volatile element is one of a spintronic device, a ferroelectric device, and a magnetoresistive device.

Example 38 includes the subject matter of any of Examples 27-37, wherein the nonvolatile element includes a spin-torque switched magnet, a spin-hall effect- switched magnet, a ferroelectric field-effect transistor, a ferroelectric capacitor, a magnetic tunnel junction, a resistive random-access memory, and/or a magneto-electric-switched magnet.

Example 39 includes the subject matter of any of Examples 27-38, further including at least one additional transistor configured to sense the memory state and/or amplify the memory state of the non-volatile element.

Example 40 includes the subject matter of any of Examples 27-39, further including at least one additional transistor configured to modulate current supply to the NMOS and PMOS devices. Example 41 includes the subject matter of any of Examples 27-40, further including at least one additional transistor configured to modulate current supply to the non-volatile element.

Example 42 is a mobile computing system including the subject matter of any of Examples 27-41.

Example 43 is a method of forming an integrated circuit (IC), the method including: forming an n-channel metal-oxide-semiconductor field-effect transistor ( MOS) device including a first channel region and a first gate structure at least above the first channel region; forming a p-channel transistor metal-oxide-semiconductor field-effect transistor (PMOS) device including a second channel region and a second gate structure at least above the second channel region, the PMOS device electrically connected to the NMOS device; and forming a non- volatile storage element electrically connected to the NMOS and PMOS devices. The NMOS device includes a surface of the first gate structure having a work function value of at most 4.4 electron volts (eV), net p-type doping levels of at most 1E16 atoms per cubic centimeter (cm) in the first channel region, and/or n-type dopant in a concentration of at least 1E17 atoms per cubic cm in the first channel region. The PMOS device includes a surface of the second gate structure having a work function value of at least 4.6 eV, net n-type doping levels of at most 1E16 atoms per cubic cm in the second channel region, and/or p-type dopant in a concentration of at least IE 17 atoms per cubic cm in the second channel region. In some cases, the non- volatile storage element is configured to store one of at least two available states based on output from the NMOS and PMOS devices.

Example 44 includes the subject matter of Example 43, wherein the non- volatile storage element is formed at a back-end-of-line location of the IC.

Example 45 includes the subject matter of Example 43, wherein the non-volatile storage element is formed at a front-end-of-line location of the IC.

Example 46 includes the subject matter of any of Examples 43-45, wherein the first gate structure includes a first gate electrode and a first gate dielectric, the first gate dielectric between the first gate electrode and the first channel region, the surface of the first gate structure being the surface of the first gate electrode closest to the first gate dielectric, and that surface having a work function value of at most 4.4 eV.

Example 47 includes the subject matter of any of Examples 43-46, wherein the second gate structure includes a second gate electrode and a second gate dielectric, the second gate dielectric between the second gate electrode and the second channel region, the surface of the second gate structure the surface of the second gate electrode closest to the second gate dielectric, and that surface having a work function value of at least 4.6 eV.

Example 48 includes the subject matter of any of Examples 43-47, wherein the NMOS device includes net p-type doping levels of at most IE 16 atoms per cubic cm in the first channel region.

Example 49 includes the subject matter of any of Examples 43-48, wherein the NMOS device includes n-type dopant in a concentration of at least 1E17 atoms per cubic cm in the first channel region.

Example 50 includes the subject matter of any of Examples 43-49, wherein the PMOS device includes net n-type doping levels of at most 1E16 atoms per cubic cm in the second channel region.

Example 51 includes the subject matter of any of Examples 43-50, wherein the PMOS device includes p-type dopant in a concentration of at least 1E17 atoms per cubic cm in the second channel region.

Example 52 includes the subject matter of any of Examples 43-51, wherein the first and/or second channel regions include both p-type and n-type dopants.

Example 53 includes the subject matter of any of Examples 43-52, wherein the first and/or second channel regions include monocrystalline group IV semiconductor material.

Example 54 includes the subject matter of any of Examples 43-53, wherein the first and/or second channel regions include monocrystalline group III-V semiconductor material.

Example 55 includes the subject matter of any of Examples 43-54, wherein the first and/or second gate structures include gold, copper, magnesium, aluminum, and/or nickel.

Example 56 includes the subject matter of any of Examples 43-55, wherein the NMOS and PMOS devices each include non-planar transistor configurations.

Example 57 includes the subject matter of any of Examples 43-56, wherein the nonvolatile storage element is one of a spintronic device, a ferroelectric device, and a magnetoresistive device.

Example 58 includes the subject matter of any of Examples 43-57, wherein the nonvolatile storage element includes a spin-torque switched magnet, a spin-hall effect- switched magnet, a ferroelectric field-effect transistor, a ferroelectric capacitor, a magnetic tunnel junction, a resistive random-access memory, and/or a magneto-electric-switched magnet. Example 59 includes the subject matter of any of Examples 43-58, further including forming at least one additional transistor configured to sense the memory state and/or amplify the memory state of the non- volatile storage element.

Example 60 includes the subject matter of any of Examples 43-59, further including forming at least one additional transistor configured to modulate current supply to the NMOS and PMOS devices.

Example 61 includes the subject matter of any of Examples 43-60, further including forming at least one additional transistor configured to modulate current supply to the nonvolatile storage element.

Example 62 includes the subject matter of any of Examples 43-61, further including forming a complementary metal-oxide- semiconductor (CMOS) circuit that includes at least two of the NMOS devices and at least two of the PMOS devices, such that the CMOS circuit includes at least four transistors.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.