Title:
NON-VOLATILE LOGIC GATE ELEMENT
Document Type and Number:
WIPO Patent Application WO/2013/187193
Kind Code:
A1
Abstract:
The present invention is configured as a non-volatile logic gate element, having as one storage structure a resistor network in which at least three or more non-volatile resistor elements are connected, comprising: a reference resistor network which is a reference resistor with which the storage structure manifests resilience, with respect to a resistance value of the resistor network which forms the storage structure; a write unit which, when storing data in the resistor network, alternatively rewrites a value of each non-volatile resistor element which forms the resistor network as either a maximum or a minimum which is associated with a read-out logic value; and a logic circuit structure which employs as the logic value of the storage structure a value which is obtained by a comparison of the resistor network resistance value and the reference resistor network resistance value.
Inventors:
NEBASHI RYUSUKE (JP)
SAKIMURA NOBORU (JP)
TSUJI YUKIHIDE (JP)
TADA AYUKA (JP)
SUGIBAYASHI TADAHIKO (JP)
HANYU TAKAHIRO (JP)
ENDOH TETSUO (JP)
OHNO HIDEO (JP)
SAKIMURA NOBORU (JP)
TSUJI YUKIHIDE (JP)
TADA AYUKA (JP)
SUGIBAYASHI TADAHIKO (JP)
HANYU TAKAHIRO (JP)
ENDOH TETSUO (JP)
OHNO HIDEO (JP)
Application Number:
PCT/JP2013/064138
Publication Date:
December 19, 2013
Filing Date:
May 15, 2013
Export Citation:
Assignee:
NEC CORP (JP)
UNIV TOHOKU (JP)
UNIV TOHOKU (JP)
International Classes:
H03K19/18; G11C11/15; H01L21/8246; H01L27/105; H01L29/82; H01L43/08
Foreign References:
| JP2005235307A | 2005-09-02 | |||
| JP3812498B2 | 2006-08-23 |
Attorney, Agent or Firm:
IKEDA, Noriyasu et al. (JP)
Noriyasu Ikeda (JP)
Noriyasu Ikeda (JP)
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