Title:
NON-VOLATILE MEMORY DEVICE AND PRODUCTION METHOD THEREOF
Document Type and Number:
WIPO Patent Application WO/2012/070096
Kind Code:
A1
Abstract:
An upright chain memory comprising: a two-level select transistor comprising first select transistors, which are upright transistors disposed in a matrix arrangement, and second select transistors, which are upright transistor formed respectively on the first select transistors; and a plurality of memory cells vertically connected in series on the two-level select transistor. This prevents both of the adjoining select transistors from being selected by their respectively shared gates, makes it possible to independently select a plurality of two-level select transistors respectively, and prevents a reduction in the memory capacity of a non-volatile memory device.
Inventors:
SASAGO YOSHITAKA (JP)
KINOSHITA MASAHARU (JP)
MORIKAWA TAKAHIRO (JP)
SHIMA AKIO (JP)
KOBAYASHI TAKASHI (JP)
KINOSHITA MASAHARU (JP)
MORIKAWA TAKAHIRO (JP)
SHIMA AKIO (JP)
KOBAYASHI TAKASHI (JP)
Application Number:
PCT/JP2010/070769
Publication Date:
May 31, 2012
Filing Date:
November 22, 2010
Export Citation:
Assignee:
HITACHI LTD (JP)
SASAGO YOSHITAKA (JP)
KINOSHITA MASAHARU (JP)
MORIKAWA TAKAHIRO (JP)
SHIMA AKIO (JP)
KOBAYASHI TAKASHI (JP)
SASAGO YOSHITAKA (JP)
KINOSHITA MASAHARU (JP)
MORIKAWA TAKAHIRO (JP)
SHIMA AKIO (JP)
KOBAYASHI TAKASHI (JP)
International Classes:
H01L27/105; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; H01L45/00
Foreign References:
| JPH0274069A | 1990-03-14 | |||
| JPH06325580A | 1994-11-25 | |||
| JP2007180389A | 2007-07-12 | |||
| JP2008160004A | 2008-07-10 | |||
| JP2008181978A | 2008-08-07 | |||
| JP2009224466A | 2009-10-01 | |||
| JPH10255483A | 1998-09-25 | |||
| JPH1093083A | 1998-04-10 | |||
| JP2009146942A | 2009-07-02 | |||
| JP2010165982A | 2010-07-29 |
Attorney, Agent or Firm:
TSUTSUI, YAMATO (JP)
Tsutsui Daiwa (JP)
Tsutsui Daiwa (JP)
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Claims: