NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

Title:

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

Document Type and Number:

WIPO Patent Application WO/2013/042665

Kind Code:

A1

Abstract:

Proposed is a non-volatile semiconductor memory device in which it is possible to more freely set the voltage used when accumulating charge in a selected memory cell transistor than a conventional one. In the non-volatile semiconductor memory device (1), when accumulating charge in a selected memory cell transistor (115), a high write inhibit voltage is applied through a P-type MOS transistor (9b) and a low write voltage is applied through an N-type MOS transistor (15a). A function for applying a voltage to the selected memory cell transistor (115) or a non-selected memory cell transistor (116) is thereby shared by the separate P-type MOS transistor (9b) and N-type MOS transistor (15a). This makes it possible to separately adjust, for example, the gate and source voltages of each of the P-type and N-type MOS transistors (9b, 15a) and finally to set the gate-substrate voltage to, for example, 4 V or other value.

Inventors:

SHINAGAWA HIROSHI (JP)
KASAI HIDEO (JP)
TANIGUCHI YASUHIRO (JP)

Application Number:

PCT/JP2012/073849

Publication Date:

March 28, 2013

Filing Date:

September 18, 2012

Export Citation:

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Assignee:

FLOADIA CORP (JP)

International Classes:

G11C16/04; G11C16/02

Domestic Patent References:

WO1997008707A1

1997-03-06

Foreign References:

JP2001230332A	2001-08-24
JP2005228446A	2005-08-25
JPH10144807A	1998-05-29

Other References: