Title:
NON-VOLATILE STORAGE ELEMENT ARRAY, AND ITS MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2008/047711
Kind Code:
A1
Abstract:
Over a substrate (26) of a semiconductor chip, there are formed lower electrodes
(22), which are thereover covered with a first inter-layer insulating film (27).
Over the lower electrodes (22), there are formed first contact holes (28) which
extend through the first inter-layer insulating film (27). A low-resistance
layer (29) to form a variable-resistance film (24) is buried in the first contact
holes (28). Moreover, a high-resistance layer (30) is formed over the first
inter-layer insulating film (27) and the low-resistance layer (29), and the
variable-resistance film (24) is constituted as a multi-layered resistance
film including one high-resistance layer (30) and one low-resistance layer
(29). Moreover, this low-resistance layer (29) for constituting a storage
unit (25) is separated from at least the adjoining storage unit (25).
Inventors:
MIKAWA TAKUMI
TAKAGI TAKESHI
KAWASHIMA YOSHIO
ARITA KOJI
TAKAGI TAKESHI
KAWASHIMA YOSHIO
ARITA KOJI
Application Number:
PCT/JP2007/069966
Publication Date:
April 24, 2008
Filing Date:
October 12, 2007
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD (JP)
MIKAWA TAKUMI
TAKAGI TAKESHI
KAWASHIMA YOSHIO
ARITA KOJI
MIKAWA TAKUMI
TAKAGI TAKESHI
KAWASHIMA YOSHIO
ARITA KOJI
International Classes:
H01L27/10
Foreign References:
| JP2006229227A | 2006-08-31 | |||
| JPH08293585A | 1996-11-05 | |||
| JP2006080259A | 2006-03-23 |
Attorney, Agent or Firm:
PATENT CORPORATE BODY ARCO PATENT OFFICE (Bo-eki Bldg.123-1, Higashimachi, Chuo-k, Kobe-shi Hyogo 31, JP)
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