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Title:
NONVOLATILE LOGIC INTEGRATED CIRCUIT AND NONVOLATILE REGISTER ERROR BIT CORRECTION METHOD
Document Type and Number:
WIPO Patent Application WO/2013/132806
Kind Code:
A1
Abstract:
[Problem] If ECC circuits are provided for respective registers, the circuit scale will increase and further, not only the area cost but also the power consumption will increase. The objective of the invention is to arrange that error corrections be performed for all of the registers, while the reduction of the operation frequency being inhibited. [Solution] A nonvolatile logic integrated circuit comprises: a function module configured by use of a plurality of nonvolatile logic element circuits each having a nonvolatile element; an ECC module associated with the function module; and a CPU that controls the function module and the ECC module.

Inventors:
SAKIMURA NOBORU (JP)
NEBASHI RYUSUKE (JP)
TSUJI YUKIHIDE (JP)
TADA AYUKA (JP)
Application Number:
PCT/JP2013/001265
Publication Date:
September 12, 2013
Filing Date:
March 01, 2013
Export Citation:
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Assignee:
NEC CORP (JP)
SAKIMURA NOBORU (JP)
NEBASHI RYUSUKE (JP)
TSUJI YUKIHIDE (JP)
TADA AYUKA (JP)
International Classes:
G11C29/42; G06F1/30; H03K3/356
Domestic Patent References:
WO2009072511A12009-06-11
Foreign References:
JP2003248631A2003-09-05
JP2005327437A2005-11-24
JP2007242162A2007-09-20
JPS62214599A1987-09-21
JP2010079954A2010-04-08
JP2000293989A2000-10-20
JP3768504B22006-04-19
JP2007141372A2007-06-07
JPH0533252U1993-04-30
JP2012256392A2012-12-27
JP2012221536A2012-11-12
JPH0349098A1991-03-01
JPS62206877A1987-09-11
JP2004241004A2004-08-26
Attorney, Agent or Firm:
SHIMOSAKA, NAOKI (JP)
Naoki Shimosaka (JP)
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