NONVOLATILE MEMORY ELEMENT AND METHOD FOR MANUFACTURING SAME

WIPO Patent Application WO/2011/111361

A1

Disclosed is a variable resistance nonvolatile memory element which is capable of suppressing variations in the resistance. Specifically disclosed is a nonvolatile memory element which comprises: a silicon substrate (11); a lower electrode layer (102) that is formed on the silicon substrate (11); a variable resistance layer that is formed on the lower electrode layer (102); an upper electrode layer (104) that is formed on the variable resistance layer; a second interlayer insulating layer (19) that is formed so as to cover at least the lower electrode layer (102) and the lateral surface of the variable resistance layer; a stress relaxation region layer (105) for relaxing the stress on the upper electrode layer (104), said stress relaxation region layer (105) being formed from a material, which has less stress than the insulating layer that is used for the second interlayer insulating layer (19), so as to directly cover at least the upper surface and the lateral surface of the upper electrode layer (104); a second contact (16) that is formed so as to reach the upper electrode layer (104); and a wiring pattern (18) that is connected to the second contact (16).

KAWASHIMA YOSHIO
MIKAWA TAKUMI
HAYAKAWA YUKIO

PCT/JP2011/001315

September 15, 2011

March 07, 2011

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PANASONIC CORP (JP)
KAWASHIMA YOSHIO
MIKAWA TAKUMI
HAYAKAWA YUKIO

H01L27/105; H01L21/768; H01L23/522; H01L45/00; H01L49/00

JP2008192995A	2008-08-21
JP2009124167A	2009-06-04
JP2007027537A	2007-02-01
JP2002280528A	2002-09-27
JP2009260060A	2009-11-05
JP2008218541A	2008-09-18

NII, Hiromori (JP)
New house Extensive 守 (JP)

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