NONVOLATILE MEMORY AND STORAGE DEVICE

WIPO Patent Application WO/2012/014505

A1

In addition to an existing memory device configuration such as a memory cell array, a sense amplifier, a driver, an interface logic, and the like, a semiconductor memory device is provided with a volatile buffer memory having a capacity of one page which is a reading/writing unit of data of a memory cell array, and a data selection circuit which selectively inputs the output from the sense amplifier, the output from the buffer memory, and the exclusive OR of the output from sense the amplifier and the output from the buffer memory, to the buffer memory. Further, in response to the selection of input to the buffer memory by the data selection circuit, a control circuit functions so that the output from the buffer memory is input to at least one of the buffer memory through the data selection circuit and the driver, or is not input to either the buffer memory through the data selection circuit or the driver.

MIZUSHIMA Nagamasa (HITACHI LTD., 292, Yoshida-cho, Totsuka-ku, Yokohama-sh, Kanagawa 17, 〒2440817, JP)
水島　永雅 (〒17 神奈川県横浜市戸塚区吉田町２９２番地　株式会社日立製作所　システム開発研究所内 Kanagawa, 〒2440817, JP)
MIURA Seiji (HITACHI LTD., 280, Higashikoigakubo 1-chome, Kokubunji-sh, Tokyo 01, 〒1858601, JP)

JP2011/052441

February 02, 2012

February 04, 2011

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HITACHI, LTD. (6-6 Marunouchi 1-chome, Chiyoda-ku Tokyo, 80, 〒1008280, JP)
株式会社日立製作所 (〒80 東京都千代田区丸の内一丁目６番６号 Tokyo, 〒1008280, JP)
MIZUSHIMA Nagamasa (HITACHI LTD., 292, Yoshida-cho, Totsuka-ku, Yokohama-sh, Kanagawa 17, 〒2440817, JP)
水島　永雅 (〒17 神奈川県横浜市戸塚区吉田町２９２番地　株式会社日立製作所　システム開発研究所内 Kanagawa, 〒2440817, JP)

G11C13/00; G06F12/16; G11C16/02; G11C16/06

POLAIRE I.P.C. (7-1 Hatchobori 2-chome, Chuo-ku Tokyo, 32, 〒1040032, JP)

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