NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING SAME

WIPO Patent Application WO/2012/005003

A1

A nonvolatile semiconductor memory device comprises: a plurality of memory cell holes (101) formed at respective cross points between a plurality of stripe-shaped first interconnections (10) and a plurality of stripe-shaped second interconnections (20) in a planar view by opening an interlayer insulating layer (80) so as to expose top surfaces of the first interconnections; a plurality of dummy holes (111) formed on the first interconnections and in the interlayer insulating layer so as to reach the top surfaces of the first interconnections; and a stacked structure of a first electrode (30) and a resistance change layer (40) formed inside the memory cell holes and the dummy holes. The area of the first interconnection exposed to the bottom opening portion of one dummy hole is larger than the area of the first interconnection exposed to the bottom opening portion of one memory cell hole. One or more dummy holes are formed on each of the first interconnections.

TSUJI KIYOTAKA
MIKAWA TAKUMI
TOMINAGA KENJI

PCT/JP2011/003902

January 12, 2012

July 07, 2011

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PANASONIC CORP (JP)
TSUJI KIYOTAKA
MIKAWA TAKUMI
TOMINAGA KENJI

H01L27/105; H01L21/288; H01L21/3205; H01L23/52; H01L45/00; H01L49/00

WO2010050094A1

2010-05-06

JP2001185691A	2001-07-06
JP2005311132A	2005-11-04
JP2010093277A	2010-04-22
JPH09306914A	1997-11-28
JP2011066337A	2011-03-31

PATENT CORPORATE BODY ARCO PATENT OFFICE (JP)
Patent business corporation Owner old patent firm (JP)

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