FIELD

[0001] The present disclosure relates to power amplifiers (PAs), and more specifically to an apparatus and a method for applying digital predistortion (DPD) in power amplifiers.

BACKGROUND

[0002] Wireless communication systems typically use power amplifiers to amplify signals prior to over the air transmission. The efficiency of a power amplifier generally impacts the performance of devices such as mobile phones and base stations. High efficiency power amplifiers are typically nonlinear in power output response, and exhibits nonlinear and memory effects. Non-linear amplification may cause out-of-band (OOB) emissions or spectral regrowth and in-band distortions (e.g., error vector magnitude (EVM) degradation). Thus, linearization technologies have been developed in various forms to compensate for non-linear distortion characteristics of an amplifier to ensure stable and high quality signal transmissions. One way to improve a power amplifier’s efficiency and its overall linearity is by digital predistortion, where the input to the power amplifier is digitally predistorted, in order to compensate for the distortion introduced by the power amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Some examples of circuits, apparatuses and/or methods will be described in the following by way of example only. In this context, reference will be made to the accompanying Figures.

[0004] Fig. 1 illustrates a simplified block diagram of an exemplary power amplifier (PA) system, according to one embodiment of the disclosure.

[0005] Fig. 2 illustrates an example implementation of a PA system, according to one embodiment of the disclosure. [0006] Fig. 3 illustrates an example implementation of a power amplifier (PA) system, according to one embodiment of the disclosure.

[0007] FIG. 4 is a block diagram illustrating a multi-feed predistorter circuitry, in accordance with some embodiments.

[0008] Fig. 5 illustrates a flow diagram of a method for applying digital predistortion (DPD) to a power amplifier (PA) circuit in a PA system, according to one embodiment of the disclosure.

[0009] FIG. 6 illustrates example components of a device, in accordance with some embodiments.

DETAILED DESCRIPTION

[0010] In one embodiment of the disclosure, a multi-feed predistorter circuit associated with a power amplifier (PA) system is disclosed. The multi-feed predistorter circuit comprises one or more processors configured to receive an input signal associated with the PA system. The one or more processors is further configured to receive one or more PA measurement signals comprising one or more measured parameter values, respectively associated with the PA circuit and generate a

predistorted input signal, based on the PA input signal and the one or more PA measurement signals. In some embodiments, the one or more processors is further configured to provide the predistorted input signal to a transmitter circuitry comprising the PA circuit, in order to compensate for non-linearities associated with the PA circuit.

In some embodiments, the one or more measured parameter values comprises measured parameter values that are different from measured parameter values associated with a PA output signal and a PA input signal of the PA circuit.

[0011] In one embodiment of the disclosure, an apparatus for applying predistortion to a power amplifier (PA) circuit in a PA system is disclosed. The apparatus comprises a predistortion circuit configured to receive an input signal associated with the PA system. The predistortion circuit is further configured to receive one or more PA measurement signals comprising one or more measured parameter values, respectively associated with the PA circuit and generate a predistorted PA input signal, based on the input signal and the one or more PA measurement signals. In some embodiments, the one or more processors is further configured to provide the predistorted input signal to a transmitter circuitry comprising the PA circuit, in order to compensate for non-linearities associated with the PA circuit. In some embodiments, the one or more measured parameter values comprises measured parameter values that are different from measured parameter values associated with a PA output signal and a PA input signal of the PA circuit.

[0012] In one embodiment of the disclosure, a method for applying predistortion to a power amplifier (PA) circuit associated with a PA system is disclosed. The method comprises receiving, at a predistortion circuit, an input signal associated with the PA system. The method further comprises receiving, at the predistortion circuit, one or more PA measurement signals comprising one or more measured parameter values, respectively associated with the PA circuit and generating, at the predistortion circuit, a predistorted PA input signal, based on the PA input signal and the one or more PA measurement signals. In some embodiments, the method further comprises providing, from the predistortion circuit, the predistorted input signal to a transmitter circuitry comprising the PA circuit, in order to compensate for non-linearities associated with the PA circuit. In some embodiments, the one or more measured parameter values comprises measured parameter values that are different from measured parameter values associated with a PA output signal and a PA input signal of the PA circuit.

[0013] The present disclosure will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. As utilized herein, terms“component,”“system,”“interface,”“circuit ” and the like are intended to refer to a computer-related entity, hardware, software (e.g., in execution), and/or firmware. For example, a component can be a processor (e.g., a microprocessor, a controller, or other processing device), a process running on a processor, a controller, an object, an executable, a program, a storage device, a computer, a tablet PC and/or a user equipment (e.g., mobile phone, etc.) with a processing device. By way of illustration, an application running on a server and the server can also be a component. One or more components can reside within a process, and a component can be localized on one computer and/or distributed between two or more computers. A set of elements or a set of other components can be described herein, in which the term“set” can be interpreted as“one or more.”

[0014] Further, these components can execute from various computer readable storage media having various data structures stored thereon such as with a module, for example. The components can communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network, such as, the Internet, a local area network, a wide area network, or similar network with other systems via the signal).

[0015] As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, in which the electric or electronic circuitry can be operated by a software application or a firmware application executed by one or more processors. The one or more processors can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts; the electronic components can include one or more processors therein to execute software and/or firmware that confer(s), at least in part, the functionality of the electronic components.

[0016] Use of the word exemplary is intended to present concepts in a concrete fashion. As used in this application, the term“or” is intended to mean an inclusive“or” rather than an exclusive“or”. That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then“X employs A or B” is satisfied under any of the foregoing instances. In addition, the articles“a” and“an” as used in this application and the appended claims should generally be construed to mean“one or more” unless specified otherwise or clear from context to be directed to a singular form. Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term

"comprising."

[0017] The following detailed description refers to the accompanying drawings. The same reference numbers may be used in different drawings to identify the same or similar elements. In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the various aspects of various embodiments. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the various embodiments may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the various embodiments with unnecessary detail.

[0018] As indicated above, the efficiency and linearity of a power amplifier can be improved by utilizing digital predistortion (DPD). In typical implementations, the digital predistortion of a power amplifier (PA) is realized by extracting the PA non-linearity model (e.g., determining DPD coefficients associated with the PA) based on the PA output samples and modifying (i.e., predistorting) a PA input signal to the power amplifier based on the determined DPD coefficients. In some embodiments, however, the PA non-linear behavior depends, among other things, on the PA supply voltage and ground voltage. In such embodiments, the supply voltage and the ground voltage of the PA varies due to the PA operation. The PA non-linearity is directly related to the PA supply and ground voltages. Existing implementations of digital predistortion in power amplifiers ignores the non-linearity variation of the PA due to the supply voltage variation, leading to DPD performance degradation.

[0019] Further, as the cellular telephone industry develops new standards for the next generation of cellular telephone technology, the field of envelope tracking (ET) faces new challenges. One such new cellular telephone technology standard that is presently being defined is known as 5G NR (New Radio). Commercial 5G NR deployment is expected to begin in the year 2020, but large-scale field testing is expected to begin in the year 2017. LTE advanced or 5G modulation schemes may feature higher bandwidth and more complex modulation schemes in the uplink than prior standards. The new more complex modulation schemes in the uplink may include higher peak-to-average-power ratio (PAPR) than the modulation schemes of prior standards. Mobile stations or user equipment may be expected to support 200MHz aggregated bandwidth (e.g., 2 c 100MHz) or even higher, and advanced uplink modulation schemes may include an evolved single-carrier frequency-division multiple access (SC-FDMA) scheme (e.g., 256-QAM (quadrature amplitude modulation)) and possibly an orthogonal frequency-division multiplexing (OFDM) scheme such as that currently used for a downlink modulation scheme in the present LTE standard.

[0020] Modulation schemes having a high PAPR imply a low PA efficiency when operating in Average Power Tracking (APT) mode. In the APT mode, the PA circuitry may receive its power supply voltage from a DC-DC converter that adjusts its output voltage based on the average output power target within a time interval, e.g., a transmission slot. Low PA efficiency may be caused by large PA voltage headroom to prevent RF voltage clipping and subsequent degradation of the PA linearity characteristics, e.g., adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM). A lower PA efficiency may cause high battery consumption and excessive heat dissipation in a mobile device. Higher battery consumption may lead to decreased operation time of the mobile device, while excessive heat dissipation may lead to a larger and less desirable size and form factor of the mobile device to dissipate the excess heat.

[0021] ET may improve PA efficiency by facilitating the PA circuitry to operate close to its peak efficiency relatively independent of the PAPR. The ET DC-DC converter, also known as a tracker, may provide an instantaneous power supply voltage to the PA circuitry that follows the instantaneous envelope of the RF signal being amplified by the PA circuitry. The modulation of the power supply voltage provided to the PA circuitry in turn may modulate the compression point of the PA. To achieve preferred gain trajectory (e.g., iso-gain), the PA gain compression point may be varied over time by means of the power supply voltage according to the instantaneous value of the envelope of the RF signal such that the PA compressed gain is constant or follows a preferred trajectory e.g. enabling iso-effciency operation where the supply voltage is selected such that the PA efficiency over instantaneous power is constant or at least higher than other voltage profiles. Using ET, the PA headroom may be < 1 dB. In contrast, the tracker may have a lower efficiency, e.g., about 85%, dependent upon the signal bandwidth, vs. about 95% in APT mode without ET. The overall efficiency of the tracker and PA circuitry may be expressed as the PA efficiency multiplied by the tracker efficiency. At high PAPR, the lower tracker efficiency in ET mode may be overcompensated by the higher PA efficiency, so ET systems may provide superior efficiency for systems with high PAPR.

[0022] However, ET systems present challenges due to bandwidth limitations of their trackers. Typical trackers may support a transmit channel bandwidth of 40 MHz, while next generation trackers may be expected to support 60 MHz or 80 MHz signal transmission bandwidths. Beyond 40 MHz, memory predistortion may be applied to a signal to be transmitted in order to compensate for impairments introduced by the trackers. When tracker bandwidth is too small, the PA power supply voltage may only be modulated according to a low pass filtered version of the RF envelope, such that the PA gain compression point is set according to the low pass filtered version of the RF envelope. Thus, the PA gain compression point may not follow the fast portion of the RF envelope outside the tracking bandwidth, thereby causing the PA gain to no longer be constant, and thereby causing the PA to introduce nonlinearities and distortion into the transmitted signal as the PA gain is modulated by the high frequency part of the RF envelope outside the tracker bandwidth via the PA power supply voltage with a gain compression point that is set by the low frequency part of the RF envelope inside the tracker bandwidth. High frequency gain ripple introduced by a tracker bandwidth that is too low may include intermodulation (IM) products.

[0023] The IM products may be compensated by digital memory predistortion if the PA power supply voltage value is known at every time point in the digital memory predistortion computation to estimate the gain compression (e.g., gain ripple) for the high frequency part of the RF envelope outside the tracker bandwidth, because the PA gain compression point depends upon the absolute level of the PA power supply voltage. Therefore, in order to overcome the above disadvantages, an apparatus and a method for a predistorter circuit is proposed in this disclosure. In particular, an apparatus and a method of a predistorter circuit that utilizes, among other things, the instantaneous PA supply voltage to generate a predistorted PA input signal, in order to compensate for the PA non-linearity is proposed. In some embodiments, the proposed predistorter circuit enables to recover the linearity degrade caused by tracker bandwidth limitation in ET systems.

[0024] Fig. 1 illustrates a simplified block diagram of an exemplary power amplifier (PA) system 100, according to one embodiment of the disclosure. In some

embodiments, the PA system 100 facilitates to provide digital predistortion to PAs. In some embodiments, the PA system 100 described herein can be part of wireless communication devices like mobile phones, base stations etc. The PA system 100 comprises a predistortion circuitry 100a and a transmitter circuitry 100b. In some embodiments, the predistortion circuitry 100a can be part of a baseband (BB) integrated circuit (IC) and the transmitter circuitry 100b can be part of a radio frequency (RF) IC.

In some embodiments, the transmitter circuitry 100b comprises a PA circuit 104, a source circuit 106, and an RF front end (RFFE) circuitry and antenna 130. In some embodiments, however, the transmitter circuitry 100b can comprise more or less than the above components, including a radio-frequency (RF) signal generation circuit 103 configured to generate an RF signal that represents a modulated baseband (BB) signal to be transmitted by the transmitter circuitry 100b. Further, in some embodiments, a part of the source circuit 106 can be included in the transmitter circuitry 100b and another part of the source circuit 106 can be included in the predistortion circuitry 100a.

[0025] In some embodiments, the predistortion circuitry 100a comprises a predistortion circuit 102, a sensing circuit 1 10 and an analog-to-digital converter (ADC) circuit 1 12. However, in other embodiments, the predistortion circuitry 100a can comprise more or less than the above components. For example, in some

embodiments, the sensing circuit 1 10 and the ADC circuit 1 12 can be part of the transmitter circuitry 100b. In some embodiments, the PA circuit 104 is configured to receive a PA input signal 1 17 and generate a PA output signal 1 18 based thereon. In some embodiments, the PA circuit 104 is configured to amplify the PA input signal 1 17 and therefore, in such embodiments, the PA output signal y 1 18 is an amplified version of the PA input signal 1 17. In some embodiments, the PA output signal y 1 18 is provided to the RF front end (RFFE) circuitry and antenna 130 for wireless transmission. In some embodiments, the PA circuit 104 is further configured to receive a supply signal 124 from the source circuit 106. In some embodiments, the source circuit 106 can comprise an envelope tracking source circuitry, the details of which is given in an embodiment below.

[0026] In some embodiments, the PA input signal 1 14 is an upconverted version of a predistorted input signal x’ 1 16 associated with the predistorter circuitry 100a. In some embodiments, the predistorted input signal x’ 1 16 from the predistortion circuit or circuitry 102 is received at an RF signal generation circuit 103 associated with the transmitter circuitry 100b and upconverted from BB domain to RF domain, in order to form the PA input signal 1 17. In some embodiments, the predistorted input signal x’

1 16 is generated at the predistortion circuit 102 based on applying a predistortion to an input signal x 1 14. In some embodiments, the input signal x 1 14 comprises a

modulated baseband (BB) signal, for example, carrying a LTE signal, a 5G NR signal or any other signals including signals that are composed from different standards e.g. 5G NR + LTE, 5G NR + Wifi. In some embodiments, the input signal x 1 14 is predistorted to form the predistorted PA input signal x’ 1 16, in order to compensate for the non- linearities associated with the PA circuit 104. In a first instance associated with the PA circuit 104, the predistorted input signal x’ 1 16 and the input signal x 1 14 are the same. However, from a next instance (e.g., a second instance following the first instance), the predistorted input signal x’ 1 16 and the input signal x 1 14 are different, depending on the predistortion applied by the predistortion circuit 102. In such embodiments, the predistortion circuit 102 is configured to receive the input signal x 1 14 and modify (e.g., predistort) the input signal x 1 14 to form the predistorted input signal x’ 1 16 to be provided to the transmitter circuitry 100b. In some embodiments, the predistorted input signal x’ 1 16 is generated at the predistortion circuit 102 based on computing a predefined predistortion function associated with the predistortion circuit 102. However, in other embodiments, the predistorted input signal x’ 1 16 can be generated differently. In some embodiments, the predistortion circuit 102 is further configured to receive one or more additional signals (different from the input signal x 1 14), to be utilized to generate the predistorted input signal x’ 1 16 (e.g., in order to compute the predistortion function) and therefore, in some embodiments, the predistortion circuit 102 is referred to as a multi-feed predistorter circuit. The predistortion circuit 102 can comprise one or more processors and a memory circuit (not shown), in order to perform the various functions explained herein. In some embodiments, the predistortion function associated with the predistortion circuit 102 comprises an inverse memory model of the PA circuit 104. The key idea behind digital predistortion in power amplifiers to is to apply an inverse distortion (relative to the distortion contributed by the PA circuit 104) to the input signal x 1 14, so that a cascaded system comprising the predistortion circuit 102 (that provides the predistortion) and the PA circuit 104 behaves linearly.

[0027] In order to compute the predistortion function, in some embodiments, a non linearity model associated with the PA circuit 104 is to be extracted/determined. In some embodiments, extracting the non-linearity model associated with the PA circuit 104 comprises determining a plurality of DPD coefficients 120 based on the PA output signal y 1 18. In some embodiments, other parameters, for example, the PA input signal 1 17 or the predistorted input signal x’1 16 or the input signal x 1 14 may also be utilized, in addition to the PA output signal y 1 18, in order to determine the DPD coefficients 120. In some embodiments, the DPD coefficients 120 are determined based on a

scaled/processed version (e.g., captured by means of a directional coupler or a voltage divider circuit) of the PA output signal y 1 18. In some embodiments, the PA system 100 comprises a DPD computation circuit 108 (outside of the predistortion circuit 102) configured to receive the PA output signal y 1 18 (and other parameters as indicated above) and determine the DPD coefficients 120 and provide the determined DPD coefficients 120 to the predistortion circuit 102. However, in other embodiments, the DPD computation circuit 108 may be part of the predistortion circuit 102 and therefore, in such embodiments, the predistortion circuit 102 may be configured to receive the PA output signal y 1 18 (and other parameters as indicated above) and determine the DPD coefficients based thereon (not shown). Further, in some embodiments, the DPD coefficients 120 may be determined external to the PA system 100 and provided to the predistortion circuit 102. In some embodiments, the DPD coefficients 120 may be determined using known methods, for example, indirect learning. However, other methods of determining the DPD coefficients 120 are also contemplated to be within the scope of this disclosure. In some embodiments, it is assumed that the DPD coefficients 120 are not determined in real-time. In such embodiments, it is assumed that the DPD coefficients 120 are determined in a previous training/leaning phase of the predistortion circuit 102 and are available to the predistortion circuit 102, for example, stored in a memory circuit associated with the predistortion circuit 102, prior to receiving the input signal 1 14.

[0028] In some embodiments, the predistortion circuit 102 is further configured to receive one or more PA measurement signals 122b associated with the PA circuit 104. In some embodiments, the one or more PA measurement signals 122b are also utilized to generate the predistorted input signal x’ 1 16 (e.g., in order to compute the predistortion function associated with the predistortion circuit 102). In some

embodiments, the one or more PA measurement signals 122b comprises one or more measured parameter values, respectively associated with the PA circuit 104. In the embodiments described herein, the measured parameter values associated with the PA circuit 104 refers to one or more measurements associated with the PA input signal 1 17, the PA output signal y 1 18, the PA supply signal 124 and the PA circuit 104. In some embodiments, the measured parameter values associated with the one or more PA measurement signals 122b comprises one or more of a supply voltage

measurement, a supply current measurement, a PA voltage standing wave ratio (VSWR) measurement, a temperature measurement and a PA bias associated with the PA circuit 104. However, in other embodiments, PA measurement signals comprising other measured parameter values associated with the PA circuit 104 than above are also contemplated to be within the scope of this disclosure. In some embodiments, the one or more measured parameter values associated with the one or more PA measurement signals 122b comprises measured parameter values that are different from measured parameter values associated with the PA output signal y 1 18 and the PA input signal 1 17. For example, in some embodiments, the one or more measured parameter values associated with the one or more PA measurement signals 122b comprises measured parameter values associated with supply signal 124 (e.g., the supply voltage measurement, supply current measurement etc.) or with the PA circuit 104 itself (e.g., temperature measurement, VSWR etc.), or both. In some

embodiments, utilizing the measured parameter values in order to generate the predistorted PA input signal x’ 1 16 enables real-time adaptation of the digital

predistortion of the PA circuit 104.

[0029] In some embodiments, the PA system 100 further comprises a sensing circuit 1 10 configured to measure/sample the one or more measured parameter values associated with the PA circuit 104 and generate the one or more PA measurement signals 122b/122a based thereon. In this embodiment, the sensing circuit 1 10 is only shown to determine measured parameter values associated with the supply signal 124 and the PA circuit 104. However, in other embodiments, the sensing circuit 1 10 may be configured to determine other measured parameter values associated with the PA circuit 104, for example, associated with the PA input signal 1 17 etc. In some embodiments, the sensing circuit 1 10 can comprise a plurality of sensing circuits configured to measure the one or more measured parameter values associated with the PA circuit 104. In some embodiments, if the one or more PA measurement signals 122a are analog signals, an analog-to-digital converter (ADC) circuit 1 12 is included between the sensing circuit 1 10 and the predistortion circuit 102 to convert the analog PA measurement signals 122a to digital PA measurement signals 122b. However, in other embodiments, if the sensing circuit 1 10 is implemented as a digital measurement interface, then the ADC circuit 1 12 need not be included. In such embodiments, the PA measurement signals 122a and the PA measurement signals 122b are the same.

Further, in some embodiments, part of the one or more PA measurement signals 122a can be analog signals (for which the ADC circuit 1 12 is required) and part of the one or more PA measurement signals 122a can be digital signals (for which the ADC circuit 1 12 is not required).

[0030] The predistortion function associated with the predistortion circuit 102 can be computed/implemented differently in different embodiments. In particular, in different embodiments, the PA measurement signals 122b can be utilized differently, in order to compute the predistortion function associated with the PA circuit 104. For example, in some embodiments, the predistorter circuit 102 can be configured to comprise one or more lookup tables (LUTs) comprising predefined relations between the measured parameter values associated with the one or more PA measurement signals 122b and one or more predistortion functions associated with the predistorter circuit 102. In particular, in one example embodiment, the predistorter circuit 102 can be configured to comprise a lookup table (LUT) comprising a plurality of PA non-linearity models (or predistortion functions) respectively associated with a plurality of supply voltage ranges. Therefore, in this embodiment, based on the supply voltage measurement provided by a corresponding PA measurement signal (e.g., the PA measurement signals 122b), the predistortion function can be chosen. Once the predistortion function is chosen, the predistortion function can be computed using information on the input signal x 1 14 and the DPD coefficients 120, in order to form the predistorted input signal x’ 1 16.

[0031] Further, in another example embodiment, the predistorter circuit 102 can be configured to comprise a plurality of lookup tables (LUTs), each LUT comprising a plurality of PA non-linearity models (or predistortion functions) respectively associated with one or more of the measured parameter values (e.g., current measurement, temperature measurement etc.) associated with the PA measurement signals (e.g., the PA measurement signals 122b). In yet another example embodiment, the predistortion function associated with the predistorter circuit 102 can be computed based on computing one or more memory polynomial equations operating on pairs of the measured parameter values associated with the one or more PA measurement signals; and summing results of computing the one or more memory polynomial equations, the details of which are given in an embodiment below. In addition, in other embodiments, the predistortion function can be computed differently than above, based on utilizing the measured parameter values associated with the one or more PA measurement signals 122b.

[0032] Fig. 2 illustrates an example implementation of a PA system 200, according to one embodiment of the disclosure. In some embodiments, the PA system 200 depicts one possible way of implementation of the PA system 100 in Fig. 1 . In some embodiments, the PA system 200 is similar to the PA system 100 in Fig. 1 , with the source circuit implemented as part of an envelope tracking (ET) system. In some embodiments, the PA system 200 comprises a predistortion circuitry 200a and a transmitter circuitry 200b. In some embodiments, predistortion circuitry 200a may help overcome bandwidth limitations and signal impairments caused by ET circuitry integrated with the transmitter circuitry 200b by recovering the linearity degradations caused by tracker bandwidth limitations. In some embodiments, the transmitter circuitry 200b comprises a PA circuit 204, a tracker circuit 206a, a conditioning circuit 206b and an RF front end (RFFE) circuitry and antenna 230. In some embodiments, the transmitter circuitry 200b may further include RF signal generation circuit 203 configured to generate an RF signal 217 that represents a modulated baseband (BB) signal (i.e., the input signal x 214) to be transmitted by the transmitter circuitry 200b, and then output the RF signal 217 to PA circuit 204. In some embodiments, the predistortion circuitry 200a comprises a predistortion circuit 202, a sensing circuit 210 and an analog-to-digital converter (ADC) circuit 212. Further, in some embodiments, the predistortion circuitry 200a comprises a shaping circuit 206d, a filter circuit 206c and an envelope generation circuit 206e. However, in other embodiments, the predistortion circuitry 200a can comprise more or less than the above components. For example, in some embodiments, the sensing circuit 210 and the ADC circuit 212 can be part of the transmitter circuitry 200b. In some embodiments, the tracker circuit 206a, the conditioning circuit 206b, the shaping circuit 206d, the envelope generation circuit 206e and the filter circuit 206c comprises an envelope tracking (ET) system. In some embodiments, the ET system comprises an example implementation of a source circuit (e.g., the source circuit 106 in Fig. 1 ) of the PA circuit 204.

[0033] In some embodiments, the PA circuit 204 is configured to receive a PA input signal 217 and generate a PA output signal y 218 based thereon. In some embodiments, the PA circuit 204 is configured to amplify the PA input signal 217 and therefore, in such embodiments, the PA output signal y 218 is an amplified version of the PA input signal 217. In some embodiments, the PA output signal y 218 is provided to the RF front end (RFFE) circuitry and antenna 230 for wireless transmission. The PA circuit 204 may further receive a power supply signal 224 from the tracker circuit 206a of the ET system. The tracker circuitry 206a may include DC-DC converter circuitry that modulates the power supply signal 224 based on the modulated BB signal to be transmitted by the transmitter circuitry 200b in order to provide an instantaneous power supply voltage (e.g., the power supply signal 224) that follows the instantaneous envelope of the modulated BB signal x 214 (or the PA input signal 217) to be transmitted. In some embodiments, the tracker circuitry 206a may facilitate constant/preferred gain conditions (e.g., iso-gain) in the PA circuit 204 by modifying the compression point of the PA circuit 204 by modulating the power supply signal 224 provided to the PA circuit 204. As illustrated, in some embodiments, the tracker circuit 206a may modulate the power supply signal 224 according to a filtered input signal x1 based on the modulated BB signal x after being conditioned by the conditioning circuit 206b. Note that the different elements included in the transmitter circuit 200b may be realized by different physical components, or some of the elements may be integrated together. For example, the conditioning circuitry 206b that performs signal conditioning may be included in an RF integrated circuit (RFIC), or may be included in a BB IC in embodiments in which phase quadrature (IQ) processing and envelope generation are performed in BB. Also, the tracker circuit 206a and the PA circuit 204 may be separate front-end (FE) components.

[0034] In order to implement the envelope tracking in the PA system 200, the envelope generation circuit 206e may perform a coordinate rotation digital computer (CORDIC) algorithm on the modulated BB signal x 214 to generate an envelope (e.g., magnitude) of the modulated BB signal x 214 _. While CORDIC algorithm may be used to generate the envelope of the modulated BB signal x 214, this should not be construed as limiting. In various embodiments, different algorithms and circuitry may be used to generate the envelope of the modulated BB signal x 214. Shaping circuit 206d may clamp the envelope at the low end, e.g., clamp the envelope to a constant value when the input envelope goes below a pre-defined threshold level. The shaping circuit 206d may also add an offset to the envelope and/or apply a weighting factor to the envelope to scale the envelope. Clamping the envelope may help to prevent tracking to low values of the envelope, which may limit the required tracking bandwidth of the ET circuitry, and may avoid small envelope values. In general, the lower the amplitude of the envelope, the higher the instantaneous bandwidth of the ET circuitry may be. The shaping circuitry 206d may perform envelope waveform conditioning in a manner similar to that performed in the tracker circuit 206a of the ET circuitry. Signal conditioning of the envelope may be performed by the shaping circuit 206d in preparation for performing the predistortion by the predistortion circuit 202.

[0035] Filtering circuit 206c may perform filtering of the signal conditioned envelope received from the shaping circuit 206d and may output a filtered input signal x1. The filtering circuit 206c may limit the bandwidth of the envelope signal such that the bandwidth becomes smaller than the external tracking bandwidth of the ET circuitry. In some embodiments, reducing the bandwidth of the envelope signal enables to reduce the complexity of the ADC circuit 212. The dominant filtering may therefore be applied in the digital domain and be stable and reproducible. By applying the dominant filtering in the digital domain, the filtering may be less susceptible to manufacturing variations such as part-to-part variations of the tracker circuit 206a and circuit board layout. The filtering circuit 206c may introduce distortion into the signal output by the PA circuit 204, as the PA circuit 204 is modulated by a signal after passing the filtering circuit 206c. For example, the PA circuit 204 may be modulated by a high frequency portion of the RF envelope signal that falls into a stop band of a digital filter implemented by the filtering circuit 206c.

[0036] Therefore, in order to compensate for the distortion caused by the ET system, the predistortion circuit 202 may be configured to pre-distort the modulated BB signal x 214 and generate a predistorted input signal x’ 216 to be provided to the transmitter circuitry 200b so that after being distorted by the ET circuitry integrated with the transmitter circuitry 200b (e.g., the PA circuit 204 and tracker circuit 206a), the amplified RF signal y 218 (sometimes referred to as PA output signal y 218) sent to the RFFE circuitry and antenna 230 for transmission may be essentially equal to the gain k of the PA 204 times the modulated BB signal x 214. In other words, the predistortion circuit 202 may be configured to add distortions to the modulated BB signal x 214 that cancel out the distortions added by the ET circuitry integrated with the transmitter circuitry 200b to generate the predistortion signal x’ 216 to be provided to the transmitter circuitry 200b. In some embodiments, the modulated BB signal x 214 corresponds to the input signal x 1 14 in Fig. 1 above and maybe referred to as an input signal in various embodiments described herein.

[0037] In some embodiments, the predistortion circuit 202 operates on the modulated BB signal x 214 and predistort the BB signal x 214 to output the predistorted input signal x’ 216 to the transmitter circuitry 200b. In some embodiments, the predistortion circuit 202 is further configured to receive one or more PA measurement signals 222b comprising one or more measured parameter values, respectively associated with the PA circuit 204, in order to generate the predistorted input signal x’ 216. In the embodiments described herein, the measured parameter values associated with the PA circuit 204 refers to measurements associated with the PA input signal 217, the PA output signal y 218, the PA supply signal 224 and the PA circuit 204. In some embodiments, the measured parameter values associated with the one or more PA measurement signals 222b comprises one or more of a supply voltage measurement, a supply current measurement, a PA voltage standing wave ratio (VSWR) measurement, a temperature measurement and a PA bias associated with the PA circuit 204. However, in other embodiments, PA measurement signals comprising other measured parameter values associated with the PA circuit 204 than above are also contemplated to be within the scope of this disclosure. In some embodiments, utilizing the measured parameter values associated with the supply signal 224 in generating the predistorted input signal x’ 216 enables to compensate for the non-linearities introduced by the ET system in the PA circuit 204.

[0038] In order to generate the predistorted input signal x’ 216, in some

embodiments, a non-linearity model associated with the PA circuit 204 is to be extracted/determined. In some embodiments, extracting the non-linearity model associated with the PA circuit 204 comprises determining a plurality of DPD coefficients 220 based on the PA output signal y 218. In some embodiments, other parameters, for example, the PA input signal 217 or the predistorted input signal x’ 216 or the input signal x 214 may also be utilized, in addition to the PA output signal y 218, in order to determine the DPD coefficients 220. In some embodiments, the DPD coefficients 220 are determined based on a scaled/processed version (e.g., captured by means of a directional coupler or a voltage divider circuit) of the PA output signal y 218. In some embodiments, the PA system 200 comprises a DPD computation circuit 208 (outside of the predistortion circuit 202) configured to receive the PA output signal y 218 and determine the DPD coefficients 220 and provide the determined DPD coefficients 220 to the predistortion circuit 202. However, in other embodiments, the DPD computation circuit 208 may be part of the predistortion circuit 202 and therefore, in such

embodiments, the predistortion circuit 202 may be configured to receive the PA output signal y 218 and determine the DPD coefficients based thereon (not shown). Further, in some embodiments, the DPD coefficients 220 may be determined external to the PA system 200 and provided to the predistortion circuit 202. In some embodiments, the DPD coefficients 220 may be determined using known methods, for example, indirect learning. However, other methods of determining the DPD coefficients 220 are also contemplated to be within the scope of this disclosure. In some embodiments, it is assumed that the DPD coefficients 220 are not determined in real-time. In such embodiments, it is assumed that the DPD coefficients 220 are determined in a previous training/leaning phase of the predistortion circuit 202 and are available to the

predistortion circuit 202, prior to receiving the input signal x 214.

[0039] In some embodiments, the predistortion circuit 202 is configured to generate the predistorted input signal x’ 216 based on computing a predistortion function associated with the predistortion circuit 202 by utilizing the modulated BB signal x 214, the one or more PA measurement signals 222b and the one or more DPD coefficients 220, as explained above with respect to Fig. 1. However, in other embodiments, other methods of utilizing the modulated BB signal x 214 and the one or more PA measurement signals 222b in order to generate the predistorted input signal x’ 216 are also contemplated to be within the scope of this disclosure. In some embodiments, the predistortion circuit 202 may compute the predistortion function by performing memory polynomial operations on the modulated BB signal x 214 and the one or more PA measurement signals 222b to generate the predistorted PA output signal y 218, further details of which are discussed below with reference to FIG.4. However, in other embodiments, the predistortion function can be computed differently, for example, using the lookup table (LUT) approach, as explained above with respect to Fig. 1 above.

[0040] Fig. 3 illustrates an example implementation of a power amplifier (PA) system 300, according to another embodiment of the disclosure. In some embodiments, the PA system 300 depicts another possible way of implementation of the PA system 100 in Fig. 1 . The PA system 300 comprises a predistortion circuit 302 and a PA circuit 304.

In some embodiments, the PA circuit 304 is configured to receive a PA input signal 315 and generate a PA output signal y 316 based thereon. In some embodiments, the PA circuit 304 is configured to amplify the PA input signal 315 and therefore, in such embodiments, the PA output signal y 316 is an amplified version of the PA input signal 315. In some embodiments, the PA output signal y 316 is provided to an RF front end (RFFE) circuitry and antenna (not shown) for wireless transmission.

[0041] In some embodiments, the PA input signal 315 is an upconverted version of a predistorted input signal x’ 314 associated with the predistorter circuit 302. In some embodiments, the predistorted input signal x’ 314 from the predistortion circuit 302 is received at an RF signal generation circuit 303 and upconverted from BB domain to RF domain, in order to form the PA input signal 315. In some embodiments, the predistortion circuit 302 is configured to receive an input signal x 312 (e.g., a baseband signal) and predistort the input signal x 312, in order to generate the predistorted input signal x’ 314 to be provided to the PA circuit 304. In some embodiments, the predistortion circuit 302 may be configured to add distortions to the input signal x 312 that cancel out the distortions added by the PA circuit non-linearities, so as to get a desired PA output signal y 316 at the output of the PA circuit 304. In some embodiments, the predistortion circuit 302 is implemented as part of a baseband (BB) integrated circuit (IC) and the PA circuit 304 is implemented as part of a radio-frequency (RF) IC. In some embodiments, the PA circuit 302 and the RF signal generation circuit 303 may comprise a transmitter circuitry associated with the PA system 300.

[0042] In some embodiments, the PA system 300 further comprises a source circuitry 306a and 306b configured to provide a supply signal 322a and a ground signal 322b respectively, to the PA circuit 304. In other embodiments, the source circuitry can be implemented differently than above. In some embodiments, the source circuitry has parasitic components, for example, RV _D D, LV _D D, RVSS and LV _SS. During operation, in some embodiments, the PA supply including the supply signal VDD _PA 322a and the ground signal VSSPA 322b is modulated due to the voltage drop over these parasitic components. Further, in some embodiments, due to changes in the environmental conditions, parameters such as temperature, voltage standing wave ratio (VSWR) etc. associated with the PA circuit 304 changes. In some embodiments, the above effects lead to a variation in the non-linearity of the PA circuit 304. Therefore, in some embodiments, in order to compensate for the non-linearities caused by the above effects, the predistortion circuit 302 is further configured to receive one or more PA measurement signals 320 comprising one or more measured parameter values, respectively associated with the PA circuit 304, in order to generate the predistorted input signal x’ 314. In this embodiment, the predistortion circuit 302 is shown to receive a single PA measurement signal 320 comprising a supply voltage measurement associated with the PA circuit 304, in order to generate the predistorted input signal x’ 314.

[0043] However, in other embodiments, additional PA measurement signals comprising additional measured parameter values associated with the PA circuit 304, for example, temperature measurement, VSWR, supply current measurement etc. can be utilized by the predistortion circuit 302, in order to generate the predistorted input signal x’ 314. In some embodiments, utilizing the one or more PA measurement signals 320 comprising the one or more measured parameter values associated with the PA circuit 304 in generating the predistorted input signal x’ 314 enables to compensate for the non-linearities introduced by various factors (e.g., supply voltage variation, temperature variation etc.) in the PA circuit 304. The PA system 300 further comprises a sensing circuitry 324 configured to measure the supply voltage associated with the PA circuit 304 and generate the PA measurement signal 320 based thereon. In this embodiment, the sensing circuitry 324 is implemented as comprising resistors R1 , R2 and R3. However, in other embodiments, the sensing circuitry 324 can be implemented differently, for example, comprising other components like op-amps. Further, in some embodiments, the sensing circuitry 324 can be configured to measure other parameter values associated with the PA circuit 304, for example, supply current, temperature etc.

[0044] In this embodiment, the supply voltage measurement associated with the PA measurement signal 320 is measured at the sensing circuitry 324 as a difference between the supply voltage VDDPA and the ground voltage VSSPA, in accordance with the equation given below. where R1 , R2 and R3 are the resistances associated with the sensing circuit 324, VDDPA is the supply voltage associated with the supply signal 322a and VSSPA is the ground voltage associated with the ground signal 322b. However, in other embodiments, the supply voltage measurement can be done differently than above, depending on the implementation of the sensing circuit. In some embodiments, the PA system 300 further comprises an analog-to-digital converter (ADC) circuit 310 configured to convert the measurements associated with the sensing circuitry 324 into digital values.

[0045] In some embodiments, the predistortion circuit 302 is configured to generate the predistorted input signal x’ 314 based on computing a predistortion function associated with the predistortion circuit 302 by utilizing the modulated BB signal x 312 and the PA measurement signal 320, as explained above with respect to Fig. 1. However, in other embodiments, other methods of utilizing the modulated BB signal x 312 and the PA measurement signals 320 within the predistortion circuit 302, in order to generate the predistorted PA input signal x’ 314 are also contemplated to be within the scope of this disclosure. In some embodiments, the predistortion circuit 302 may compute the predistortion function by performing memory polynomial operations on the modulated BB signal x 312 and the PA measurement signals 320 to generate the predistorted input signal x’ 314, further details of which are discussed below with reference to FIG.4. However, in other embodiments, the predistortion function can be computed differently, for example, using the lookup table (LUT) approach, as explained above with respect to Fig. 1 above. In some embodiments, the predistortion circuit 302 further requires one or more digital predistortion (DPD) coefficients that depicts the PA non-linearity, in order to determine the predistortion function. In some embodiments, the PA system 300 comprises a DPD feedback circuit 308 configured to receive the PA output signal y 316, determine the DPD coefficients based thereon and provide the DPD coefficients to the predistortion circuit 302. However, in other embodiments, the DPD coefficients can be determined at the predistortion circuit 302 based on receiving the PA output signal y 316 at the predistortion circuit 302.

[0046] FIG. 4 is a block diagram illustrating a multi-feed predistorter circuitry 400, in accordance with some embodiments. In some embodiments, the multi-feed predistorter circuitry 400 may be included within the predistorter circuit 102 of FIG. 1 , the predistortion circuit 202 of Fig. 2 and the predistortion circuit 302 of Fig. 3. The multi feed predistorter circuitry 400 may implement the following memory polynomial equation (Eq. 2) for each pair of inputs (e.g., the modulated BB signal x 214, and the one or more PA measurement signals 222b in Fig. 2), and then sum the results of each polynomial equation together by the summer å before outputting a predistorted signal (e.g., the predistorted input signal x’ 216 to the transmitter circuitry 200b in Fig. 2). In some embodiments, the multi-feed predistorter circuitry 400 may include a plurality of memory polynomial circuits 402a, 402b....402f, to implement the various memory polynomial equations.

[0047] In one example implementation, if the inputs include a modulated BB signal X1 , and two PA measurement signals X2 and X3, the implemented memory polynomial equations may include P(Xi, X ₂ ), P(Xi, X ₃ ), P(X ₂ , X ₃ ), P(Xi, Xi), P(X ₂ , X ₂ ), and P(X ₃ , X ₃ ), each of which may be represented by: where x, and X _j represent inputs to each of the plurality of memory polynomial circuits 402a, 402b....402f, each of x, and X _j being one of the modulated baseband signal and measured parameter values associated with the PA measurement signals, K describes the maximum order of the memory polynomial, which may be different for each P(Xj, X _j ), M is the memory depth of the memory polynomial, n is a discrete time index, and h is the complex weighting of each polynomial. The polynomial coefficients h may be determined by a processor, e.g., according to a self-tuning control mechanism, for example, an indirect learning method for memory polynomial predistorters. In some embodiments, the polynomial coefficients h is same as the digital predistortion (DPD) coefficients explained above with respect to Fig. 1 . The polynomial equation Eq. 2 is an example polynomial equation, but should not be considered limiting. In various embodiments, other computational processing of Xi , X ₂ , and X ₃ may be used instead. In some embodiments, the multi-feed predistorter circuitry 400 may capture effects caused by limited bandwidth of the tracker circuit in ET systems as well as distortions caused by frequency-dependent loading of the PA circuit, ET delay dispersion, ET delay offset, and other nonlinearities and impairments of the PA circuit, for example, due to PA supply voltage variation.

[0048] Fig. 5 illustrates a flow diagram of a method 500 for applying digital predistortion (DPD) to a power amplifier (PA) circuit in a PA system, according to one embodiment of the disclosure. The method 500 is explained herein with respect to the PA system 100 in Fig. 1. However, in other embodiments, the method 500 can be applied to any PA system, for example, the PA system 200 in Fig. 2, the PA system 300 in Fig. 3 etc. In some embodiments, the method 500 described herein facilitates to compensate for the PA non-linearity. At 502, an input signal (e.g., the input signal x 1 14 in Fig. 1 ) associated with a PA system (e.g., the PA system 100 in Fig. 1 ) is received at a predistortion circuit (e.g., the predistortion circuit 102 in Fig. 1 ). At 504, one or more PA measurement signals (e.g., the PA measurement signals 122b in Fig. 1 ) comprising one or more measured parameter values respectively, associated with the PA circuit is received at the predistortion circuit.

[0049] In some embodiments, the measured parameter values associated with the one or more PA measurement signals comprises one or more of a supply voltage measurement, a supply current measurement, a PA voltage standing wave ratio (VSWR) measurement, a temperature measurement and a PA bias associated with the PA circuit. However, in other embodiments, PA measurement signals comprising other measured parameter values associated with the PA circuit than above are also contemplated to be within the scope of this disclosure. In some embodiments, the one or more measured parameter values associated with the one or more PA measurement signals comprises measured parameter values that are different from measured parameter values associated with a PA output signal (e.g., the PA output signal y 1 18 in Fig. 1 ). For example, in some embodiments, the one or more measured parameter values associated with the one or more PA measurement signals comprises measured parameter values associated with supply signal 124 (e.g., the supply voltage

measurement, supply current measurement etc.) or with the PA circuit itself (e.g., temperature measurement, VSWR etc.). In some embodiments, utilizing the measured parameter values in order to generate the predistorted input signal enables real-time adaptation of the digital predistortion of the PA circuit. [0050] At 506, the PA output signal associated with the PA circuit is received at the predistortion circuit. Upon receiving the PA output signal, in some embodiments, the predistortion circuit is configured to determine digital predistortion (DPD) coefficients that defines the PA non-linearity. However, in other embodiments, the PA circuit may receive the DPD coefficients from outside, for example, from a DPD computation circuit (e.g., the DPD computation circuit 108 in Fig. 1 ). In such embodiments, the PA circuit may not receive the PA output signal directly. At 508, a predistorted PA output signal (e.g., the predistorted input signal x’ 1 16 in Fig. 1 ) is generated at the predistortion circuit based on the PA input signal, the one or more PA measurement signals and the DPD coefficients. In some embodiments, the predistorted input signal is generated at the predistortion circuit based on computing a predistortion function associated with the predistortion circuit by utilizing the input signal, the one or more PA measurement signals and the DPD coefficients. However, in other embodiments, the predistorted input signal x’ 1 16 can be generated differently than above, based on utilizing the input signal and the one or more PA measurement signals. At 510, the generated

predistorted PA input signal is provided to a transmitter circuitry (e.g., the transmitter circuitry 100b in Fig. 1 ).

[0051] While the methods are illustrated, and described above as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the disclosure herein. Also, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

[0052] FIG. 6 illustrates example components of a device 600 in accordance with some embodiments. In some embodiments, the device 600 may include application circuitry 602, baseband circuitry 604, Radio Frequency (RF) circuitry 606, front-end module (FEM) circuitry 608, one or more antennas 610, and power management circuitry (PMC) 612 coupled together at least as shown. The components of the illustrated device 600 may be included in a UE or a RAN node. In some embodiments, the PA system 100, the PA system 200 and the PA system 300 could be implemented as a part of the device 600. In some embodiments, the device 600 may include less elements (e.g., a RAN node may not utilize application circuitry 602, and instead include a processor/controller to process IP data received from an EPC). In some

embodiments, the device 600 may include additional elements such as, for example, memory/storage, display, camera, sensor, or input/output (I/O) interface. In other embodiments, the components described below may be included in more than one device (e.g., said circuitries may be separately included in more than one device for Cloud-RAN (C-RAN) implementations).

[0053] The application circuitry 602 may include one or more application processors. For example, the application circuitry 602 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.). The processors may be coupled with or may include memory/storage and may be configured to execute instructions stored in the memory/storage to enable various applications or operating systems to run on the device 600. In some embodiments, processors of application circuitry 602 may process IP data packets received from an EPC.

[0054] The baseband circuitry 604 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The baseband circuitry 604 may include one or more baseband processors or control logic to process baseband signals received from a receive signal path of the RF circuitry 606 and to generate baseband signals for a transmit signal path of the RF circuitry 606. Baseband processing circuity 604 may interface with the application circuitry 602 for generation and processing of the baseband signals and for controlling operations of the RF circuitry 606. For example, in some embodiments, the baseband circuitry 604 may include a third generation (3G) baseband processor 604A, a fourth generation (4G) baseband processor 604B, a fifth generation (5G) baseband processor 604C, or other baseband processor(s) 604D for other existing generations, generations in development or to be developed in the future (e.g., second generation (2G), sixth generation (6G), etc.). The baseband circuitry 604 (e.g., one or more of baseband processors 604A-D) may handle various radio control functions that enable communication with one or more radio networks via the RF circuitry 606. In other embodiments, some or all of the functionality of baseband processors 604A-D may be included in modules stored in the memory 604G and executed via a Central Processing Unit (CPU) 604E. The radio control functions may include, but are not limited to, signal modulation/demodulation, encoding/decoding, radio frequency shifting, etc. In some embodiments, modulation/demodulation circuitry of the baseband circuitry 604 may include Fast-Fourier Transform (FFT), precoding, or constellation mapping/demapping functionality. In some embodiments,

encoding/decoding circuitry of the baseband circuitry 604 may include convolution, tail- biting convolution, turbo, Viterbi, or Low Density Parity Check (LDPC) encoder/decoder functionality. Embodiments of modulation/demodulation and encoder/decoder functionality are not limited to these examples and may include other suitable functionality in other embodiments.

[0055] In some embodiments, the baseband circuitry 604 may include one or more audio digital signal processor(s) (DSP) 604F. The audio DSP(s) 604F may be include elements for compression/decompression and echo cancellation and may include other suitable processing elements in other embodiments. Components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or disposed on a same circuit board in some embodiments. In some embodiments, some or all of the constituent components of the baseband circuitry 604 and the application circuitry 602 may be implemented together such as, for example, on a system on a chip (SOC).

[0056] In some embodiments, the baseband circuitry 604 may provide for communication compatible with one or more radio technologies. For example, in some embodiments, the baseband circuitry 604 may support communication with an evolved universal terrestrial radio access network (EUTRAN) or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), a wireless personal area network (WPAN). Embodiments in which the baseband circuitry 604 is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

[0057] RF circuitry 606 may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium. In various embodiments, the RF circuitry 606 may include switches, filters, amplifiers, etc. to facilitate the communication with the wireless network. RF circuitry 606 may include a receive signal path which may include circuitry to down-convert RF signals received from the FEM circuitry 608 and provide baseband signals to the baseband circuitry 604. RF circuitry 606 may also include a transmit signal path which may include circuitry to up-convert baseband signals provided by the baseband circuitry 604 and provide RF output signals to the FEM circuitry 608 for transmission.

[0058] In some embodiments, the receive signal path of the RF circuitry 606 may include mixer circuitry 606a, amplifier circuitry 606b and filter circuitry 606c. In some embodiments, the transmit signal path of the RF circuitry 606 may include filter circuitry 606c and mixer circuitry 606a. RF circuitry 606 may also include synthesizer circuitry 606d for synthesizing a frequency for use by the mixer circuitry 606a of the receive signal path and the transmit signal path. In some embodiments, the mixer circuitry 606a of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry 608 based on the synthesized frequency provided by synthesizer circuitry 606d. The amplifier circuitry 606b may be configured to amplify the down- converted signals and the filter circuitry 606c may be a low-pass filter (LPF) or band pass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals. Output baseband signals may be provided to the baseband circuitry 604 for further processing. In some embodiments, the output baseband signals may be zero-frequency baseband signals, although this is not a requirement. In some embodiments, mixer circuitry 606a of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect.

[0059] In some embodiments, the mixer circuitry 606a of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 606d to generate RF output signals for the FEM circuitry 608. The baseband signals may be provided by the baseband circuitry 604 and may be filtered by filter circuitry 606c. [0060] In some embodiments, the mixer circuitry 606a of the receive signal path and the mixer circuitry 606a of the transmit signal path may include two or more mixers and may be arranged for quadrature downconversion and upconversion, respectively. In some embodiments, the mixer circuitry 606a of the receive signal path and the mixer circuitry 606a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuitry 606a of the receive signal path and the mixer circuitry 606a may be arranged for direct downconversion and direct upconversion, respectively. In some embodiments, the mixer circuitry 606a of the receive signal path and the mixer circuitry 606a of the transmit signal path may be configured for super-heterodyne operation.

[0061] In some embodiments, the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternate embodiments, the output baseband signals and the input baseband signals may be digital baseband signals. In these alternate embodiments, the RF circuitry 606 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry and the baseband circuitry 604 may include a digital baseband interface to communicate with the RF circuitry 606.

[0062] In some dual-mode embodiments, a separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the

embodiments is not limited in this respect.

[0063] In some embodiments, the synthesizer circuitry 606d may be a fractional-N synthesizer or a fractional N/N+1 synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable. For example, synthesizer circuitry 606d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider.

[0064] The synthesizer circuitry 606d may be configured to synthesize an output frequency for use by the mixer circuitry 606a of the RF circuitry 606 based on a frequency input and a divider control input. In some embodiments, the synthesizer circuitry 606d may be a fractional N/N+1 synthesizer. [0065] In some embodiments, frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a requirement. Divider control input may be provided by either the baseband circuitry 604 or the applications processor 602 depending on the desired output frequency. In some embodiments, a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the applications processor 602.

[0066] Synthesizer circuitry 606d of the RF circuitry 606 may include a divider, a delay-locked loop (DLL), a multiplexer and a phase accumulator. In some

embodiments, the divider may be a dual modulus divider (DMD) and the phase accumulator may be a digital phase accumulator (DPA). In some embodiments, the DMD may be configured to divide the input signal by either N or N+1 (e.g., based on a carry out) to provide a fractional division ratio. In some example embodiments, the DLL may include a set of cascaded, tunable, delay elements, a phase detector, a charge pump and a D-type flip-flop. In these embodiments, the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

[0067] In some embodiments, synthesizer circuitry 606d may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other. In some embodiments, the output frequency may be a LO frequency (fLO). In some embodiments, the RF circuitry 606 may include an IQ/polar converter.

[0068] FEM circuitry 608 may include a receive signal path which may include circuitry configured to operate on RF signals received from one or more antennas 610, amplify the received signals and provide the amplified versions of the received signals to the RF circuitry 606 for further processing. FEM circuitry 608 may also include a transmit signal path which may include circuitry configured to amplify signals for transmission provided by the RF circuitry 606 for transmission by one or more of the one or more antennas 610. In various embodiments, the amplification through the transmit or receive signal paths may be done solely in the RF circuitry 606, solely in the FEM 608, or in both the RF circuitry 606 and the FEM 608.

[0069] In some embodiments, the FEM circuitry 608 may include a TX/RX switch to switch between transmit mode and receive mode operation. The FEM circuitry may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry may include an LNA to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 606). The transmit signal path of the FEM circuitry 608 may include a power amplifier (PA) to amplify input RF signals (e.g., provided by RF circuitry 606), and one or more filters to generate RF signals for subsequent transmission (e.g., by one or more of the one or more antennas 610).

[0070] In some embodiments, the PMC 612 may manage power provided to the baseband circuitry 604. In particular, the PMC 612 may control power-source selection, voltage scaling, battery charging, or DC-to-DC conversion. The PMC 612 may often be included when the device 600 is capable of being powered by a battery, for example, when the device is included in a UE. The PMC 612 may increase the power conversion efficiency while providing desirable implementation size and heat dissipation

characteristics.

[0071] While FIG. 6 shows the PMC 612 coupled only with the baseband circuitry 604. However, in other embodiments, the PMC 8 12 may be additionally or alternatively coupled with, and perform similar power management operations for, other components such as, but not limited to, application circuitry 602, RF circuitry 606, or FEM 608.

[0072] In some embodiments, the PMC 612 may control, or otherwise be part of, various power saving mechanisms of the device 600. For example, if the device 600 is in an RRC_Connected state, where it is still connected to the RAN node as it expects to receive traffic shortly, then it may enter a state known as Discontinuous Reception Mode (DRX) after a period of inactivity. During this state, the device 600 may power down for brief intervals of time and thus save power. [0073] If there is no data traffic activity for an extended period of time, then the device 600 may transition off to an RRCJdle state, where it disconnects from the network and does not perform operations such as channel quality feedback, handover, etc. The device 600 goes into a very low power state and it performs paging where again it periodically wakes up to listen to the network and then powers down again. The device 600 may not receive data in this state, in order to receive data, it must transition back to RRC_Connected state.

[0074] An additional power saving mode may allow a device to be unavailable to the network for periods longer than a paging interval (ranging from seconds to a few hours). During this time, the device is totally unreachable to the network and may power down completely. Any data sent during this time incurs a large delay and it is assumed the delay is acceptable.

[0075] Processors of the application circuitry 602 and processors of the baseband circuitry 604 may be used to execute elements of one or more instances of a protocol stack. For example, processors of the baseband circuitry 604, alone or in combination, may be used execute Layer 3, Layer 2, or Layer 1 functionality, while processors of the application circuitry 604 may utilize data (e.g., packet data) received from these layers and further execute Layer 4 functionality (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers). As referred to herein, Layer 3 may comprise a radio resource control (RRC) layer, described in further detail below. As referred to herein, Layer 2 may comprise a medium access control (MAC) layer, a radio link control (RLC) layer, and a packet data convergence protocol (PDCP) layer, described in further detail below. As referred to herein, Layer 1 may comprise a physical (PHY) layer of a UE/RAN node, described in further detail below.

[0076] While the apparatus has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described

components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention.

[0077] In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms

(including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure. In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.

[0078] Examples can include subject matter such as a method, means for performing acts or blocks of the method, at least one machine-readable medium including instructions that, when performed by a machine cause the machine to perform acts of the method or of an apparatus or system for concurrent communication using multiple communication technologies according to embodiments and examples described herein.

[0079] Example 1 is a multi-feed predistorter circuit associated with a power amplifier (PA) system, comprising one or more processors, configured to receive an input signal associated with the PA system; receive one or more PA measurement signals comprising one or more measured parameter values, respectively associated with a PA circuit in the PA system, wherein the one or more measured parameter values comprises measured parameter values that are different from measured parameter values associated with a PA output signal and a PA input signal of the PA circuit; generate a predistorted input signal, based on the input signal and the one or more PA measurement signals; and provide the predistorted input signal to a transmitter circuitry comprising the PA circuit, in order to compensate for non-linearities associated with the PA circuit.

[0080] Example 2 is a circuit, including the subject matter of example 1 , wherein the one or more measured parameter values comprises measured parameter values associated with a supply signal of the PA circuit or with the PA circuit itself, or both.

[0081] Example 3 is a circuit, including the subject matter of examples 1 -2, including or omitting elements, wherein the one or more measured parameter values comprises one or more of a supply voltage measurement, a supply current measurement, a PA voltage standing wave ratio (VSWR) measurement, a temperature measurement and a PA bias associated with the PA circuit.

[0082] Example 4 is a circuit, including the subject matter of examples 1 -3, including or omitting elements, wherein the one or more processors is configured to generate the predistorted input signal based on computing a predistortion function associated with the multi-feed predistorter circuit, in accordance with the one or more PA measurement signals.

[0083] Example 5 is a circuit, including the subject matter of examples 1 -4, including or omitting elements, further comprising a memory circuit configured to store one or more digital predistortion (DPD) coefficients associated with the predistortion function of the PA circuit.

[0084] Example 6 is a circuit, including the subject matter of examples 1 -5, including or omitting elements, wherein the one or more processors is further configured to receive the PA output signal and determine the one or more DPD coefficients, at least in part, based on the PA output signal, prior to storing the one or more DPD coefficients in the memory circuit, wherein the one or more DPD coefficients are utilized to generate the predistorted input signal.

[0085] Example 7 is a circuit, including the subject matter of examples 1 -6, including or omitting elements, wherein the one or more processors is configured to compute the predistortion function of the multi-feed predistorter circuit by utilizing one or more lookup tables (LUTs) comprising predefined relations between the measured parameter values associated with the one or more PA measurement signals and one or more predistortion functions associated with the multi-feed predistorter circuit.

[0086] Example 8 is a circuit, including the subject matter of examples 1 -7, including or omitting elements, wherein the one or more processors is configured to compute the predistortion function of the multi-feed predistorter circuit by computing one or more memory polynomial equations operating on pairs of the measured parameter values associated with the one or more PA measurement signals; and summing results of computing the one or more memory polynomial equations.

[0087] Example 9 is a circuit, including the subject matter of examples 1 -8, including or omitting elements, wherein each of the one or more memory polynomial equations implement the following polynomial equation:

Where x, and X _j represent inputs to the multi-feed predistorter circuit, each of x, and X _j being measured parameter values associated with the one or more PA measurement signals; Kxi,X _j describes a maximum order of the polynomial equation; M x,,X _j is a memory depth of the polynomial equation; n is a discrete time index; and h Xi,X _{j,ki ,k2} is a complex weighting of each polynomial of the polynomial equation.

[0088] Example 10 is an apparatus for applying predistortion to a power amplifier (PA) circuit associated with a PA system comprises a predistortion circuit configured to receive an input signal associated with the PA system; receive one or more PA measurement signals comprising one or more measured parameter values, respectively associated with the PA circuit, wherein the one or more measured parameter values comprises measured parameter values that are different from measured parameter values associated with a PA output signal and a PA input signal of the PA circuit;

generate a predistorted input signal, based on the input signal and the one or more PA measurement signals; and provide the predistorted input signal to a transmitter circuitry comprising the PA circuit, in order to compensate for non-linearities associated with the PA circuit.

[0089] Example 1 1 is an apparatus, including the subject matter of example 10, wherein the one or more measured parameter values comprises measured parameter values associated with a supply signal associated with the PA circuit or with the PA circuit itself, or both.

[0090] Example 12 is an apparatus, including the subject matter of examples 10-1 1 , including or omitting elements, wherein the one or more measured parameter values comprises one or more of a supply voltage measurement, a supply current

measurement, a PA voltage standing wave ratio (VSWR) measurement, a temperature measurement and a PA bias associated with the PA circuit.

[0091] Example 13 is an apparatus, including the subject matter of examples 10-12, including or omitting elements, further comprising a sensing circuit configured to determine the one or more measured parameter values associated with the PA circuit; generate the one or more PA measurement signals respectively comprising the one or more measured parameter values; and provide the one or more PA measurement signals to the predistortion circuit.

[0092] Example 14 is an apparatus, including the subject matter of examples 10-13, including or omitting elements, wherein the predistortion circuit is configured to generate the predistorted input signal based on computing a predistortion function associated with the predistortion circuit, in accordance with the one or more PA measurement signals.

[0093] Example 15 is an apparatus, including the subject matter of examples 10-14, including or omitting elements, wherein the predistortion circuit is further configured to receive the PA output signal and determine the one or more digital predistortion (DPD) coefficients associated with the predistortion function of the predistorter circuit, at least in part, based on the PA output signal.

[0094] Example 16 is an apparatus, including the subject matter of examples 10-15, including or omitting elements, further comprising an analog-to-digital converter (ADC) circuit coupled to the sensing circuit, and configured to receive the PA measurement signals from the sensing circuit; and convert the PA measurement signals to digital values, prior to providing the PA measurement signals to the predistorter circuit.

[0095] Example 17 is an apparatus, including the subject matter of examples 10-16, including or omitting elements, wherein the sensing circuit is configured to receive the supply voltage or the supply current or both, from a source circuit associated with the PA circuit.

[0096] Example 18 is an apparatus, including the subject matter of examples 10-17, including or omitting elements, wherein the source circuit comprises a tracker circuit configured to receive the input signal and generate the supply voltage based thereon, wherein the supply voltage is modulated in accordance with an envelope of the input signal.

[0097] Example 19 is an apparatus, including the subject matter of examples 10-18, including or omitting elements, further comprising a filter circuit configured to limit a bandwidth of the amplitude of the input signal to be less than the tracker circuit bandwidth, prior to providing the input signal to the tracker circuit.

[0098] Example 20 is an apparatus, including the subject matter of examples 10-19, including or omitting elements, wherein the predistortion circuit is configured to compute the predistortion function of the predistortion circuit based on utilizing one or more lookup tables (LUTs) comprising predefined relations between measured parameter values associated with the one or more PA measurement signals and one or more predistortion functions associated with the predistortion circuit.

[0099] Example 21 is an apparatus, including the subject matter of examples 10-20, including or omitting elements, wherein the predistortion circuit is configured to compute the predistortion function of the predistortion circuit by computing one or more memory polynomial equations operating on pairs of the measured parameter values associated with the one or more PA measurement signals; and summing results of computing the one or more memory polynomial equations. [00100] Example 22 is an apparatus, including the subject matter of examples 10-21 , including or omitting elements, wherein each of the one or more memory polynomial equations implement the following polynomial equation: where x, and X _j represent inputs to the multi-feed predistorter circuit, each of x, and X _j being measured parameter values associated with the one or more PA measurement signals; Kxi,X _j describes a maximum order of the polynomial equation; M x,,X _j is a memory depth of the polynomial equation; n is a discrete time index; and h Xi,X _{j,ki ,k2} is a complex weighting of each polynomial of the polynomial equation.

[00101] Example 23 is a method for applying predistortion to a power amplifier (PA) circuit associated with a PA system, the method comprising receiving, at a predistortion circuit, an input signal associated with the PA system; receiving, at the predistortion circuit, one or more PA measurement signals comprising one or more measured parameter values, respectively associated with a PA circuit of the PA system, wherein the one or more measured parameter values comprises measured parameter values that are different from measured parameter values associated with a PA output signal and a PA input signal of the PA circuit; generating, at the predistortion circuit, a predistorted input signal, based on the input signal and the one or more PA

measurement signals; and providing, from the predistortion circuit, the predistorted input signal to a transmitter circuitry comprising the PA circuit, in order to compensate for non-linearities associated with the PA circuit.

[00102] Example 24 is a method, including the subject matter of example 23, wherein the one or more measured parameter values comprises measured parameter values associated with a supply signal associated with the PA circuit or with the PA circuit itself, or both.

[00103] Example 25 is a method, including the subject matter of examples 23-24, including or omitting elements, wherein the one or more measured parameter values comprises one or more of a supply voltage measurement, a supply current

measurement, a PA voltage standing wave ratio (VSWR) measurement, a temperature measurement and a PA bias associated with the PA circuit.

[00104] Example 26 is a method, including the subject matter of examples 23-25, including or omitting elements, wherein generating the predistorted input signal at the predistortion circuit comprises computing a predistortion function associated with the multi-feed predistorter circuit, in accordance with the one or more PA measurement signals.

[00105] Example 27 is a method, including the subject matter of examples 23-26, including or omitting elements, further comprising receiving the PA output signal at the predistortion circuit and determining one or more DPD coefficients associated with the predistortion function, at least in part, based on the PA output signal.

[00106] Example 28 is a method, including the subject matter of examples 23-27, including or omitting elements, wherein computing the predistortion function associated with the multi-feed predistorter circuit, at the predistortion circuit, comprises utilizing one or more lookup tables (LUTs) comprising predefined relations between the measured parameter values associated with the one or more PA measurement signals and one or more predistortion functions associated with the multi-feed predistorter circuit.

[00107] Example 29 is a method, including the subject matter of examples 23-28, including or omitting elements, wherein computing the predistortion function associated with the multi-feed predistorter circuit, at the predistortion circuit, comprises computing one or more memory polynomial equations operating on pairs of the measured parameter values associated with the one or more PA measurement signals; and summing results of computing the one or more memory polynomial equation.

[00108] Example 30 is a method, including the subject matter of examples 23-29, including or omitting elements, wherein each of the one or more memory polynomial equations implement the following polynomial equation:

where x, and X _j represent inputs to the multi-feed predistorter circuit, each of x, and X _j being measured parameter values associated with the one or more PA measurement signals; Kxi,X _j describes a maximum order of the polynomial equation; M x,,X _j is a memory depth of the polynomial equation; n is a discrete time index; and h Xi,X _{j,ki ,k2} is a complex weighting of each polynomial of the polynomial equation.

[00109] Various illustrative logics, logical blocks, modules, and circuits described in connection with aspects disclosed herein can be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other

programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform functions described herein. A general-purpose processor can be a microprocessor, but, in the alternative, processor can be any conventional processor, controller, microcontroller, or state machine.

[00110] The above description of illustrated embodiments of the subject disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various modifications are possible that are considered within the scope of such embodiments and examples, as those skilled in the relevant art can recognize.

[00111] In this regard, while the disclosed subject matter has been described in connection with various embodiments and corresponding Figures, where applicable, it is to be understood that other similar embodiments can be used or modifications and additions can be made to the described embodiments for performing the same, similar, alternative, or substitute function of the disclosed subject matter without deviating therefrom. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims below.

[00112] In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms

(including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure. In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.