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Title:
A NOVEL NVRAM MEMORY CELL ARCHITECTURE THAT INTEGRATES CONVENTIONAL SRAM AND FLASH CELLS
Document Type and Number:
WIPO Patent Application WO2006019653
Kind Code:
A3
Abstract:
A nonvolatile SRAM array has an array of integrated nonvolatile SRAM circuits arranged in rows and columns on a substrate. Each of the integrated nonvolatile SRAM circuits includes an SRAM cell, a first and second nonvolatile memory element. The SRAM cell has a latched memory element in communication first and second nonvolatile memory elements to receive and permanently retain the digital signal from the latched memory element. A power detection circuit detects a power interruption and a power initiation and communicates the detection of the power interruption and power initiation to the plurality of integrated nonvolatile SRAM circuits. The SRAM cell, upon detection of the power interruption, transmits the digital signal to the first and second nonvolatile memory elements. The SRAM cell of each of the nonvolatile static random access memories upon detection of the power initiation receives the digital signal from the first and second nonvolatile memory elements.

Inventors:
LEE PETER W (US)
Application Number:
US2005024417W
Publication Date:
November 09, 2006
Filing Date:
July 11, 2005
Export Citation:
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Assignee:
APLUS FLASH TECHNOLOGY INC (US)
LEE PETER W (US)
International Classes:
G11C16/04; G11C11/34
Foreign References:
US20030179630A12003-09-25
US6414873B12002-07-02
US5914895A1999-06-22
US6781916B22004-08-24
Other References:
See also references of EP 1779390A4
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