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Patent Searching and Data


Title:
NOVEL SLEW RATE ENHANCEMENT CIRCUIT AND LOW DROPOUT REGULATOR
Document Type and Number:
WIPO Patent Application WO/2019/237220
Kind Code:
A1
Abstract:
The present invention is applicable to circuit design, and provides a novel slew rate enhancement circuit, comprising multiple MOS transistors and multiple capacitors. The multiple capacitors are used for detecting a change in a feedback voltage input from the outside, and sending a control signal to the multiple MOS transistors when detecting that the feedback voltage changes; the multiple MOS transistors are used for controlling, according to the control signal, the rise or drop of a voltage output from an output terminal of the novel slew rate enhancement circuit, so that limitation of a slew rate of a power regulation transistor connected to the output terminal of the novel slew rate enhancement circuit is improved. The novel slew rate enhancement circuit provided by embodiments of the present invention can improve the limitation of a slew rate of a power regulating transistor at the moment of load jumping change, so that the integral instant response is improved and a quiescent current is reduced. When a load current generates a transient change or generates a switching glitch and peak, a change in an output voltage can be quickly detected by means of a feedback voltage, and charging and discharging can be performed on the grid capacitance and Miller equivalent capacitance of the power regulating transistor quickly, and finally the transient characteristic of the circuit is greatly improved.

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Inventors:
JIANG MEI (CN)
SUN KAI (CN)
ZHANG HANYUAN (CN)
YANG ZHAOCHENG (CN)
Application Number:
PCT/CN2018/090563
Publication Date:
December 19, 2019
Filing Date:
June 11, 2018
Export Citation:
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Assignee:
UNIV SHENZHEN (CN)
International Classes:
G05F1/56
Foreign References:
CN103760943A2014-04-30
CN103744462B2015-11-18
CN105045329A2015-11-11
KR20120073832A2012-07-05
Attorney, Agent or Firm:
HENSEN INTELLECTUAL PROPERTY FIRM (CN)
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