OPTIMIZED COMPRESSIVE SiGe CHANNEL PMOS TRANSISTOR WITH ENGINEERED Ge PROFILE AND OPTIMIZED SILICON CAP LAYER

Title:

OPTIMIZED COMPRESSIVE SiGe CHANNEL PMOS TRANSISTOR WITH ENGINEERED Ge PROFILE AND OPTIMIZED SILICON CAP LAYER

Document Type and Number:

WIPO Patent Application WO/2010/056433

Kind Code:

A3

Abstract:

A semiconductor process and apparatus includes forming PMOS transistors (72) with enhanced hole mobility in the channel region by epitaxially growing a bi-axially stressed forward graded silicon germanium channel region layer (22) and a counter-doped silicon cap layer (23) prior to forming a PMOS gate structure (34) and associated source/drain regions (38, 40) in the channel region layer(s).

Inventors:

TEKLEAB DANIEL G (US)
SAMAVEDAM SRIKANTH B (US)

Application Number:

PCT/US2009/059494

Publication Date:

July 15, 2010

Filing Date:

October 05, 2009

Export Citation:

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Assignee:

FREESCALE SEMICONDUCTOR INC (US)
TEKLEAB DANIEL G (US)
SAMAVEDAM SRIKANTH B (US)

International Classes:

H01L21/336; H01L29/78

Foreign References:

US20070215859A1	2007-09-20
US20060186436A1	2006-08-24
US20010045604A1	2001-11-29
US20050051851A1	2005-03-10

Attorney, Agent or Firm:

KING, Robert, L. et al. (MD: TX32/PL02Austin, TX, US)

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