The present invention relates to an orthogonal frequency-division multiplexing (OFDM) receiver circuit. Background

Wireless communication technologies continue to evolve to meet the demand for increased data throughput. This is addressed on many levels with different approaches including higher order modulation, MIMO, scheduling, increased bandwidth, and so on. In particular, higher frequencies than commonly used today, and mmW frequencies in particular, have attracted a lot of interest as there are larger blocks of continuous spectra available, spanning up to several GHz. A mmW-based air interface is considered to be one important component of a forthcoming 5G standard.

One problem related to these large bandwidths is the implementation of analog-to-digital converters (ADC). To accommodate such large bandwidths while being reasonably power efficient so called time-interleaved (TI) ADCs are sometimes used. A basic TI-ADC comprises M sub- ADCs, each operating at the same clock frequency f _s but at different phases of that same clock so as to effectively yield a conversion rate of M x f _s when the outputs of the sub- ADCs are recombined. The sub- ADCs are typically implemented as SAR (Successive Approximation Register) or pipeline ADCs or hybrids of those schemes. The individual sub- ADCs cannot normally be designed to operate accurately and/or power efficient at the conversion rate of M x f _s , but the time interleaving enables operation for the TI-ADC as a whole at this aggregated conversion rate M x f _s .

Mismatches that appear between sub- ADCs (timing, phase, gain, DC offset, transfer function) may lead to poor spurious-free dynamic range (SFDR), that may need to be corrected.

Some algorithms/techniques for estimation and interpolation of time errors with dedicated test signals (ramps and sine waves) have been presented, for instance:

Jenq, Y.-C, "Digital spectra of nonuniformly sampled signals: a robust sampling time offset estimation algorithm for ultra high-speed waveform digitizers using interleaving," Instrumentation and Measurement, IEEE Transactions on , vol.39, no. l , pp.71 ,75, Feb 1990. Huawen Jin; Lee, E.K.F., "A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol.47, no.7, pp.603,613, Jul 2000.

Some background calibration methods requiring no dedicated test input signal have also been proposed, for instance:

Jamal, S.M.; Fu, D.; Chang, N.C.-J.; Hurst, P.J.; Lewis, S.H., "A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration," Solid-State Circuits, IEEE Journal of , vol.37, no.12, pp.1618, 1627, Dec 2002.

Elbornsson, J.; Gustafsson, F.; Eklund, J.-E., "Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.51, no.1, pp.151, 158, Jan. 2004.

US 2008/0158029 Al discloses a technique for reducing errors in a TI-ADC (or, with the terminology used in that document, a PTIC (parallel, time-interleaved analog-to-digital converter)) consisting of M ADCs involves sampling an input signal with the TI-ADC and performing M different DFTs, one for each ADC. Elements of the M DFTs are grouped together according to bin number. If all elements corresponding to the same bin number exceed a predetermined threshold, the elements are multiplied by correction matrices to yield corrected DFT terms for a reconstructed power spectrum. If they do not exceed the threshold, DFT elements are processed to produce uncorrected DFT terms for the reconstructed power spectrum. The reconstructed power spectrum is then transformed back to the time domain as a digital time-domain output signal.

Summary

Many communication systems, such as those based on orthogonal frequency-division multiplexing (OFDM) and similar systems, are frequency-domain based. For such systems, a digital baseband signal representation in the frequency domain may be used. The inventors have realized that, for instance for such systems just mentioned, ADCs (referred to below as "conversion circuits") can be beneficially implemented as TI-ADCs with integrated frequency transformation, resulting in a frequency domain-output signal.

According to a first aspect, there is provided an OFDM receiver circuit. The receiver circuit comprises a receiver front-end circuit configured to frequency downconvert and filter a received signal comprising received data and output an analog signal in the time domain. The receiver circuit comprises a conversion circuit configured to generate a digital output signal in the frequency-domain based on said analog signal in the time domain. The conversion circuit comprises a plurality of signal processing sub branches. Each signal processing sub branch comprises a sub analog-to-digital converter (ADC) arranged to convert the analog signal to a digital output signal of the sub ADC (ADC m), wherein said digital output signal of the sub ADC (ADC m) is in the discrete time domain. Furthermore, each signal processing sub branch comprises a sub transform unit arranged to convert the digital output signal of the sub ADC to a digital output signal of the sub transform unit, wherein said digital output signal of the sub transform unit is in the discrete frequency domain. The signal processing sub branches are arranged to operate in a time-interleaved manner such that, in operation, when each signal processing sub branch operates at a first sample rate, the overall sample rate of the conversion circuit is higher than said first sample rate. The conversion circuit comprises a combiner unit arranged to combine the digital output signals from the sub transform units in the signal processing sub branches to form the digital output signal of the conversion circuit. Moreover, the receiver circuit comprises circuitry configured to process the digital output signal of the conversion circuit to recover the received data.

According to some embodiments, each sub transform unit comprises a sub discrete Fourier transform (DFT) arranged to apply a DFT operation on the digital output signal of the sub ADC in the same signal processing sub branch to generate a signal, in the following labeled DFT signal, of the sub transform unit. The DFT signal of each sub transform unit may be the digital output signal of that sub transform unit. The combiner unit may be adapted to upsample the digital output signal of each sub transform unit by generating a series of phase- rotated spectral replicas thereof, prior to combining them. Alternatively, each sub transform unit may comprise an upsampler unit adapted to generate the digital output signal of the sub transform unit as a series of phase-rotated spectral replicas of the DFT signal of the sub transform unit to match the overall sample rate of the conversion circuit in each of the signal processing sub branches.

The analog signal may be a complex signal having an in-phase (I) component and a quadrature-phase (Q) component.

In some embodiments, the sub ADC in each signal processing sub branch is a complex sub ADC, comprising a first real ADC arranged to convert the I component of the analog input signal of the conversion circuit to a first real digital output signal of the sub ADC, and a second real ADC arranged to convert the Q component of the analog input signal of the conversion circuit to a second real digital output signal of the sub ADC. Said first and second real digital output signals of the sub ADC together forms the digital output signal of the sub ADC as a complex digital output signal. In some such embodiments, the sub transform unit in each signal processing sub branch comprises a first real sub transform unit arranged to operate on the first real digital output signal of the sub ADC to generate a first complex digital output signal component of the sub transform unit and a second real sub transform unit arranged to operate on the second real digital output signal of the sub ADC to generate a second complex digital output signal component of the sub transform unit, wherein said first and second complex output signal components together forms the digital output signal of the sub transform unit. In other such embodiments, the sub transform unit in each signal processing sub branch is a complex sub transform unit arranged to operate on the complex digital output signal of the sub ADC to generate the digital output signal of the sub transform unit as a complex digital output signal.

The combiner unit may be adapted to detect a mismatch between signal processing sub branches and compensate for the mismatch in the discrete frequency domain. The combiner unit may be adapted to detect and compensate for the mismatch in a limited portion of an overall frequency band of the conversion circuit. The limited portion may correspond to subcarriers of a received OFDM symbol that are allocated to the receiver circuit.

In some embodiments, each subcarrier of a received OFDM symbol is represented with a sample of the output signal of the conversion circuit.

According to a second aspect, there is provided a communication apparatus comprising the receiver circuit according to the first aspect. In some embodiments, the communication apparatus is a base station for a wireless communication network. In some embodiments, the communication apparatus is a wireless terminal for a wireless communication network.

Further embodiments are defined in the dependent claims. It should be emphasized that the term "comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof.

Brief description of the drawings

Further objects, features and advantages of embodiments of the invention will appear from the following detailed description, reference being made to the accompanying drawings, in which:

Fig. 1 illustrates a communication system.

Fig. 2 is a block diagram of a communication apparatus.

Fig. 3 is a block diagram of a conversion circuit.

Figs. 4-5 show block diagrams of sub branches of a conversion circuit. Figs. 6-7 show block diagrams of sub branches of a conversion circuit.

Figs. 8 shows a flow chart for gain mismatch estimation.

Detailed description

Fig. 1 illustrates a communication environment where embodiments of the present 5 invention may be employed. A wireless terminal 1, in Fig. 1 illustrated as a mobile phone, is in wireless communication with a base station 2 in a wireless communication network. The wireless communication network may e.g. be a cellular communication network. However, embodiments of the present invention are also applicable in other types of wireless communication networks, such as a wireless local area network (WLAN) or a peer-to-peer 10 network.

Other alternatives are possible for the wireless terminal 1 than a mobile phone, for example a machine-type communication (MTC) terminal, a personal computer, such as a laptop, a tablet computer, or any type of terminal device capable of wireless communication. In the context of cellular networks, the wireless terminal 1 is often referred to as a user equipment

15 (UE). The base station 2 may be any type of base station, such as an eNodeB, a macro base station, a pico base station, or a femto base station of a cellular communication network, or an access point (AP) or the like in a WLAN.

The wireless terminal 1 and the base station 2 are examples of apparatuses which are generically referred to herein as communication apparatuses. Embodiments of the present

20 invention may also be employed in wireline communication apparatuses, such as a cable modem or the like.

Fig. 2 is a simplified block diagram of the wireless terminal 1 according to some embodiments. Embodiments of the base station 2, or any other communication apparatus, may be depicted in the same way. In Fig. 2, the wireless terminal 1 comprises a transmitter circuit

25 10 connected to an antenna 15. It also comprises a receiver circuit 20 connected to the antenna 15. Although a single antenna 15 is shown in Fig. 2, multiple antennas can be used in some embodiments. For instance, the receiver circuit 20 and the transmitter circuit 10 may be connected to different antennas.

The receiver circuit 20 comprises a receiver front-end circuit 30 configured to frequency

30 downconvert and filter a received signal comprising received data and output an analog signal (in the following denoted s(t)) in the time domain. The receiver frontend 30 may comprise filters, mixers, amplifiers etc. to perform this function. The implementation of such receiver frontends are well known in the art and not described in any further detail herein. Furthermore, the receiver circuit 20 comprises a conversion circuit 40 configured to generate a digital output signal, in the following referred to as Y[q] or Z[q], in the discrete frequency-domain based on the said analog signal s(t) . The notation Z[q] is used in the description of embodiments where compensation of mismatch between signal processing sub branches of the conversion circuit 40, whereas the notation Y[q] is used in the description of embodiments without such mismatch compensation.

Moreover, the receiver circuit 20 comprises circuitry 50, such as a digital signal processing (DSP) circuit 50, configured to process the digital output signal of the conversion circuit 40 to recover the received data.

The inventors have realized that this type of receiver circuit 20 is particularly useful for orthogonal frequency-division multiplexing (OFDM) applications, where the data recovery is done in the frequency domain. With the conversion into the frequency domain integrated with the analog-to-digital conversion in the conversion circuit 40, no additional fast Fourier transform (FFT) circuit, or other discrete Fourier transform (DFT) circuit, which is normally used in OFDM receivers, is required. This is facilitated if the conversion into the frequency domain integrated with the analog-to-digital conversion is synchronized with the OFDM symbols being received in time, such that samples are captured over one DFT frame corresponding to the length of the OFDM symbol. In doing so each sub-carrier of the OFDM symbol may be represented as a separate sample from the output of conversion unit 40 and thus no further demodulation is required. Furthermore with frequency domain representation synchronous with OFDM symbols being received enables on a per sub-carrier basis compensation of errors introduced by the conversion circuit 40.

Fig. 3 is a block diagram of the conversion circuit 40 according to some embodiments. The conversion circuit 40 comprises a plurality of signal processing sub branches b_m, with the integer index m ranging from 1 to some integer M. The word "sub" is used herein in connection with different units to indicate that there are several such units in the circuit that are arranged to operate on different signals. Each signal processing sub branch b_m comprises a sub analog-to-digital converter (ADC) ADC m arranged to convert the analog signal s(t) to a digital output signal of the sub ADC ADC m. The digital output signal of ADC m is in the discrete time domain. ADC m may be any suitable type of ADC. High-performance (high dynamic range and large bandwidth) ADCs typically employ a combination of techniques including pipeline and successive-approximation register (SAR). The design of such ADCs are well known in the art and not described herein in any further detail. Each signal processing sub branch b_m comprises a sub transform unit TRANS m arranged to convert the digital output signal of ADC m to a digital output signal of the sub transform unit TRANS m. The digital output signal of the sub transform unit TRANS m is in the discrete frequency domain. Various embodiments of the sub transform unit TRANS m are described below with reference to Figs. 4 and 5.

The signal processing sub branches b_m are arranged to operate in a time-interleaved manner such that, in operation, when each signal processing sub branch b_m operates at a first sample rate, the overall sample rate of the conversion circuit is higher than said first sample rate. For instance, if the first sample rate is denoted f _s and there are M signal processing sub branches, the overall sample rate would be M ^■ f _s . This is similar to a time-interleaved ADC. In Fig. 3, this is schematically illustrated with a circulating switch delivering the signal s (t) to the different signal processing sub branches b_m in consecutive order. In a practical implementation, the signal processing sub branches b_m would typically all be connected to receive the signal s(t), and the sampling clock signals to the sub ADCs ADC m would typically be skewed in time in order to obtain the time interleaving, as in a regular time- interleaved ADC.

The conversion circuit 40 further comprises a combiner unit 100. The combiner unit 100 is arranged to combine the digital output signals from the sub transform units TRANS m in the signal processing sub branches b_m to form the digital output signal Y[q] or Z[q] of the conversion circuit 40.

Notably, the combination of the signals from the different signal processing sub branches b_m is done in the frequency domain. This is in contrast with conventional time-interleaved ADCs, wherein the combination of output signals from sub ADCs is normally done in the time domain. One benefit of this, as hinted above, is that no additional FFT circuit is required in OFDM applications, or similar applications where a frequency-domain representation of the signal is needed. Furthermore, compensation of mismatch between the signal processing sub branches becomes comparably simpler when the combination is done in the frequency domain rather than in the time domain. This is further elaborated on in this text.

Some embodiments of the signal processing sub branches b_m are illustrated in Figs. 4 and 5. In some embodiments, the sub transform units TRANS m are arranged to transform the time-domain output signal from the sub ADCs ADC m using a discrete Fourier transform (DFT). In such embodiments, each sub transform unit TRANS m comprises a sub DFT unit, labeled DFT m in the figures, arranged to apply a DFT operation on the digital output signal of the sub ADC ADC m in the same signal processing sub branch b_m to generate a signal, in the following labeled "DFT signal", of the sub transform unit TRANS m.

Because the individual signal processing sub branches b_m operate at a sampling rate that is lower than the overall sampling rate of the conversion circuit 40, the individual DFT signal output from the sub DFT units DFT_m have fewer samples than the digital output signal Y[q] or Z[q] of the conversion circuit 40 per DFT frame. According to embodiments of the present invention, the DFT signals are therefore subject to an upsampling operation before they are combined to form the digital output signal Y[q] or Z[q]of the conversion circuit 40. This upsampling operation may e.g. either be performed within the signal processing sub branches b_m, or within the combiner unit 40. According to embodiments of the present invention, this upsampling operation comprises generating a series of phase rotated spectral replicas of the DFT signal of each sub transform unit TRANS m.

According to some embodiments, the DFT signal of each sub transform unit TRANS m is the digital output signal of that sub transform unit. This is illustrated in Fig. 4. In these embodiments, the combiner unit 100 may be adapted to upsample the digital output signal of each sub transform unit TRANS m by generating a series of phase-rotated spectral replicas thereof, prior to combining them.

According to other embodiments, each sub transform unit TRANS m comprises an upsampler unit UP m adapted to generate the digital output signal of the sub transform unit as a series of phase-rotated spectral replicas of the DFT signal of the sub transform unit

TRANS m, to match the overall sample rate of the conversion circuit 40 in each of the signal processing sub branches b_m. This is illustrated in Fig. 5.

The above-mentioned upsampling operation is described in the following. It is discussed in the context of the embodiment illustrated in Fig. 5, which includes an upsampler unit UP m in the sub transform unit TRANS m. However, it should be noted, as discussed above, that the function of the upsampler unit UP m, namely to provide the upsampling operation, could equally well be performed by some other circuit, such as the combiner unit 100. Each signal processing sub branch b_m run at a sampling rate f _s , with an equivalent clock period of T _s = l//s- With M signal processing sub branches, the overall effective sampling rate of M ^■ f _s , with an equivalent effective clock period of T _s /M, is obtained for the conversion circuit 40. Each sub DFT unit takes L samples (in the time domain) to generate a frame of the corresponding DFT signal of the same length, namely L samples, or points, (but in the frequency domain). We refer to this as an Z-point DFT. During the same time interval as these L time-domain samples are obtained in each signal processing sub branch b_m, M ^■ L samples are obtained in the overall conversion circuit 40, i.e. in all of the signal processing sub branches b_m together. Hence, a corresponding frame size of the digital output signal Y[q] or Z[q]of the conversion circuit is M ^■ L samples, or points (again in the frequency domain), which corresponds to an M · L-point DFT. Below, q is generally used as a frequency bin index for the M ^■ L point frequency domain signals, whereas k is generally used as a frequency bin index for the L point frequency domain signals.

The purpose of an upsampler unit UP m is twofold; to up-sample the sub DFT sample rate by a factor M and to phase rotate the spectrum so as to compensate for the specific clock phase being used by the associated sub- ADC ADC m. Upsampling with a factor M in the time-domain can be carried out using an -fold rate expander configured to insert M— 1 zeroes between adjacent low rate samples to give the higher rate samples. The upsampler unit UP m, however, operates in the frequency domain with the output from the corresponding sub DFT unit DFT m. With X _m [k] (k E {0, ... , L — 1}) being the output of sub DFT unit DFT m the output of the upsampler unit UP m, Y _m [q] (q E {0, ... , LM— 1}), becomes

)2nq (m— 1)

Ym lq] = Xm lq mod L] ^■ e ML

The spectral replication comes from the modulus operation q mod L. Furthermore, the phase rotation comes from the compensation of the delay associated with respective signal processing sub branch b_m that is t _{d m} = T _s (m— 1)/M. In frequency domain, this delay corresponds to a factor

Recombining these upsampler unit outputs thus yields:

M M

)2nq (m— 1)

Y[q] = ^ Y _m [q] = ^ x _m [q mod L] ^■ e LM

771 = 1 771=1

The receiver frontend 30 may be arranged to generate the analog signal s(t) in quadrature, such that s(t) is a complex signal having an in-phase (I) component and a quadrature-phase (Q) component. Various alternatives are possible for the implementation of the signal processing sub branches b_m for such a complex signal s(t). Some embodiments are illustrated in Figs. 6 and 7. In some embodiments, the sub ADC ADC m in each signal processing sub branch b_m is a complex sub ADC comprising a first real ADC ADC-I_m and a second real ADC ADC-Q_m. The word "real" in this context means that the ADC is arranged to operate on a real, or real- valued, analog input signal to generate a real, or real- valued, digital output signal. ADC-I_m is arranged to convert the I component of the analog input signal s(t) of the conversion circuit 40 to a first real digital output signal of the sub ADC ADC m. ADC-Q_m is arranged to convert the Q component of the analog input signal s (t) of the conversion circuit 40 to a second real digital output signal of the sub ADC ADC m. The first and second real digital output signals of the sub ADC ADC m together forms the digital output signal of the sub ADC ADC m as a complex digital output signal. The first digital output signal is an I component, and the second digital output signal is a Q component of the complex digital output signal.

Fig. 6 illustrates embodiments where the sub transform unit TRANS m partitioned into separate real sub transform units. In each signal processing sub branch b_m, the sub transform unit TRANS m comprises a first real sub transform unit TRANS-I_m and a second real sub transform unit TRANS-Q_m. TRANS-I_m is arranged to operate on the first real digital output signal of the sub ADC (ADC m) to generate a first complex digital output signal component of the sub transform unit TRANS m. TRANS-Q_m arranged to operate on the second real digital output signal of the sub ADC ADC m to generate a second complex digital output signal component of the sub transform unit TRANS m. The first and second complex output signal components together forms the digital output signal of the sub transform unit TRANS_m. Note that the term "real", in this context, indicates that TRANS-I_m and

TRANS-Q_m are arranged to operate on real- valued input signals, but that their respective digital output signals are complex valued. In such embodiments, the combiner unit 100 may be implemented to first combine the output signals from the first real sub transform units TRANS-I_m in all signal processing sub branches b_l-b_ to form a first combined signal Yj [q], and to combine the output signals from the second real sub transform units TRANS- Q_m in all signal processing sub branches b_l-b_ to form a second combined signal Y _Q [q] , which are then combined to form the digital output signal Y[q] of the conversion circuit, e.g. as

Y[q] = Y, [q] + jY _Q [q]

where j denotes the imaginary unit. Each of TRANS-I_m and TRANS-Q_m may comprise a DFT unit, as in the illustration of TRANS m in Figs. 4 and 5. In some embodiments, each of TRANS-I_m and TRANS-Q_m comprises an upsampling unit, as in the illustration of TRANS m in Fig. 5.

Alternatively, in some embodiments, the sub transform unit TRANS m may be

implemented as a complex sub transform unit arranged to operate on the complex digital output signal of the sub ADC ADC m to generate the digital output signal of the sub transform unit TRANS m as a complex digital output signal. This is illustrated in Fig. 7. Refering to Figs. 4 and 5, DFT m may in these embodiments be implemented as a complex DFT unit arranged to operate on a complex-valued input signal.

As described above, the combiner unit 100 may be adapted to detect a mismatch between signal processing sub branches b_m and compensate for the mismatch in the discrete frequency domain. The description below assumes that this correction is performed on the upsampled version of the output signals from the sub DFT units DFT m, regardless of whether the upsampling is performed by an upsampling unit UP m, or by the combiner unit 100. Both gain and phase mismatches can be compensated for by multiplication of this upsampled signal with a complex- valued compensation signal. The frequency domain representation of sub- ADC signals is advantageous over the time-domain representation as mismatch effects in gain, phase, and timing and even in an arbitrary transfer function could all be combined into a single complex multiplication per bin in the upsampled signal. Even the phase rotation in the upsampler can be incorporated here. This is not the case for a time domain based solution.

More specifically, consider the upsampler unit UP m output Y _m [q] (q £ {0, ... , LM— 1}) . We define an error compensation factor, here denoted G _m [q], by which each frequency bin in Y _m [q] is multiplied:

j2nAt _m qf _s

G _m [q] = (1 + Ag _m ) ^■ e LM

Here, G _m [q] includes a first compensation factor (1 + Ag _m ) representing the compensation

j2nAt _m qf _s

of the gain error (Ag _m ), and finally a second compensation factor (e LM ) representing the compensation of the timing error ( t _m ).

To conclude, the recombined output after error compensation becomes:

M M

j2nq (m—1)

Ym lq] G _m [q] = ^ XjAq mod L] ^■ e LM G _m [q] =

771 =1 771=1

where j2nq (m—1)

H _m [q] = e Of G _m [q] i.e. a factor representing the upsampling operation described above times the compensation factor G _m [q] . Thus, as mentioned above, the upsampling operation and the error

compensation can be combined and represented by the factor H _m [q] . Note that the upsampler factors can be pre-computed and that the gain error and timing error factors can be combined to a single complex factor (per frequency bin) after they have been determined.

As elucidated above, for each sample, or "frequency bin", of the upsampled signal that should be compensated, this compensation can be performed by a multiplication with a complex number that corrects the amplitude and the phase for that sample. The computational complexity of performing such compensation in the frequency domain is lower than performing it in the time domain as in a conventional TI-ADC, which in turn facilitates implementing the compensation with a processing circuit with relatively small circuit area and/or relatively low power consumption. For example, if the correction was done in the time domain with an FIR (finite- length impulse response) filter, each time domain sample would have to be multiplied with several (e.g. in the order of 10 or so) filter coefficients, compared with a single complex multiplication per sample, or bin, in the frequency domain.

Furthermore, this multiplication with a complex number could be merged with the

multiplication used to obtain the phase rotation into a single multiplication, further reducing the computational complexity. DC offset can be readily estimated when there is no input signal as any deviation from zero at the output of respective sub ADC ADC m would be a direct measure of the DC offset d _m for said respective sub ADC ADC m. If the DC offset would be compensated for in time domain the estimated DC offset d _m have to be subtracted from every sample of the sub ADC ADC m output. If, on the other hand, the DC offset is compensated for in frequency domain the estimated DC offset d _m would only have to be subtracted from DC bin of the sub transform unit TRANS m output to generate a DC compensated sub transform unit TRANS m output:

Xm.dc would then replace X _m in any of the other equations or expression provided herein in order to achieve DC-compensated signals.

The inventors have realized that error compensation in frequency domain provides further advantages when used in conjunction with communication systems based on OFDM . In for example 3GPP (3 ^rd generation partnership project) LTE (long-term evolution) systems, or other systems that apply orthogonal frequency-division multiple access (OFDMA), only a limited subset of the sub carriers of the down-link OFDM signal are often allocated to a particular wireless terminal. The inventors have realized that e.g. in such situations, there is no need for mismatch compensation in the whole frequency band, since parts of the frequency band that do not carry information directed towards the receiver circuit 20 need not be considered when recovering the information. Thus, in some embodiments, wherein the combiner unit 100 is adapted to detect and compensate for the mismatch in a limited portion of an overall frequency band of the conversion circuit 40. This further reduces the

computational complexity of the mismatch compensation. In some embodiments, the limited portion correspond to subcarriers of a received OFDM symbol that are allocated to the receiver circuit 20. For instance, the limited portion may consist of the frequency bins representing the subcarriers allocated to the receiver circuit 20. Information regarding which subcarriers are allocated to the receiver circuit 20 may e.g. be provided in control information included in a previously received OFDM symbol.

As for the estimation of mismatch effects a number of alternatives are proposed:

Gain mismatch between sub-branches b in may readily be estimated based on comparing total power between different sub ADC outputs as they should, over time, be equal. The power of the sub ADC outputs can be determined in the time domain, based on the time- domain output signals from the sub ADCs, or in the frequency domain, based on the frequency domain output signals of the sub transform units or sub DFT units. For example, an average power level from all sub ADCs within one conversion circuit is calculated and then g _m is calculated for each sub ADC to reach the mean power level. If sub DFT frames are too short then power should be estimated over a number of sub DFT frames to ensure sufficient accuracy. The process outlined above is illustrated with a flowchart in Fig. 8. In step 500, a number of samples, such as a frame of data with M ^■ L samples, are captured by the conversion circuit, In step 510, the average power P _{a m} for each sub ADC ADC m is computed over the L samples captured by that sub ADC ADC m. In step 520, the mean power level P _a of all sub ADCs combined is computed. (In the preceding sentences, the word "average" is used to denote averaging over a number of signal samples, whereas the word "mean" is used to denote averaging over a number of sub ADCs.) In step 530, the "power error" ΔΡ _{α τη} is computed for each sub ADC, e.g. as

ΔΡ a,m = P ¹ a,m— P ¹ a

In step 540, the gain correction parameters g _m are computed, e.g. as α,πι

Gain and time (phase) mismatches between sub-branches b in manifest themselves as aliasing. Thus, correlation between different Nyquist intervals (with respect to sub ADC sample rate f _s ) of the recombined signal Z[q] should be forced to zero so as to minimize residual aliases from sub ADCs which appear as a result of mismatch effects. More specifically, for a first Nyquist interval r E {0, ... , M— 1} and second Nyquist interval p £ {0, ... , M— 1} the correlation between first and second Nyquist interval is calculated as:

to zero. More generally, a set U with N combinations of r, p can be used to form

Optimizing based on C, i.e. selecting the compensation factors that generates the Z[q] that minimizes C, would be a blind optimization of the different mismatch effects exemplified above. However, if the gain mismatch was first removed (say by the method proposed above) then this method could optimize e.g. only on clock phase timing of each sub- ADC.

The method proposed above only makes use of the magnitude of the correlation between Nyquist intervals. The phase of the correlation may however also be exploited. For example, the outputs X _m [k] and X _n [k] from sub DFTs m and n ideally should be equal, except for the (nominal) delay factor _e -j ^2jj:c i ⁽ . ^m - ⁿ⁾ /i ^LM) reflecting the difference in timing between said sub ADCs. Thus, a measure of the timing error between two sub ADCs can be obtained by multiplication of two the outputs from two sub DFTs m and n and normalized with the nominal delay factor:

L—-l

j2nk (m—ri)

X _m [k]Xn [k] /e M

fe=0 The deviation from zero of the phase of D will be a direct indication of time error between the two sub ADCs and an optimization method may operate on At _m to push the phase (or alternatively and simpler the imaginary part) of D to zero thus compensating the time error of sub ADC ADC m with respect to sub ADC ADC n.

This method, however, assumes that only frequencies within one known Nyquist interval k E {0, ... , L — 1} are present. That could be guaranteed with a dedicated test signal (pilot) but generally not with an arbitrary (and unknown) signal covering multiple Nyquist intervals.

DC offset mismatch between sub ADC ADC m can also be conveniently estimated in frequency domain. DC offsets, whether the same or different for all sub ADCs, will manifest themselves as contributions at frequency bins q = rh (r E {0, ... , M— 1}) in the output of the conversion circuit 40. In case there is no input to the conversion circuit and all DC offsets are the same (no DC offset mismatch between sub ADCs), contributions at said frequency bins q = rh (r E {1, ... , M— 1}) are an indication of at least one of gain and phase mismatch and thus it will be harder to distinguish DC offset mismatch from gain and phase mismatch. It is therefore proposed that gain and phase mismatch is compensated before DC offset estimation begins, at least if DC offset estimation is performed based on the output of the conversion circuit 40. Alternatively, DC offset may be estimated on a per sub ADC/DFT basis. Again, with no input signal the first bin of the sub transform unit TRANS m output, X _m [0], will be a direct measure of the associated DC offset. Averaging over several DFT frames can be used to further improve the estimation. In case DC offset is to be estimated in presence of an input signal averaging must be performed over a sufficiently large number of DFT frames to suppress the impact from the input signal as signal power at rf _s (r E {1, ... , M— 1}) will fold down to the DC bin of the sub DFT output.

In some embodiments, the sub transform units TRANS m each comprises a frequency correction unit arranged to align subcarriers of the received signals with frequency bins, or DFT bins, of the output signal of the sub transform unit TRANS m. The frequency correction is performed on the sub ADC output prior to transformation to frequency domain simply by means of multiplying the sub ADC output with a rotating phasor e ^~ i ²ⁿ ^ , where Af is the frequency error to be corrected. It should be noted that frequency correction typically requires DC offset compensation, otherwise the resulting frequency compensated signal is likely to be deteriorated in quality. A reason for this is that with frequency compensation, any remaining DC offset will be frequency shifted as well, and therefore will not be aligned with the DFT bins again, which would lead to interference.

As indicated above, it is beneficial if each subcarrier of a received OFDM symbol is represented with a sample of the output signal Y[q] or Z[q] of the conversion circuit 40. The receiver circuit 20 may comprise circuitry, such as the DSP circuit 50, adapted to derive the timing of the OFDM symbols and providing control signals to conversion circuits indicating start instants for DFT frames. OFDM signals usually incorporate so called cyclic prefixes between OFDM symbols to provide guard periods and reduce inter symbol interference. A cyclic prefix is simply a copy of fraction of the beginning of an OFDM symbol attached to the end or copy of a fraction of the end attached to the beginning. In addition, there may be other separators in time between the OFDM symbols as well. Thus, the DFT frames of the conversion circuit 40 need not be contiguous in time, but there may well be "silent" time periods in between DFT frames. Hence, while the sub ADCs may run continuously, the sub transform units should in these cases operate on a subset of the sample streams from the sub ADCs. The start of the DFT frame can be given as a control signal to the sub transform units, e.g. from the DSP circuit 50.

OFDM signals contain a sequence of consecutive OFDM symbols. As indicated above, in some embodiments, each OFDM symbol has a length corresponding to exactly one DFT frame to allow for direct demodulation of sub-carriers. The conversion circuit will for all practical purposes see the OFDM signal as periodic with LxM samples as long as the LxM samples captured for one OFDM symbol are within the duration of said OFDM symbol and associated cyclic prefix. Therefore, it can also be assumed that each sub ADC ADC m will see exactly the same modulated signal except for a shift in time (disregarding noise and other contributions not related the OFDM symbol being received).

The present invention has been described above with reference to specific embodiments. However, other embodiments than the above described are possible within the scope of the invention. Different method steps than those described above, performing the method by hardware or software, may be provided within the scope of the invention. The different features and steps of the embodiments may be combined in other combinations than those described. The scope of the invention is only limited by the appended patent claims.