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Patent Searching and Data


Title:
OFFSET CORRECTING CIRCUIT FOR ENCODER
Document Type and Number:
WIPO Patent Application WO/1998/051997
Kind Code:
A1
Abstract:
An offset correcting circuit for encoder which can detect accurate offset values even when the sampling period of a low-speed A/D converter, etc., is long, is hardly affected by noise, and is used for such an encoder that detects an angle signal based on digital signals obtained by the A/D-conversion of two signals having phases which are shifted from each other by about 90� at the same timing. The offset correcting circuit is provided with an offset detecting circuit which finds the offset value of one of the two signals by using the A/D-converted value of the signal when the A/D-converted value of the other signal is zero or its vicinity and a compensation circuit which compensates for the phase offset of one signal by using the offset value detected by means of the offset detecting circuit.

Inventors:
Taniguchi, Mitsuyuki (1158-11, Kawashimada Gotenba-shi, Shizuoka, 412-0045, JP)
Inoue, Tadashi (Room 6-201, Fanuc Manshonharimomi 3537-1, Shibokusa, Oshino-mur, Minamitsuru-gun Yamanashi, 401-0511, JP)
Application Number:
PCT/JP1998/002099
Publication Date:
November 19, 1998
Filing Date:
May 12, 1998
Export Citation:
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Assignee:
FANUC LTD (3580, Shibokusa Aza-Komanba Oshino-mur, Minamitsuru-gun Yamanashi, 401-0597, JP)
Taniguchi, Mitsuyuki (1158-11, Kawashimada Gotenba-shi, Shizuoka, 412-0045, JP)
Inoue, Tadashi (Room 6-201, Fanuc Manshonharimomi 3537-1, Shibokusa, Oshino-mur, Minamitsuru-gun Yamanashi, 401-0511, JP)
International Classes:
G01B21/00; G01D5/244; G01D5/245; G01P5/20; H03M1/06; H03M1/30; (IPC1-7): G01D5/245
Foreign References:
JPH07209020A
JPH06201403A
JPH0658769A
JPH07218288A
JPH04365542A
Other References:
See also references of EP 0932027A1
Attorney, Agent or Firm:
Takemoto, Shoji (2F. Yamagata Building, 23-10 Toranomon 1-chom, Minato-ku Tokyo, 105-0001, JP)
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