OPERATION CIRCUIT AND OPERATION CONTROL METHOD THEREOF

WIPO Patent Application WO2005038645

A3

A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0 - 11-(n-1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

NOMURA OSAMU (JP)
MORIE TAKASHI (JP)
NAKANO TEPPEI (JP)

PCT/JP2004/015540

July 14, 2005

October 14, 2004

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CANON KK (JP)
NOMURA OSAMU (JP)
MORIE TAKASHI (JP)
NAKANO TEPPEI (JP)

G06F7/544; G06N3/04; G06N3/063; H03M1/82; H03M5/08; H03K7/08; H03K9/08; (IPC1-7): G06F7/544; H03M5/08; G06N3/04

US4077030A

1978-02-28

KOREKADO ET AL: "A convolutional neural network VLSI for image recognition using merged/mixed analog-digital architecture", LECTURE NOTES IN COMPUTER SCIENCE; 7TH INT. CONF. KES, OXFORD, UK, vol. 2774/2003, 5 September 2003 (2003-09-05), HEIDELBERG, DE, pages 169 - 176, XP002324833, Retrieved from the Internet [retrieved on 20050415]

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