Title:
OPERATION PROCESSING CIRCUIT AND RECOGNITION SYSTEM
Document Type and Number:
WIPO Patent Application WO/2018/074012
Kind Code:
A1
Abstract:
The purpose of the present invention is to carry out parallel processing which is suited to convolution operations in a convolutional neural network. Each of a plurality of selectors sequentially selects, from among data which is retained in a two-dimensional shift register, data in a prescribed two-dimensional region which differs at least partially thereamong. Each of a plurality of two-dimensional convolution operation circuits accumulates the result of multiplying the data which is selected by the corresponding selector with coefficient data which is stored in a coefficient memory, and mutually parallel computes the two-dimensional convolution operation results in the two-dimensional region. Each of a plurality of adders adds, in a channel direction, the results of each of the operations which are performed by the two-dimensional convolution operation circuits and outputs same as a three-dimensional convolution operation result.
Inventors:
SAKAGUCHI HIROAKI (JP)
Application Number:
PCT/JP2017/024422
Publication Date:
April 26, 2018
Filing Date:
July 04, 2017
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G06F17/10; G06N3/063; G06V10/764
Foreign References:
| JP2009080693A | 2009-04-16 | |||
| JP2015210709A | 2015-11-24 | |||
| JP2010134697A | 2010-06-17 | |||
| JP2001067338A | 2001-03-16 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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