OPERATIONAL TRANSCONDUCTANCE AMPLIFIER HAVING TWO AMPLIFICATION STAGES

The object of the present invention is an amplification electronic device. More particularly, the invention relates to an operational amplifier of the transconductance type, comprising two amplification stages .

In order to achieve a reduction of the power consumption in telecommunications equipment and systems, for example, for wireless applications, there is a tendency to reduce the supply voltage of the electronic circuits that are employed in such systems. Due to the development of more and more improved technological processes, it is now possible, also for analog circuit systems, to operate at a supply voltage of about 1.2 V.

Particularly, for applications relating to time- sampled analog networks operating at frequencies of tens/hundreds MHz, such supply voltage of the circuits imposes to implement and employ specific operational amplifiers which are capable of ensuring suitable performance for the above-mentioned applications, with reference in particular to the frequency response of such amplifiers and to the dynamics of the output signal. At the same time, such amplifiers have to ensure a low current consumption.

An operational transconductance amplifier (OTA) of known type currently employed in circuits of time- sampled analog networks, for example, at the supply voltage of 1.2 V, is the Miller amplifier.

Such amplifier comprises two amplification stages, therefore it ensures a suitable voltage gain for most applications . However, the Miller amplifier is not free from drawbacks .

In fact, as it is known, the frequency response of such operational amplifier is determined by the presence of two poles on high impedance nodes of the same amplifier. Particularly, each pole is associated to a high impedance node relative to each of the amplification stages. In order to ensure the stability of such Miller amplifier, it is known to provide for a compensation capacity connected between the above- mentioned high impedance nodes. The introduction of such capacity allows obtaining the pole splitting effect, known to those skilled in the art, that is, it causes the reduction of the characteristic frequency of one of the poles, or fundamental pole, of the operational, and the increase of the second pole characteristic frequency.

In more detail, as it is known to those skilled in the art, following to compensation, the frequency response of the open loop operational amplifier is characterized by a transition frequency F _τ , equal to:

where C _C i is the compensation capacity of the amplifier, and girii is the transconductance of the transistors of the first amplification stage. The frequency of the second pole F ₂ is about:

where C _L is the loading capacity of the amplifier, and gm ₂ is the transconductance of the transistors of the second amplification stage.

As it is known, in order to ensure the stability of the Miller amplifier, the condition has to be true that:

Therefore, the transition frequency F _τ is limited by the second pole F ₂ frequency. Since the whole amplifier bandwidth is determined by the open-loop transition frequency of the response, in order to obtain a suitable band, particularly for wireless applications, it is necessary to increase the girii and gm ₂ values and, consequently, also to increase the current consumption .

The object of the present invention is to devise and to provide an operational amplifier, particularly, of the transconductance type, which allows at least partially obviating to the drawbacks set forth above with reference to the operational amplifiers of the known type.

Such object is achieved by an operational amplifier in accordance with claim 1. Preferred embodiments of said amplifier are defined by the dependant claims 2-10.

Further characteristics and advantages of the above-mentioned operational amplifier will result from the description reported below of a preferred exemplary embodiment, given by way of non-limiting example, with reference to the annexed Figures, in which:

Fig. 1 shows a circuit scheme of an exemplary embodiment of the above-mentioned operational amplifier;

Fig. 2 schematically shows a high-frequency equivalent circuit of the amplifier of Fig. 1; Fig. 3 schematically shows a low-frequency equivalent circuit of the amplifier of Fig. 1.

With reference to the above-mentioned Fig. 1, an exemplary embodiment of an innovative operational amplifier has been generally indicated with 100. Particularly, such operational amplifier 100 is implemented in CMOS technology, and it is preferably a transconductance amplifier adapted to drive a capacitive load C _L . Particularly, it shall be noted that such operational amplifier 100 can be preferably used in time-sampled analog networks at operative frequencies of the order of tens/hundreds MHz.

Furthermore, the amplifier 100 comprises a supply terminal connectable to a supply potential V _DD which is provided, for example, by a battery, and a ground terminal (ground) connectable to a ground potential GND. Preferably, the supply potential V _DD is about 1.2 V.

The operational amplifier 100 comprises, in input, a first amplification stage 101 having input terminals INM, INP to receive a signal to be amplified. Preferably, such first amplification stage 101 is a differential stage provided with respective differential input terminals INM, INP. Particularly, such differential stage comprising PMOS transistors Ml, each of the gate terminals of which are connected to one of the above-mentioned differential inputs INM, INP.

In addition, source terminals of the transistors

Ml are connected to the supply potential V _DD through a PMOS transistor M7. Such transistor M7 is driven by a first reference potential V _B i to generate a bias current for the differential stage 101.

Furthermore, drain terminals of the transistors Ml are connected to respective devices M4 operating as active loads. For example, such active loads are implemented in NMOS transistors M4 driven by a reference potential VCMIN.

In addition, the first amplification stage 101 comprises first differential output terminals Tl and T2 at the drain terminals of the transistors Ml. In this regard, it shall be noted that the operational amplifier 100 has a completely differential circuit structure, therefore it comprises differential output terminals OUTl and OUT2 to provide the amplified signal on the capacitive loads C _L . Particularly, with reference to Fig. 1, such circuit structure is obtained by duplicating the circuit components connected to the above-mentioned first differential output terminals Tl and T2 of the first differential input stage 101. In more detail, the operational amplifier 100 comprises a second amplification stage 102 which is implemented in NMOS transistors M2 in common source. Each second stage transistor M2 has the drain and source terminals connected to one of the amplifier 100 output terminals OUTl, OUT2, and to the ground terminal GND, respectively. First input terminals Ql, Q2 or gate terminals of the transistors M2 are connected to one of the first output terminals Tl, T2 of the first differential stage 101.

The operational amplifier 100 further comprises decoupling devices 103, each of which is so configured as to be interposed between a differential input terminal INM, INP of the first amplification stage 101 and one of the amplifier 100 differential output terminals OUTl, OUT2.

In more detail, each decoupling device 103 comprises an electronic follower device M5 of the signal applied at the input of the first amplification stage 101. Such follower device is implemented in a PMOS transistor M5 configured as a source follower connected to a PMOS bias transistor M6. Particularly, a follower M5 gate terminal, which represents an input terminal for the whole decoupling device 103, is connected to one of the differential input terminals, for example, INM, of the first stage 101. Drain and source terminals of the transistor M5 are connected to the ground potential GND and to the transistor M6, respectively. Such transistor M6 is so configured as to generate a bias current for the follower M5. Such transistor M6 is connected to the supply potential V _DD , and it is driven by a second reference potential V _B 2 •

Furthermore, each decoupling device 103 comprises a further PMOS transistor M3 connected between the supply terminal V _DD and each output terminal OUTl, OUT2 of the operational amplifier 100. Such transistors M3 have respective gate terminals connected to further outputs Ul, U2 of the follower device M5. Particularly, such further outputs coincide with the source terminals of the transistors M5.

It shall be noted that such further transistors M3 represent A-class load transistors for the second amplification stage 102 transistors M2.

With reference to Fig. 1, it shall be noted that, through the bias terminal V _DD and the ground terminal GND, the operational amplifier 100 is connected, by way of example, to a biasing stage 104. Such biasing stage 104 comprises a first MDl and a second MD2 PMOS transistors in a diode configuration, mutually connected in series, and to a bias current generator I _DD . Particularly, the first transistor MDl is adapted to provide a reference potential V _B i _N for an optional common mode potential control network relative to the differential input terminals INM, INP of the first amplification stage 101. Similarly, the second transistor MD2 is adapted to provide the above-indicated second bias potential V _B 2 to the transistor M6 gate terminal of the decoupling stage 103. It shall be noted that the biasing stage 104 is so configured as to ensure a potential equal to the second bias potential V _B 2 to the PMOS transistor M3 gate terminal. In this manner, advantageously, the second potential V _B 2 allows establishing the output current I _O uτ provided to the capacitive load C _L . Furthermore, the operational amplifier 100 of Fig. 1 comprises compensation capacities Cc connected between the gate and drain terminals of the second stage 102 transistors M2. As it is known to those skilled in the art, such capacitors are adapted to stabilize the operational amplifier in terms of frequency response. In fact, through such capacities, the operative frequency associated to one of the poles, or main pole, of the operational amplifier is splitted (pole splitting) towards lower values than that associated to such pole in the absence of compensation. Instead, the frequency of the other pole, or secondary pole, is brought to frequency values above that associated to such second pole in the absence of compensation.

Herein below it shall be assumed that the follower devices M5 of the amplifier 100 are substantially ideal, that is, a voltage V _1N applied to the differential input terminals INM and INP results to be entirely applied to the further outputs Ul, U2 of the decoupling stage 103 (therefore to the gate terminals of the transistors M3) . Furthermore, an amplified voltage present on the amplifier 100 differential output terminals OUTl, OUT2 will be indicated with V _O uτ •

With reference to a high-frequency circuit of Fig. 2, equivalent to the amplifier 100 circuit scheme, it is possible to perform a small-signal analysis (the detailed calculations of which are reported in the annexed Appendix) of the above-mentioned amplifier 100 in the dominion of the Laplace transform to obtain the relationship correlating the output differential voltage V _0UT and the input differential voltage V _1N , that is, a transfer function H(s) of the same amplifier 100. Particularly, such transfer function H(s) is equal to:

where : gm ₁ , gm ₂ and gm ₃ are the transconductance values of the transistors Ml, M2, and M3, respectively,

Ci is the equivalent capacity present on the input of the second amplification stage 102.

In the above-indicated analysis, by the term high frequency are meant frequency values, such that the output resistances of the transistors can be neglected.

This assumption is to be considered as valid for frequency values proximate to a transition frequency F _T of the operational amplifier 100. Such transition frequency is given by:

where C _c is the compensation capacity of the amplifier 100, and girii is the transconductance of the transistors Ml of the first amplification stage 101.

As it is known, said poles of the transfer function H(S) are the values of the complex variable s which cancels the transfer function (1) denominator, while zeros are defined those values of s which make the numerator equal to zero.

With reference to the circuit scheme of the proposed operational amplifier 100, it shall be noted that the decoupling stage 103 is so arranged as to introduce at least one zero in the amplifier 100 transfer function H(S) .

In the particular case of the transfer function (1), the pulsation of the single zero Cϋ _z can be obtained by the equation:

Similarly, the pulsation of the secondary pole of the amplifier 100, can be obtained by the equation :

therefore:

A pulsation of the amplifier 100 main pole, or first pole, can be obtained by performing an analysis of the low-frequency equivalent circuit of the amplifier 100 shown in Fig. 3. By low frequency, it is meant that the above-mentioned analysis is valid for those frequency values for which the Miller effect on the capacity C _c is relevant compared to the other circuit elements. For example, this is valid for frequency values below F _τ /10. Particularly, such main pole is expressed by the relationship:

in which : r _O i is the output resistance of the first amplification differential stage 101 present at one of the first output terminals Tl or T2;

Avo2 is the low-frequency voltage gain of the second amplification stage 102; r _Oϋ τ is the amplifier 100 output resistance present at one of the output terminals OUTl or OUT2.

The above-mentioned pulsation of the main pole is related to the amplifier transition frequency F _τ by the relationship: where is the low-frequency voltage gain of the whole amplifier 100.

In relationship to the transfer function H(s) of the amplifier 100, the Applicant has disclosed that it is advantageously possible to make the above-mentioned zero

Cϋ _z pulsation equal to that of the secondary pole by operating on the amplifier 100 circuit parameters, with the aim of eliminating the effect of such secondary pole .

Particularly, in order for this to occurr, that is, the pulsations of the zero and of the secondary pole coincide, starting from the previous relationships (3) and (4), the condition has to be true that: that is :

therefore

In other terms, once the value of the loading capacities C _L which are driven by the amplifier 100 has been established, once the ratio between the bias currents of the transistors Ml (from which girii depends) of the first stage amplification 101 and those of the transistors M3 (from which gm ₃ depends) has been fixed, it is possible to derive the value of the compensation capacity C _c which satisfies the equation (8), thus ensuring the cancellation of the effect of the secondary pole through the zero

By comparing the above-mentioned relationship (8), which is valid for the amplifier 100, to the relationship (Ia), which is valid for the Miller amplifier, it shall be noted that, while keeping the ratio of transconductance values constant, that is, while keeping the bias currents of the amplifiers constant (since the gm values depend on such currents) , and while keeping the driven capacitive loads C _L constant, the compensation capacity C _c which has to be employed in the amplifier 100 of the proposed solution is advantageously about thrice less than that required to compensate the Miller amplifier of known type. For example, by selecting a gm ratio equal to 4, the relationship (8) implies that the amplifier 100 compensation capacity C _c is equal to one third of the loading capacity C _L . Instead, with reference to the relationship (Ia) relative to the Miller amplifier, by selecting a gm ratio equal to 4, the compensation capacity C _c is always higher than or at most equal to the loading capacity C _L .

Furthermore, since the operational amplifier 100 band is determined by the transition frequency F _τ of the relationship (2), therefore by the pulsation of the main pole ωp ₁ based on (6), following the above-indicated reduction of the compensation capacity C _c , the proposed amplifier 100 advantageously ensures also a higher band than that provided by the Miller amplifier, while keeping the bias currents and loading capacities to be driven constant. In this manner, the amplifier 100 can be advantageously employed in all the more recent wireless applications.

Furthermore, compared to the Miller amplifier, the proposed transconductance amplifier 100 advantageously ensures a reduction of the current dissipation, while keeping the obtained pass band constant.

To the above-described embodiments of the operational amplifier, those of ordinary skill in the art, to the aim of meeting contingent needs, will be able to make modifications, adaptations, and replacements of elements with functionally equivalent other ones, without departing from the scope of the following claims. Each of the characteristics described as belonging to a possible embodiment can be implemented independently from the other embodiments described.

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Appendix

With reference to the high-frequency circuit of Fig. 2, which is equivalent to the amplifier 100 circuit scheme, the ratio between the output differential voltage V _Ouτ and the input differential voltage V _1N , that is, the transfer function H(s) of such circuit, is obtained from:

therefore

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