Background of the Invention Today's optical networks are designed to carry high capacity data signals coded in Non-Return to Zero (NRZ) format using a single wavelength or multiple different wavelengths on a single fiber known as Dance Wave Division Multiplexing (DWDM) technology. Two main factors dictate the communication link length: (a) optical power losses of the data propagating through the fiber, and (b) signal distortion due to chromatic dispersion. Limitations due to non-linear effects caused by Stimulated Brillouin Scattering (SBS) and Four Wave Mixing (FWXM) influence data propagation at extreme use (excessive optical power and ultra long (>1000kln) transmission distance) of the link. Power losses are independent of bit rate, while chromatic dispersion is bit rate dependent. Up to 2. 5Gb/s bit rate transmissions, power losses and chromatic dispersions are treated at reasonable cost-effective factors. AT lOGb/s and higher bit rates, the chromatic dispersion effect becomes a significant distance limitation. The use of Dispersion Compensation Fibers (DCF) controls the chromatic dispersion effect at the cost of increased network management complexity and increased optical power losses along the optical network.

ODB transmission is a scheme of transmitting data at less than half Band-Width (BW) of conventional NRZ modulation, thus improving the tolerance to chromatic dispersion and reduces sensitivity to non-linear effects on the transmitted data, when it is propagating through the fiber.

Fig. 1 illustrates a basic circuit diagram of a prior art single-ended ODB transmitter using an analog encoder. It is composed of four main blocks : Duobinary Precoder (DP) unit 2, Duobinary Encoder (DE) unit 4, a Low Pass Filter (LPF) unit 12 and three level Modulator Driver (MDR) unit 6 and a Mach-Zehnder Modulator (MZM) unit 8.

The DP unit 2 consists of a logic EXOR gate 10, which performs the logic operation between the instant bit [d (k)] and the preceding bit [d (k-1) ] and a one bit<BR> delay circuit 16. The DE unit 4 is an analog summation component 14, e. g. , an analog voltage summation component and not a"logic level"summation component of the current bit [b (k)] and the preceding bit [b (k-1)]. The DE unit 4 output is a three levels voltage signal described in Table 1. wherein,"1"represents a voltage level and not a"logic"level.

The three'levels signal is fed into the MDR unit 6, passes through the LPF 12 and sets the correct offset voltage for driving the MZM unit 8 appropriately.

Similar to the single-ended ODB transmitter of Fig. 1, the prior art ODB of Fig. 2 illustrates a differential implementation using a differential MZM unit 8.

The main difficulties with the prior art approach illustrated in Fig. 1, are the implementation of the DP, DE and the MDR. Especially at high bit rates (IOGb/s and above), the implementation of logic gates, delay lines, analog summation and high power drivers is hard to achieve at reasonable cost and yield, using state of the art industrial processes. Present Silicon Germanium (SiGe) gates and 0.13 plm CMOS can support the EXOR gate and the required delays, but not generate analog summation, which requires high voltage swing and maintaining high linear characteristics.

Disclosure of the Invention It is therefore a broad object of the present invention to ameliorate the shortcomings of the prior art systems and methods for ODB transmission.

It is a further object of the present invention to provide an ODB transmission system and method using a narrow bandwidth MZM of 2. 8 GHz to 3.2 GHz, without degrading from the performance of the system.

It is still a further object of the present invention to provide an ODB system and method utilizing analog switches as an interface between the digital based circuits and units and analog current summation.

It is yet a further object of the present invention to maintain amplitude symmetry of the MZM driving signals by utilizing a close d loop control circuit.

Accordingly, there is provided an optical duobinary (ODB) transmission system, comprising a duobinary precoder receiving data signals and converting said signals into first and second different digital signals each composed of two level voltages; a duobinary encoder fed by the precoder for converting said digital signals into three level analog signals, and a close loop control circuit for maintaining equal drive voltages for driving a Mach Zehnder Modulator (MZM).

The invention further provides a method of encoding NRZ data for optical duobinary (ODB) transmission, comprising receiving a non-return to zero data sequence; converting said sequence into ODB format by utilizing a digital encoder to produce signals of first and second voltage levels; feeding said first and second voltage levels to a duobinary encoder for converting said voltage levels into three level analog signals, and passing said signals through a close loop control circuit for maintaining equal drive voltages for driving a Mach Zehnder Modulator (MZM).

Brief Description of the Drawings The invention will now be described in connection with certain preferred embodiments with reference to the following illustrative figures, so that it may be more fully understood.

With specific reference now to the figures in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present invention only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention, the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention may be embodied in practice.

In the drawings: Fig. 1 illustrates a prior art single-ended ODB system using an analog encoder; Fig. 2 illustrates a prior art differential implementation using an analog encoder: Fig. 3 is a circuit and block diagram of the ODB transmission system according to the present invention; Fig. 4 is a block diagram detailing an embodiment of the control circuit of Fig. 3 for a single ended mode; Fig. 5 is a circuit and block diagram of an embodiment for a differential mode of the system according to the present invention, and Fig. 6 is a schematic representation of a single-ended MZM showing the applied electrical field.

Detailed Description of Preferred Embodiments There is illustrated in Fig. 3 an ODB transmission system 20 composed of a DP and DE unit 22, a control unit 24 and a MZM 26. The specific circuit shown in unit 22 is that for a single-ended implementation. Seen is a DP consisting of an EXOR gate 28 and analog switches 30, constituted by e. g. , a Delay Flip-Flop (DFF). The input to the DP is a NRZ data line and a 10 GHz clock 32. The DE is an analog summation of voltages across two identical resistors 34, 36 and analog switches 30. The close loop control unit 24 advantageously also incorporates an MDR for driving the MZM 26, and is operationally connected via a variable resistor 3 8 of a value 2R +AR to the DE.

Referring to Fig. 4, there is shown a single component DP, DE 40 including the DP and DE unit 22 and details of an embodiment of the control unit 24. The latter consists of LPF's 42,44 receiving from the component DP, DE 40 signals V27i and Vn, respectively, leading to an attenuator 46 and a Vs peak detector 48. The V2 signal passes through the attenuator 46 through amplifier buffer 50 to a V2 peak detector 52 and via an error amplifier 54, to a filter and driver 56 back to the attenuator 46. Another output from the peak detector 52 leads through an analog driver 58, an error detector 60, a filter and driver 62 and via the variable resistor 38 to the DP, DE component 40.

Fig. 5 illustrates a differential implementation of the invention. This embodiment is very similar to the embodiments of Figs. 3 and 4, except for the variations, necessitating from the two signal outputs. Seen are the two DE analog switches 30, 30', wherein one of the switches 30'is fed by the clock 32 through an inverter 64. The control unit 24'is provided with a voltage divider consisting of resistors 66, 68 for producing a voltage V/2, as will be explained hereinafter.

Each of the ODB transmission systems using single or dual conventional MDR's operate at three voltage levels, OV, VTC or V211 in case of the single-ended mode of Figs.

3 and 4, and OV, Vs/2 and Vie in the case of the differential transmission mode of Fig. 5.

In order. to maintain Duobinary advantages, the phase modulation component (which creates chirp) in the transfer function of the MZ, must be cancelled. In the single-ended embodiment (Fig. 3) the signal amplitude symmetry is maintained by the close loop circuit (the phase between the electrical field across the MZ arms are taken care by the MZ structure) and in the differential embodiment (Fig. 5) both factors, amplitude and phase between the driving signals are taken care by the close loop control circuit.

Referring now to Fig. 6, the following explains how to eliminate the phase modulation term in the transfer function of the MZM 26, assuming the input optical power is PIN=I and 50% of the input power propagate in each of the MZ waveguides 70, 72. The voltage creates an optical phase shift of +1 in the first electrode 74 and an optical shift of (j) 2 in the second electrode 76. Hence, PM component AM component wherein, V1-Voltage across the first waveguide; V2 = Voltage across the second waveguide; Pout = Modulator's optical output power, and V7r = Half wave voltage.

As can be seen in the above equation, the elimination of the PM term is when Vl =-V2.

Two close loop control circuits are devised to maintain the above requirements.

For the single-ended symmetry close loop control circuit (Fig. 4), the control circuit includes two independent sub-control loops. One takes care of the required output voltage V211 and the other sub-control loop takes care of the output symmetry. The output peak signal divided by 2 is the reference to the symmetry loop and the feedback signal V7E, which represents the actual peak voltage of half the output amplitude, is brought to the DE unit 22.

The symmetry control unit for the differential implementation (Fig. 5) consists also on two sub-control loops, but in this case, the loops are dependent on each other. The output control loop maintains the required output voltage set by V. The reference signal to the amplitude symmetry sub-loop is half of the VOUTI peak voltage. The analog voltage divider, consisting of two identical resistors (66,68), will provide a stable (DC) signal at the feedback point only if VOUT] and VOUT2 will be identical in amplitude and phase. In order to avoid unstable operation, the response of the output voltage should be much faster, as compared with the amplitude symmetric loop.

Hence, with the above-described system, it is possible to use a 2.8 GHz to 3.2 GHz, narrow band MZM while maintaining an acceptable system performance, thereby significantly reducing costs.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrated embodiments and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.