CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application Serial No. 63/266,201 , entitled “Optical Module Including Metasurface Chip and Methods of Manufacturing Thereof” and filed December 30, 2021 , which is incorporated herein by reference in its entirety for all purposes.

FIELD OF THE INVENTION

[0002] The present invention generally relates to optical modules including metasurface chips and methods of manufacturing thereof.

BACKGROUND

[0003] Wave-front shaping and beam-forming are procedures in which the spatial amplitude/phase distribution of the free-space propagating light can be tailored in order to create a desired beam pattern (e.g., focal spot, deflection, and holography). The traditional methods, widely used in industry, involve dielectric parabolic mirrors/lenses which are bulky, relatively heavy, and curved. These undesired features stem from the physical mechanism behind conventional optical lenses, which is the enforcement of different optical path lengths to accumulate distinct phase delays. In contrast, metasurfaces include non-uniform subwavelength scatterers with capability of abrupt control over the reflection/transmission phase (0-2TT) and amplitude (0-1 ) at the interface. These spatially varying phase shifts over the incident light can be realized by utilizing an array of unit-cells having carefully engineered constituent materials, geometry, orientation, and structural parameters.

[0004] In general, meta-surfaces as artificially structured materials can offer device miniaturization, planar and thin form, high spatial resolution, and opportunity of dense integration into optical devices. In addition, they have the potentials to be used for steering the beam propagation direction, shaping the wave-front of light, and imparting information for applications such as sensing, imaging, light detection, and ranging (e.g. LiDAR). Although there has been remarkable progress in the design of optical meta-surfaces as a promising replacement for conventional optical elements (e.g., gratings, lenses, holograms, wave-plates, polarizers, and spectral filters), there remain several limitations that have not been adequately addressed including the overall efficiency of the large- scale graded-pattern meta-surfaces. In particular, it may be beneficial to achieve highly efficient beam deflection engineering (e.g., maximizing the diffraction efficiency) in order to transfer the total intensity of the impinging light into a desired deflection angle. This can be considered as the underlying mechanism behind a wide range of optical imaging/sensing devices. Thus, it can have a significant impact on the next-generation of flat-lenses with not only low-cost fabrication, planar form factor, and compactness but also relatively high optical efficiency.

SUMMARY OF THE DISCLOSURE

[0005] Systems and methods in accordance with various embodiments of the invention can include a metasurface module including: a secondary substrate; and a metasurface chip mounted on the secondary substrate, wherein the secondary substrate laterally extends from all sides of the metasurface chip to completely surround the metasurface chip.

[0006] In various other embodiments, the metasurface chip has a minimal border region.

[0007] In still various other embodiments, the second substrate is coated with a coating.

[0008] In still various other embodiments, the coating is at least one selected from the group consisting of: an opaque optical aperture, an anti-reflection coating, an optical filter coating, an electrical circuit, and a conductive layer.

[0009] In still various other embodiments, the optical filter coating comprises at least one selected from the group consisting of: a high-pass coating, a low-pass coating, and a band-pass coating. [0010] In still various other embodiments, the conductive layer is configured to provide eye safety.

[0011] In still various other embodiments, the coating includes patterned features and the metasurface chip is aligned with the patterned features.

[0012] In still various other embodiments, the metasurface chip is mounted to the secondary substrate by an optically transparent bond.

[0013] In still various other embodiments, the metasurface module, further includes a housing, wherein the secondary substrate is mounted to the housing.

[0014] Systems and methods in accordance with various embodiments of the invention can further include a metasurface module including a metasurface chip completely surrounded by a polymer material.

[0015] In various other embodiments, the polymer material is coplanar with a top surface of the metasurface chip.

[0016] In still various other embodiments, the metasurface chip has a minimal border region.

[0017] In still various other embodiments, the metasurface chip is coated with a coating.

[0018] In still various other embodiments, the coating is at least one selected from the group consisting of: an opaque optical aperture, an anti-reflection coating, an optical filter coating, an electrical circuit, and a conductive layer.

[0019] In still various other embodiments, the optical filter coating includes at least one selected from the group consisting of: a high-pass coating, a low-pass coating, and a band-pass coating.

[0020] In still various other embodiments, the conductive layer is configured to provide eye safety.

[0021] In still various other embodiments, the coating includes patterned features and the metasurface chip is aligned with the patterned features.

[0022] In still various other embodiments, the metasurface module further includes a housing, where the metasurface chip is mounted to the housing through the polymer material. [0023] Systems and methods in accordance with various embodiments of the invention can further include a method of manufacturing an optical device, the method including: providing a metasurface chip; providing a secondary substrate, where the metasurface chip has smaller dimensions than the secondary substrate; and mounting the metasurface chip to the secondary substrate, where the metasurface chip completely overlaps with the secondary substrate.

[0024] In various other embodiments, the secondary substrate is a singular die that supports the metasurface chip.

[0025] In still various other embodiments, the secondary substrate is a wafer that is capable of supporting multiple metasurface chips, the method further includes singulating the secondary substrate into a singular die with the mounted metasurface chip.

[0026] In still various other embodiments, the metasurface chip has a minimal border region.

[0027] In still various other embodiments, the method further includes: providing a housing; and mounting the metasurface chip to the housing through the secondary substrate such that the secondary substrate directly contacts the housing.

[0028] In still various other embodiments, the metasurface chip does not contact the housing.

[0029] Systems and methods in accordance with various embodiments of the invention can further include a method of manufacturing an optical device, the method including: providing a metasurface chip; mounting the metasurface chip on a substrate; backfilling the metasurface chip with a polymer material such that the polymer material completely surrounds the metasurface chip and is coplanar with the top surface of the metasurface chip; and singulating the metasurface chip and polymer material completely surrounding the metasurface chip.

[0030] In various other embodiments, the method further includes curing the polymer material into a hard plastic.

[0031] In still various other embodiments, the metasurface chip has a minimal border region. [0032] In still various other embodiments, the method further includes: providing a housing; mounting the metasurface chip to the housing through the polymer material such that the polymer material directly contacts the housing.

[0033] In still various other embodiments, the metasurface chip does not contact the housing.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The description will be more fully understood with reference to the following figures, which are presented as exemplary embodiments of the invention and should not be construed as a complete recitation of the scope of the invention, wherein:

[0035] Fig. 1 illustrates an example optical module with a metasurface chip.

[0036] Fig. 2 illustrates an optical module with a metasurface chip in accordance with an embodiment of the invention.

[0037] Fig. 3 is a comparison between the metasurface chip of Fig. 1 and the metasurface chip of Fig. 2.

[0038] Fig. 4 illustrates an example final structure of metasurface elements formed on a glass handle wafer after a die-to-wafer bonding process in accordance with an embodiment of the invention.

[0039] Fig. 5 illustrates an example metasurface device including structure of metasurface optical elements formed on a silicon wafer in accordance with an embodiment of the invention.

[0040] Fig. 6 illustrates the metasurface device of Fig. 5 after a reduction of the thickness of the silicon wafer in accordance with an embodiment of the invention.

[0041] Fig. 7 illustrates the metasurface device of Fig. 6 after dicing the thinned silicon wafer in accordance with an embodiment of the invention.

[0042] Fig. 8 illustrates an example of the metasurface device of Fig. 7 after transferring the thin silicon wafer onto a handle wafer in accordance with an embodiment of the invention.

[0043] Fig. 9 illustrates another example of the metasurface device of Fig. 7 after transferring the thin silicon wafer onto a handle wafer in accordance with an embodiment of the invention.

[0044] Fig. 10 illustrates an example of the metasurface device of Fig. 8 or Fig. 9 after removal of the remaining silicon wafer.

[0045] Fig. 11 illustrates an example of the metasurface device of Fig. 10 after an optional coating/pattern/encapsulation wafer.

[0046] Fig. 12 illustrates an example of the metasurface device of Fig. 11 after dicing the handle wafer.

[0047] Fig. 13A illustrates an example of the metasurface device of Fig. 11 after formation of multiple optical elements.

[0048] Fig. 13B illustrates an example resultant metasurface device where the metasurface elements include multiple metasurface elements on each side of the handle wafer after dicing.

[0049] Figs. 14A and 14B illustrate examples of a metasurface device including stacked handle wafers.

[0050] Fig. 15 illustrates the metasurface device of Fig. 11 including a bonded traditional refractive lens on one side of the handle wafer.

[0051] Fig. 16 illustrates the example steps of the polymer packaging to fabricate metasurface chips.

[0052] Fig. 17 illustrate the resultant polymer packaged metasurface chip after the process of Fig. 16.

DETAILED DESCRIPTION

[0053] Disclosed herein is an optical module including a metasurface chip and methods of manufacturing thereof. In some embodiments, the optical module may include multiple elements, including, for example, an optical element. The optical element may include metasurface optical element. The optical module may be a camera including an image sensor or the optical module may be an illuminator including a light source. The light source may include a laser. A low manufacturing cost of these optical elements may be commercially important for a successful product. For many optical elements (including metasurface optical elements), the manufacturing cost may be proportional to the chip size. For example, the optical elements may be fabricated on a wafer, where the cost of the wafer may be constant no matter how many elements fit on the wafer. Therefore, reducing the area of the chip may significantly reduce the cost of manufacturing the chip. In many configurations, the optical element may include an optically active region (e.g. the extent of the metasurface nanostructures on the metasurface optical element) on a transparent substrate/chip. It may be common that the area of the optically active region is substantially smaller than the transparent substrate/chip, primarily due to mechanical considerations of module construction. In some examples, the chip may be made bigger or smaller depending on the size of the housing in the optical module. Various disclosed embodiment can minimize the area of the optical element, while maintaining the ability to manufacture the module by enlarging the footprint of the optical module without wasting chip space.

Embodiments Including a Secondary Substrate

[0054] Described herein is a device and method minimizing the area (and therefore cost) of an optical element on a chip, while allowing for successful module integration. In this method and/or device, the optical element may be sized such that it is only marginally larger than the optically active surface. For example, if the optically active area is 1x1 mm, then the optical element can be 1.2x1 ,2mm (providing a 0.1 mm border around the active surface). Subsequently, the optical element may be bonded to a second (and larger) transparent substrate (e.g. a module cover glass; handle wafer) using an optically transparent bond (e.g. a transparent adhesive, or direct glass-glass bond). The second substrate may be substantially larger in area than the optical element, which allows for simple mechanical construction of the module. However, in some instances, since the second substrate has no optical function, and does not undergo expensive fabrication processes, the cost is very low, even for a large area.

[0055] Fig. 1 illustrates an example optical module with a metasurface chip. The optical module may include an opaque entrance 102 (e.g. aperture). A cover glass 104 may be positioned below the opaque entrance 102. The opaque entrance 102 may be integrated within a housing 106. A metasurface chip 108 may be integrated below the cover glass 104. The metasurface chip 108 includes an optical element/chip area 108a which may include an optically active area 108b. The bottom surface of the metasurface chip 108 includes an optically active surface 110 which overlaps the optically active area 108b. A light emitter (e.g. a laser) or a light detector 112 (e.g. an image sensor) may be positioned to emit radiation to or receive radiation from the metasurface chip 108. The light emitter or light detector 112 may be positioned on a substrate 114 (e.g. PCB, ceramic, flex circuit, etc). As illustrated, the metasurface chip 108 extends across the entire housing 106 which make the chip area much larger than the optically active area. The extra border area 116 for the metasurface chip 108 may be used to allow the metasurface chip 108 to fit in the housing 106. However, this extra border area 116 may increase the wasted area of the metasurface chip 108.

[0056] Fig. 2 illustrates an optical module with a metasurface chip in accordance with an embodiment of the invention. The optical module may be a metasurface module. Fig. 2 shares many identically labeled components to the device disclosed in Fig. 1. The description from Fig. 1 are applicable to Fig. 2 and these descriptions will not be repeated in detail. In Fig. 2, a metasurface chip 202 may be mounted on a secondary substrate 204 which may extend across the entire housing 106. The secondary substrate 204 may be mounted to a border region 210 of the housing 106. The metasurface chip 202 may be mounted to the secondary substrate 204 through an optically transparent bond 206. The metasurface chip 202 has an optically active area 202a which is only marginally smaller than the size of the metasurface chip 202 resulting in minimal wasted area. Thus, the metasurface chip 202 has minimal border region. Mounting the metasurface chip 202 to a secondary substrate 204 may be much less expensive than the wasted extra border of the metasurface chip 202. The secondary substrate 204 allows the metasurface chip 202 to be properly mounted within the housing 106. The secondary substrate 204 laterally extends from all sides of the metasurface chip 202 to completely surround the metasurface chip 202. The metasurface chip 202 includes an optically active surface 208 which receives light from the light emitter or the light detector 112. The optically active surface is opposed to the surface bonded by the optically transparent bond 206 to the secondary substrate 204. [0057] Fig. 3 is a comparison between the metasurface chip 302 of Fig. 1 and the metasurface chip 304 of Fig. 2. As illustrated, the metasurface chip 302 of Fig. 1 is much larger than the metasurface chip 304 of Fig. 2 which would make it much more expensive to manufacture while both of the chips are functionally similar. On the same wafer size, many more optical elements may be manufactured with the design of metasurface chip 304 of Fig. 2 when compared to the design of the metasurface chip 302 of Fig. 1 .

[0058] For the metasurface chip 302 of Fig. 1 , an optically active area 306 may be 1x1 mm; the optic element size may be 2x2mm; an optic element area 302a may be 4mm ² ; the estimated optical elements per 300mm wafer may be 16,184. For the metasurface chip 304 of Fig. 2, an optically active area 306 may be 1x1 mm; the optic element size may be 1.2x1 ,2mm; an optic element area 304a may be 1.4mm ² ; the estimated optical elements per 300mm wafer may be 45,212. Thus, for the same functional optically active area and thus the same functionality, the metasurface chip 304 of Fig. 2 may be fabricated on a much smaller footprint which leads to much more optical elements per wafer.

[0059] Various embodiments of the invention include various methods of fabrication of the metasurface chip mounted on the secondary substrate. For example, a first method includes a die-to-die process. In this method, the metasurface chip may be bonded to the singulated secondary substrate. This may take place during module assembly, or alternatively the bonding could be considered part of the full optical element fabrication.

[0060] Further, a second method may include a die-to-wafer process. In this method, a plurality of singulated optical elements are bonded (one-by-one or in combination) to a single large secondary substrate (e.g. a wafer). After all optical elements are bonded to the secondary substrate, it is also singulated, resulting in the final form for module assembly.

[0061] A metasurface may include nanostructured elements formed on a wafer. In some cases, it may be desired to fabricate the nanostructured elements on a silicon wafer and then transfer the nanostructure elements to a transparent (e.g. glass) wafer. Methods of transfer include wafer-to-wafer bonding, die-to-wafer bonding, and die-to-die bonding. Die-to-wafer bonding allows for fan-out or separation of individual elements at the same time as layer transfer, which can reduce the cost of the final optical element. [0062] An example die-to-wafer bonding process flow for a metasurface optical element includes:

• Forming metasurface optical element on silicon wafer

• Reducing the thickness of the silicon wafer

• Dicing silicon wafer

• Die-to-wafer bonding of metasurface chip to handle wafer

• Removal of residual silicon wafer

• Dicing of handle wafer

Examples of these process flow are illustrated and described in connection with Figs. 4- 15 below.

[0063] Fig. 4 illustrates an example final structure of metasurface elements formed on a glass handle wafer after a die-to-wafer bonding process in accordance with an embodiment of the invention. As illustrated, a metasurface element 402 is manufactured on a glass handle wafer 404. The metasurface element 402 may be embedded within an encapsulant 406.

[0064] Fig. 5 illustrates an example metasurface device including structure of metasurface optical elements 500 formed on a silicon wafer in accordance with an embodiment of the invention. Each of the metasurface optical elements 500 includes nanostructures 504 which may be formed on a silicon substrate 502. The nanostructure 504 may include cylindrical pillars, or in other embodiments may include other cross- sectional shapes, such as for example, square, rectangle, oval, or cross, or the nanostructure may be a cylindrical or other shaped tube. The cylindrical pillars may have a 700nm height and a diameter of 100 to 300nm, or in other embodiments may have a height in a range from 400-900nm, 500-800nm, or 600-750nm, and/or a cross-sectional diameter or dimension in a range from 100-500nm, or 200-400nm. The cylindrical pillars may be amorphous silicon. The nanostructures 504 may include metasurface optical elements described in U.S. Pat. Pub. No. 2019/0064532, entitled “Transmissive Metasurface Lens Integration” and filed Aug. 31 , 2018, which is hereby incorporated by reference in its entirety for all purposes.

[0065] Between the nanostructure 504 and the silicon substrate 502 may be at least one etch stop layer 506 which serves to facilitate subsequent removal of the silicon substrate 502 via etching. The at least one etch stop layer 506 may include SiO2. Between the nanostructure and the silicon substrate may also be one or more layers, serving as an anti-reflection coating. The nanostructure may be coated with an encapsulant 508. The encapsulant 508 may be a low index dielectric material such as SiO2 and the surface of the encapsulant 508 may be planarized, using a process such as chemical mechanical polishing. Individual metasurface elements 500 may be arrayed across a wafer. In some embodiments, a gap between the metasurface elements 500 may be chosen to facilitate subsequent die singulation, via a process such as mechanical dicing, plasma etching, laser dicing, etc.

[0066] Fig. 6 illustrates the metasurface device 600 of Fig. 5 after a reduction of the thickness of the silicon wafer in accordance with an embodiment of the invention. The silicon substrate 502 upon which the nanostructure is formed may be a standard silicon substrate thickness, such as 775pm for a 300mm diameter silicon wafer. After formation of the nanostructure 504 and subsequent encapsulation and planarization, the silicon substrate 502 may be thinned, using a process such as grinding, lapping, etching to form a thin silicon substrate 502a. The substrate 502 may be thinned to a residual thickness which is suitable for subsequent etching (e.g. 50pm).

[0067] Fig. 7 illustrates the metasurface device 600 of Fig. 6 after dicing the thinned silicon wafer in accordance with an embodiment of the invention. The metasurface device 600 formed of the thinned silicon wafer containing the metasurface optical elements may be singulated into individual chips using a cutting process such as mechanical dicing, plasma etching, laser dicing, or other such process. After dicing the wafer, the metasurface devices 600 may be mounted on dicing tape. The metasurface device 600 may form individual die.

[0068] Fig. 8 illustrates an example of the metasurface device of Fig. 7 after transferring the thin silicon wafer onto a handle wafer in accordance with an embodiment of the invention. The individual die 600 may be transferred individually or in a group from dicing tape onto a new wafer 802 (e.g. a handle wafer). The handle wafer 802 (e.g. glass) may be chosen to be transparent to the wavelength of light at which the optical element operates (e.g. 940nm). The properties of the glass wafer 802 may be chosen such that certain mechanical properties (e.g. coefficient of thermal expansion) match those properties of the individual die 600. For example, the handle wafer 802 may be a glass material such as Corning Eagle XG and Schott BF33 which are suitable as they have similar coefficient of thermal expansion (CTE) to silicon. The thickness of the handle wafer 802 may be chosen to meet the optical and mechanical properties of the final optical element, such that no further thinning of the handle wafer may be performed (e.g. 300pm). The handle wafer 802 may include deposited layers on one or both sides, including antireflection coatings, conductive layers (patterned or un-patterned) such as indium tin oxide, light absorbing, and/or light blocking layers (patterned or unpatterned). Such deposition and patterning may occur before or after the die-to-wafer bonding. The spacing 808 between the individual die 600 may be such that the final optical element size meets requirements for mechanical assembly into a module. The final die size may be substantially larger than the metasurface size. The individual die may be transferred to the handle wafer 802 using a Die-to-Wafer bonding process. The transfer may be performed using pick-and-place equipment. The bond between the individual die 600 and the handle wafer 802 may be formed using many different processes, including adhesive bonding, direct SiO2-to-SiO2 bonding, anodic bonding, or thermocompression bonding. In the case of SiO2-to-SiO2 bonding, the surfaces of the individual die 600 and the handle wafer 802 may be activated using plasma, wet chemistry, or a combination of both. In the case of SiO2-to-SiO2 bonding, the surfaces of the wafers may have been coated with an appropriate bonding layer (e.g. SiCh) and polished in order to reduce the average surface roughness to <1 nm. In some embodiments, the average surface roughness may be <0.5nm. After the individual dies 600 are transferred to the handle wafer 802, the bond strength may be increased using a curing, annealing, or related step which may include pressure, temperature, and/or UV radiation. The metasurface nanostructure layer 804 may face the handle wafer 802 such that the metasurface nanostructure layer 804 is closer to the handle wafer 802 than the silicon substrate. There may be a bond interface 806 between the individual die 600 and the handle wafer 802. The individual die 600 may be mounted on the handle wafer 802 to completely overlap the handle wafer 802. [0069] Fig. 9 illustrates another example of the metasurface device of Fig. 7 after transferring the thin silicon wafer onto a handle wafer in accordance with an embodiment of the invention. A further embodiment of the die to wafer bonding process includes bonding multiple different individual chips from the same or separate silicon wafer onto a single handle wafer. In this embodiment, a first individual chip 600a of type 1 and a second individual chip 600b of type 2 may be transferred to the same handle wafer 802. Type 1 and Type 2 individual chips may be different in size, shape, or optical functionality. For example, the Type 1 chip may be designed for transmitted light applications, and Type 2 may be designed for received light application. Alternatively, the Type 1 and the Type 2 may be both designed for transmitted (or received) light applications, though the designs may differ. For example, the Type 1 chip may be designed for a dot pattern projector and the Type 2 chip may be designed for a diffuser. There may be different chip spacing for each chip. For example, a first chip spacing 808a may separate the first individual chip 600a and the second individual chip 600b and a second chip spacing 808b may also separate the first individual chip 600a and the second individual chip 600b.

[0070] Fig. 10 illustrates an example of the metasurface device of Fig. 8 or Fig. 9 after removal of the remaining silicon wafer. After bonding of the individual die 600 to the handle wafer 802, the remaining silicon substrate may be removed using a process including wet chemical etching, plasma etching (including reactive ion etching), or a combination. The removal method may include etch selectivity between silicon and the etch stop layer. The etch selectivity may be high, at least >10:1 or >100:1 so that the nanostructure layer is not damaged and not inadvertently removed during etching. Further, the exposed surface of the handle wafer 802 and any exposed coatings may have a high etch selectivity to the silicon removal process, at least 10:1 or at least 100:1 . Thus the metasurface nanostructure layer 804 may remain on the handle wafer 802 while the silicon wafer may be removed.

[0071] Fig. 11 illustrates an example of the metasurface device of Fig. 10 after an optional coating/pattern/encapsulation wafer. After removal of the residual silicon substrate, a coating 1102 may be deposited on the exposed nanostructure 804. The coating 1102 may include deposited layers to reduce moisture penetration of the nanostructure, anti-reflection coatings, conductive layers (patterned or un-patterned) such as indium tin oxide, light absorbing, and/or light blocking layers (patterned or unpatterned).

[0072] Fig. 12 illustrates an example of the metasurface device of Fig. 11 after dicing the handle wafer. The diced elements 1204 may be the final individual optical elements. Gaps 1202 may exist between the diced elements 1204. Final process step may include singulating the handle wafer by dicing the handle wafer into individual optical elements. In some embodiments, the individual optical elements 1204 may contain one metasurface chip, or multiple metasurface chips (e.g. one or more Type 1 chip(s) and one or more Type 2 chip(s) or additional chip types).

[0073] Fig. 13A illustrates an example of the metasurface device of Fig. 11 after formation of multiple optical elements. The method of metasurface formation using die- to-wafer bonding described above in connection with Figs. 8-11 can be repeated to form a metasurface optical element 1302 containing functional metasurfaces on both sides of the handle wafer 802. For example, before dicing, the handle wafer 802 may have metasurface elements 804 transferred to its first side and may have additional metasurface elements 1302 bonded to its second side, and those metasurface elements 1302 may be aligned to the metasurface elements 804 formed on the first side. The metasurface elements 804 on the first side may have different size, shape, and optical functionality as the metasurfaces 1302 on the second side. Similar to the metasurface elements 804 on the first side, a coating 1306 may be applied to the metasurfaces 1302 on the second side. As with Fig. 11 , after die-to-wafer bonding and silicon removal on the second side of the handle wafer, the handle wafer 802 may be singulated into individual optical elements 1308. Gaps 1310 may be formed between adjacent optical elements 1308. The gaps 1310 may separate metasurface elements 804 on one side of the handle wafer 802 and metasurface elements 1302 on the other side of the handle wafer 802.

[0074] In some embodiments, the gaps may be between multiple metasurface elements 804, 1302 on each side of the handle wafer after dicing, leaving multiple metasurface elements 804, 1302 on each side of the individual diced elements. Fig. 13B illustrates an example resultant metasurface device where the metasurface elements 1306 include multiple metasurface elements 804, 1302 on each side of the handle wafer 802 after dicing. The metasurface device shares identically labeled elements of Fig. 13A and the description in connection with Fig. 13A is applicable and is not repeated. As illustrated, each side of the handle wafer 802 includes multiple metasurface elements 804, 1302 separated by the gap 1310. In some embodiments, one side may include multiple metasurface elements separated by the gap 1310 and another side may only include a single metasurface element separated by the gap 1310.

[0075] Figs. 14A and 14B illustrate examples of a metasurface device including stacked handle wafers. As illustrated, the metasurface device is fabricated similarly to the method illustrated in Fig. 13A however this metasurface device is stacked to include more than two metasurface elements prior to singulating the handle wafer 802. Fig. 14A illustrates a single function optic stack in accordance with an embodiment of the invention. As illustrated, prior to singulation, another handle wafer 1404 may be bonded to the coating 1306. Metasurface elements 1402 may be positioned on the other handle wafer 1404. Another coating 1410 may be positioned on the metasurface elements 1402. The device may be singulated into multiple individual chips 1406 with gaps 1408 between adjacent individual chips 1406.

[0076] Fig. 14B illustrates a multi-function adjacent optical stack in accordance with an embodiment of the invention. The multi-function adjacent optical stack may have missing metasurface elements in different locations. Similar to the device of Fig. 14A, another handle wafer 1404 may be bonded to the coating 1306. Metasurface elements 1402 may be positioned on the other handle wafer 1404 with another coating 1410 positioned on the metasurface elements 1402. In the device of Fig. 14B, there are positions 1502 where metasurface elements 1402 may be absent. After singulation, there may be individual chips which include different functionality to other individual chips.

[0077] In some cases, it may be desirable to add certain features to the other handle substrate 1404, including but not limited to: Opaque optical aperture (f-stop); Antireflection coating; Optical filter coatings (e.g. high-pass, low-pass, band-pass, etc); and/or Electrical circuit and/or conductive layers for eye safety. In such cases it may be necessary to align the optical element with patterned features on the other handle substrate 1404. In some embodiments, at least some of the coatings may be placed on the metasurface chip. For example, some coatings may be on the other handle substrate 1404 and some coating may be on the metasurface chip.

[0078] Fig. 15 illustrates the metasurface device of Fig. 11 including a bonded traditional refractive lens on one side of the handle wafer 802. As illustrated, a refractive lens 1504 may be bonded to the side of the handle wafer 802 opposite to the metasurface elements 804. Similar to Fig. 12, the handle wafer 802 may be singulated including the die-to-wafer bonding of the refractive lens 1504 on one side of the handle wafer 802, creating a hybrid metasurface-refractive optical element. In some embodiments, a multifunction adjacent optic stacks may be created including traditional optics similar to what is described in connection with Fig. 14B.

Embodiments Including Polymer Packaging

[0079] Embodiments of this disclosure include a process flow for encasing the optical element chip into a polymer packaging. The process may include a first step including create a “reconstructed wafer.” This may be achieved by first creating a wafer of optical elements, chip size only marginally larger than active optical area. Next, the wafer may be singulated into individual chips. Next, the individual chips may be transferred individually using a pick-and-place technique.

[0080] Fig. 16 illustrates the example steps of the polymer packaging to fabricate metasurface chips. In a first step, the “Reconstructed Wafer” is created on a tape 1604, with sufficient space between optical elements 1602. In a second step, a backfilling space between optical elements 1602 may be filled in with a polymer material 1606, coplanar with top surface of the optical elements 1602. In some embodiments, coatings may be applied after backfilling with polymer material 1606 as described above. In a third step, individual components are singulated, resulting in gaps 1608 between the individual components. The individual components may be a larger size than original optical element 1602 which may be the proper dimension to mount within the housing of the optical device. The individual components may be removed from the tape 1604 after the are singulated as illustrated in Fig. 17. [0081] Importantly, the distance between the elements in the reconstructed wafer is substantially larger than in the original optical element 1602. The optical elements 1602 may be placed on a substrate 1604 such as a tape. Next the region between the optical elements may be back-filled with a polymer 1606 (e.g. hard plastic). The surface of the polymer 1606 may be co-planar with the surface of the optical element. Importantly, for optical elements, the polymer 1606 may block light from entering and/or exiting the optical elements 1602 and thus the co-planar configuration of the polymer 1606 allows the polymer not to block the light entering from the top of the element, for example from peripheral angles.

[0082] In some embodiments, it may be desirable to add certain coatings to the surface of the optical elements, including but not limited to: Opaque optical aperture (f- stop); Anti-reflection coating; Optical filter coatings (high-pass, low-pass, band-pass, etc); electrical circuit; and/or conductive layers for eye safety.

[0083] Next the reconstructed wafer may be singulated to form individual optical elements 1602 surrounded in the polymer material 1606, which may be now substantially larger than the original optical element 1602. Thus, the optical elements 1602 including the polymer material 1606 may be the right dimension to mount within the housing of the optical device as illustrated in Fig. 2. The polymer material 1606 may be mounted to directly contact the housing while the optical elements 1602 do not contact the housing.

[0084] Fig. 17 illustrate the resultant polymer packaged metasurface chip after the process of Fig. 16. As illustrated, the resultant final chip size 1702 including the polymer packaging is larger than the optical element/chip area 1704 which is only marginally larger than the optically active surface of the metasurface chip 1602. Thus, this saves chip space while still allowing the resultant metasurface chip size 1702 to be large enough to fit the opening of the housing of the optical module (e.g. see Fig. 2) while still conserving chip space. Thus, the metasurface chip 1602 may fit in the housing without wasted chip space which may make the process of manufacturing the metasurface chip 1602 less expensive. DOCTRINE OF EQUIVALENTS

[0085] While the above description contains many specific embodiments of the invention, these should not be construed as limitations on the scope of the invention, but rather as an example of one embodiment thereof. It is therefore to be understood that the present invention may be practiced in ways other than specifically described, without departing from the scope and spirit of the present invention. Thus, embodiments of the present invention should be considered in all respects as illustrative and not restrictive. Accordingly, the scope of the invention should be determined not by the embodiments illustrated, but by the appended claims and their equivalents.