[0001] This application claims priority to United States patent application serial number 12/580,017, filed October 15, 2009.

BACKGROUND OF THE INVENTION

Field of the Invention

[0002] The present invention generally relates to graphics processing and more specifically to rasterizing multiple primitives in parallel while preserving the order of the primitives.

Description of the Related Art

[0003] Conventional graphics processors have processed primitives at a rate of up to one triangle per clock while maintaining the applications programming interface (API) specified primitive order. Graphics primitives, such as triangles are received in an ordered stream for processing. The DirectX and OpenGL APIs require that the primitive order be maintained, that is to say, the primitives must be rendered in the order presented by the application program. This requirement ensures that intersecting primitives will be rendered deterministically to avoid the introduction of visual artifacts. Additionally, the primitive order must be maintained since the results of rendering a later primitive may be dependent on the state of the frame buffer resulting from rendering an earlier primitive, particularly when blending is used.

[0004] While many graphics processors have used parallelism to increase processing throughput, systems capable of rendering more than one triangle per clock while processing from a single API input stream typically do not maintain primitive ordering at full speed.

[0005] Accordingly, what is needed in the art is a system and method for exceeding a triangle per clock while maintaining API primitive ordering. SUMMARY OF THE INVENTION

[0006] A system and method for rendering graphics primitives in parallel maintains API primitive ordering and is capable of rendering multiple primitives per system clock. Multiple, independent geometry units perform geometry processing

concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of several primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives.

[0007] Various embodiments of a method of the invention for rendering primitives in parallel include receiving primitives in a first order, where the primitives are encoded as a list of vertex indices, and distributing primitive descriptors representing the primitives for parallel processing in object-space to produce multiple streams, each stream including object-space processed primitive descriptors. The multiple streams of object-space processed primitive descriptors are routed based on screen- space positions to produce a first stream of processed primitive descriptors representing primitives that intersect a first portion of a screen and a second stream of processed primitive descriptors representing primitives that intersect a second portion of the screen. The object-space processed primitive descriptors in the first stream are reordered to match the first order, producing a reordered first stream of object-space processed primitive descriptors. The object-space processed primitive descriptors in the second stream are reordered to match the first order, producing a reordered second stream of object-space processed primitive descriptors. The primitives that intersect the first portion of the screen, and are represented by the first stream of object-space processed primitive descriptors, and the primitives that intersect the second portion of the screen, and are represented by the second stream of object-space processed primitive descriptors are rasterized in parallel to produce rasterized pixels of an image.

[0008] Various embodiments of the invention include a system for rendering primitives in parallel. The system includes a processor that is configured to receive primitives in a first order where the primitives are encoded as a list of vertex indices, and distribute primitive descriptors that represent the primitives for parallel processing in object-space to produce multiple streams, each stream including object-space processed primitive descriptors. The processor is configured to route the multiple streams of object-space processed primitives based on screen-space positions to produce a first stream of processed primitive descriptors representing primitives that intersect a first portion of a screen and a second stream of processed primitive descriptors representing primitives that intersect a second portion of the screen. The processor is configured to reorder the object-space processed primitive descriptors in the first stream to match the first order, producing a reordered first stream of object- space processed primitive descriptors and reorder the object-space processed primitive descriptors in the second stream to match the first order, producing a reordered second stream of object-space processed primitive descriptors. The processor then rasterizes primitives that intersect the first portion of the screen, and are represented by the first stream of object-space processed primitive descriptors, and the primitives that intersect the second portion of the screen, and are represented by the second stream of object-space processed primitive descriptors in parallel to produce rasterized pixels of an image.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

[0010] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the present invention;

[0011] Figure 2 is a block diagram of a parallel processing subsystem for the computer system of Figure 1 , according to one embodiment of the present invention;

[0012] Figure 3A is a block diagram of a GPC within one of the PPUs of Figure 2, according to one embodiment of the present invention;

[0013] Figure 3B is a block diagram of a partition unit within one of the PPUs of Figure 2, according to one embodiment of the present invention; [0014] Figure 3C is a block diagram of a portion of the work distribution crossbar of Figure 3A, according to one embodiment of the present invention;

[0015] Figure 4 is a conceptual diagram of a graphics processing pipeline that one or more of the PPUs of Figure 2 can be configured to implement, according to one embodiment of the present invention; and

[0016] Figure 5 is a flow diagram of method steps for rendering primitives while maintaining API primitive ordering, according to one embodiment of the present invention.

DETAILED DESCRIPTION

[0017] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one of skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.

System Overview

[0018] Figure 1 is a block diagram illustrating a computer system 100 configured to implement one or more aspects of the present invention. Computer system 100 includes a central processing unit (CPU) 102 and a system memory 104

communicating via an interconnection path that may include a memory bridge 105. Memory bridge 105, which may be, e.g., a Northbridge chip, is connected via a bus or other communication path 106 (e.g., a HyperTransport link) to an I/O (input/output) bridge 107. I/O bridge 107, which may be, e.g., a Southbridge chip, receives user input from one or more user input devices 108 (e.g., keyboard, mouse) and forwards the input to CPU 102 via path 106 and memory bridge 105. A parallel processing subsystem 1 12 is coupled to memory bridge 105 via a bus or other communication path 1 13 (e.g., a PCI Express, Accelerated Graphics Port, or HyperTransport link); in one embodiment parallel processing subsystem 1 12 is a graphics subsystem that delivers pixels to a display device 1 10 (e.g., a conventional CRT or LCD based monitor). A system disk 1 14 is also connected to I/O bridge 107. A switch 1 16 provides connections between I/O bridge 107 and other components such as a network adapter 1 18 and various add-in cards 120 and 121 . Other components (not explicitly shown), including USB or other port connections, CD drives, DVD drives, film recording devices, and the like, may also be connected to I/O bridge 107.

Communication paths interconnecting the various components in Figure 1 may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s), and connections between different devices may use different protocols as is known in the art.

[0019] In one embodiment, the parallel processing subsystem 1 12 incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In another embodiment, the parallel processing subsystem 1 12 incorporates circuitry optimized for general purpose processing, while preserving the underlying computational architecture, described in greater detail herein. In yet another embodiment, the parallel processing subsystem 1 12 may be integrated with one or more other system elements, such as the memory bridge 105, CPU 102, and I/O bridge 107 to form a system on chip (SoC).

[0020] It will be appreciated that the system shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of CPUs 102, and the number of parallel processing subsystems 1 12, may be modified as desired. For instance, in some embodiments, system memory 104 is connected to CPU 102 directly rather than through a bridge, and other devices communicate with system memory 104 via memory bridge 105 and CPU 102. In other alternative topologies, parallel processing subsystem 1 12 is connected to I/O bridge 107 or directly to CPU 102, rather than to memory bridge 105. In still other embodiments, I/O bridge 107 and memory bridge 105 might be integrated into a single chip. Large embodiments may include two or more CPUs 102 and two or more parallel processing systems 1 12. The particular components shown herein are optional; for instance, any number of add-in cards or peripheral devices might be supported. In some embodiments, switch 1 16 is eliminated, and network adapter 1 18 and add-in cards 120, 121 connect directly to I/O bridge 107. [0021] Figure 2 illustrates a parallel processing subsystem 1 12, according to one embodiment of the present invention. As shown, parallel processing subsystem 1 12 includes one or more parallel processing units (PPUs) 202, each of which is coupled to a local parallel processing (PP) memory 204. In general, a parallel processing subsystem includes a number U of PPUs, where U≥ 1 . (Herein, multiple instances of like objects are denoted with reference numbers identifying the object and

parenthetical numbers identifying the instance where needed.) PPUs 202 and parallel processing memories 204 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or memory devices, or in any other technically feasible fashion.

[0022] Referring again to Figure 1 , in some embodiments, some or all of PPUs 202 in parallel processing subsystem 1 12 are graphics processors with rendering pipelines that can be configured to perform various tasks related to generating pixel data from graphics data supplied by CPU 102 and/or system memory 104 via memory bridge 105 and bus 1 13, interacting with local parallel processing memory 204 (which can be used as graphics memory including, e.g., a conventional frame buffer) to store and update pixel data, delivering pixel data to display device 1 10, and the like. In some embodiments, parallel processing subsystem 1 12 may include one or more PPUs 202 that operate as graphics processors and one or more other PPUs 202 that are used for general-purpose computations. The PPUs may be identical or different, and each PPU may have its own dedicated parallel processing memory device(s) or no dedicated parallel processing memory device(s). One or more PPUs 202 may output data to display device 1 10 or each PPU 202 may output data to one or more display devices 1 10.

[0023] In operation, CPU 102 is the master processor of computer system 100, controlling and coordinating operations of other system components. In particular, CPU 102 issues commands that control the operation of PPUs 202. In some embodiments, CPU 102 writes a stream of commands for each PPU 202 to a pushbuffer (not explicitly shown in either Figure 1 or Figure 2) that may be located in system memory 104, parallel processing memory 204, or another storage location accessible to both CPU 102 and PPU 202. PPU 202 reads the command stream from the pushbuffer and then executes commands asynchronously relative to the operation of CPU 102. [0024] Referring back now to Figure 2, each PPU 202 includes an I/O (input/output) unit 205 that communicates with the rest of computer system 100 via communication path 1 13, which connects to memory bridge 105 (or, in one alternative embodiment, directly to CPU 102). The connection of PPU 202 to the rest of computer system 100 may also be varied. In some embodiments, parallel processing subsystem 1 12 is implemented as an add-in card that can be inserted into an expansion slot of computer system 100. In other embodiments, a PPU 202 can be integrated on a single chip with a bus bridge, such as memory bridge 105 or I/O bridge 107. In still other embodiments, some or all elements of PPU 202 may be integrated on a single chip with CPU 102.

[0025] In one embodiment, communication path 1 13 is a PCI-EXPRESS link, in which dedicated lanes are allocated to each PPU 202, as is known in the art. Other communication paths may also be used. An I/O unit 205 generates packets (or other signals) for transmission on communication path 1 13 and also receives all incoming packets (or other signals) from communication path 1 13, directing the incoming packets to appropriate components of PPU 202. For example, commands related to processing tasks may be directed to a host interface 206, while commands related to memory operations (e.g., reading from or writing to parallel processing memory 204) may be directed to a memory crossbar unit 210. Host interface 206 reads each pushbuffer and outputs the work specified by the pushbuffer to a front end 212.

[0026] Each PPU 202 advantageously implements a highly parallel processing architecture. As shown in detail, PPU 202(0) includes a processing cluster array 230 that includes a number C of general processing clusters (GPCs) 208, where C > 1 . Each GPC 208 is capable of executing a large number (e.g., hundreds or thousands) of threads concurrently, where each thread is an instance of a program. In various applications, different GPCs 208 may be allocated for processing different types of programs or for performing different types of computations. For example, in a graphics application, a first set of GPCs 208 may be allocated to perform tessellation operations and to produce primitive topologies for patches, and a second set of GPCs 208 may be allocated to perform tessellation shading to evaluate patch parameters for the primitive topologies and to determine vertex positions and other per-vertex attributes. The allocation of GPCs 208 may vary dependent on the workload arising for each type of program or computation. [0027] GPCs 208 receive processing tasks to be executed via a primitive distribution unit 200, which receives commands defining processing tasks from front end unit 212. Processing tasks include indices of data to be processed, e.g., surface (patch) data, primitive data, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). Primitive distribution unit 200 may be configured to fetch the indices corresponding to the data, or primitive distribution unit 200 may receive the indices from front end 212. Front end 212 ensures that GPCs 208 are configured to a valid state before the processing specified by the pushbuffers is initiated.

[0028] When PPU 202 is used for graphics processing, for example, the

processing workload for each patch is divided into approximately equal sized tasks to enable distribution of the tessellation processing to multiple GPCs 208. A primitive distribution unit 200 may be configured to produce tasks at a frequency capable of providing tasks to multiple GPCs 208 for processing. In some embodiments of the present invention, portions of GPCs 208 are configured to perform different types of processing. For example a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading in screen-space to produce a rendered image. Intermediate data produced by GPCs 208, such vertex attributes, may be stored in buffers to allow the intermediate data to be transmitted between GPCs 208 for further processing.

[0029] Memory interface 214 includes a number D of partition units 215 that are each directly coupled to a portion of parallel processing memory 204, where D > 1 . As shown, the number of partition units 215 generally equals the number of DRAM 220. In other embodiments, the number of partition units 215 may not equal the number of memory devices. Persons skilled in the art will appreciate that DRAM 220 may be replaced with other suitable storage devices and can be of generally conventional design. A detailed description is therefore omitted. Render targets, such as frame buffers or texture maps may be stored across DRAMs 220, allowing partition units 215 to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processing memory 204. [0030] Any one of GPCs 208 may process data to be written to any of the DRAMs 220 within parallel processing memory 204. Crossbar unit 210 is configured to route the output of each GPC 208 to the input of any partition unit 215 or to another GPC 208 for further processing. GPCs 208 communicate with memory interface 214 through crossbar unit 210 to read from or write to various external memory devices. In one embodiment, crossbar unit 210 has a connection to memory interface 214 to communicate with I/O unit 205, as well as a connection to local parallel processing memory 204, thereby enabling the processing cores within the different GPCs 208 to communicate with system memory 104 or other memory that is not local to PPU 202. In the embodiment shown in Figure 2, crossbar unit 210 is directly connected with I/O unit 205. Crossbar unit 210 may use virtual channels to separate traffic streams between the GPCs 208 and partition units 215.

[0031] Again, GPCs 208 can be programmed to execute processing tasks relating to a wide variety of applications, including but not limited to, linear and nonlinear data transforms, filtering of video and/or audio data, modeling operations (e.g., applying laws of physics to determine position, velocity and other attributes of objects), image rendering operations (e.g., tessellation shader, vertex shader, geometry shader, and/or pixel shader programs), and so on. PPUs 202 may transfer data from system memory 104 and/or local parallel processing memories 204 into internal (on-chip) memory, process the data, and write result data back to system memory 104 and/or local parallel processing memories 204, where such data can be accessed by other system components, including CPU 102 or another parallel processing subsystem 1 12.

[0032] A PPU 202 may be provided with any amount of local parallel processing memory 204, including no local memory, and may use local memory and system memory in any combination. For instance, a PPU 202 can be a graphics processor in a unified memory architecture (UMA) embodiment. In such embodiments, little or no dedicated graphics (parallel processing) memory would be provided, and PPU 202 would use system memory exclusively or almost exclusively. In UMA embodiments, a PPU 202 may be integrated into a bridge chip or processor chip or provided as a discrete chip with a high-speed link (e.g., PCI-EXPRESS) connecting the PPU 202 to system memory via a bridge chip or other communication means. [0033] As noted above, any number of PPUs 202 can be included in a parallel processing subsystem 1 12. For instance, multiple PPUs 202 can be provided on a single add-in card, or multiple add-in cards can be connected to communication path 1 13, or one or more of PPUs 202 can be integrated into a bridge chip. PPUs 202 in a multi-PPU system may be identical to or different from one another. For instance, different PPUs 202 might have different numbers of processing cores, different amounts of local parallel processing memory, and so on. Where multiple PPUs 202 are present, those PPUs may be operated in parallel to process data at a higher throughput than is possible with a single PPU 202. Systems incorporating one or more PPUs 202 may be implemented in a variety of configurations and form factors, including desktop, laptop, or handheld personal computers, servers, workstations, game consoles, embedded systems, and the like.

Processing Cluster Array Overview

[0034] Figure 3A is a block diagram of a GPC 208 within one of the PPUs 202 of Figure 2, according to one embodiment of the present invention. Each GPC 208 may be configured to execute a large number of threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In some embodiments, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each one of the GPCs 208. Unlike a SIMD execution regime, where all processing engines typically execute identical instructions, SIMT execution allows different threads to more readily follow divergent execution paths through a given thread program. Persons skilled in the art will understand that a SIMD processing regime represents a functional subset of a SIMT processing regime.

[0035] The primitive distribution unit 200 distributes processing tasks to each TPC 310 within the GPCs 208 via crossbar unit 210. In particular the primitive distribution unit 200 distributes primitives for object-space (geometry) processing by the TPCs 310. A pipeline manager 305 within each GPC 208 distributes the object-space processing tasks to streaming multiprocessors within each of the TPCs 310. Pipeline manager 305 may also be configured to control a work distribution crossbar interface 330 to distribute state parameters and commands to the TPCs 310 for object-space processing and screen-space processing.

[0036] In one embodiment, each GPC 208 includes a number M of TPCs 310, where M>1 , each TPC 310 configured to process one or more thread groups. Also, each TPC 310 advantageously includes an identical set of functional execution units (e.g., arithmetic logic units, and load-store units, and the like) that may be pipelined, allowing a new instruction to be issued before a previous instruction has finished, as is known in the art. Any combination of functional execution units may be provided. In one embodiment, the functional units support a variety of operations including integer and floating point arithmetic (e.g., addition and multiplication), comparison operations, Boolean operations (AND, OR, XOR), bit-shifting, and computation of various algebraic functions (e.g., planar interpolation, trigonometric, exponential, and logarithmic functions, etc.); and the same functional-unit hardware can be leveraged to perform different operations.

[0037] The series of instructions transmitted to a particular GPC 208 constitutes a thread, as previously defined herein, and the collection of a certain number of concurrently executing threads across the parallel processing engines (not shown) within an TPC 310 is referred to herein as a "warp" or "thread group." As used herein, a "thread group" refers to a group of threads concurrently executing the same program on different input data, with one thread of the group being assigned to a different processing engine within a TPC 310. A thread group may include fewer threads than the number of processing engines within the TPC 310, in which case some processing engines will be idle during cycles when that thread group is being processed. A thread group may also include more threads than the number of processing engines within the TPC 310, in which case processing will take place over multiple clock cycles. Since each TPC 310 can support up to G thread groups concurrently, it follows that up to G ^* M thread groups can be executing in GPC 208 at any given time.

[0038] Additionally, a plurality of related thread groups may be active (in different phases of execution) at the same time within a TPC 310. This collection of thread groups is referred to herein as a "cooperative thread array" ("CTA") or "thread array." The size of a particular CTA is equal to m ^* k, where k is the number of concurrently executing threads in a thread group and is typically an integer multiple of the number of parallel processing engines within the TPC 310, and m is the number of thread groups simultaneously active within the TPC 310. The size of a CTA is generally determined by the programmer and the amount of hardware resources, such as memory or registers, available to the CTA.

[0039] Each TPC 310 contains an L1 cache 335 or uses space in a corresponding L1 cache outside of the TPC 310 that is used to perform load and store operations. Each TPC 310 also has access to L2 caches within the partition units 215 that are shared among all GPCs 208 and may be used to transfer data produced during object-space primitive processing to TPCs 310 to perform screen-space primitive processing. Finally, TPCs 310 also have access to off-chip "global" memory, which can include, e.g., parallel processing memory 204 and/or system memory 104. It is to be understood that any memory external to PPU 202 may be used as global memory. Additionally, an L1 .5 cache may be included within the GPC 208, configured to receive and hold data fetched from memory via memory interface 214 requested by TPC 310, including instructions, uniform data, and constant data, and provide the requested data to TPC 310. Embodiments having multiple TPCs 310 in GPC 208 beneficially share common instructions and data cached in an L1 .5 cache.

[0040] Each GPC 208 includes a network interface 328 that may be configured to map virtual addresses into physical addresses. In other embodiments, the mapping of virtual addresses into physical addresses may be performed within the memory interface 214. A set of page table entries (PTEs) is used to map a virtual address to a physical address of a tile and optionally a cache line index. Address translation lookaside buffers (TLB) or caches which may reside within a TPC 310 or the L1 cache 335 or GPC 208. The physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. The cache line index may be used to determine whether or not a request for a cache line is a hit or miss.

[0041] A GPC 208 may be configured such that each TPC 310 includes a texture unit 315 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering the texture data. Texture data is read from a texture L1 cache or in some embodiments from the L1 cache 335 within TPC 310 and is fetched from an L2 cache, parallel processing memory 204, or system memory 104, as needed.

[0042] As previously explained, TPCs 310 receive batches of primitives and perform object-space processing. Each TPC 310 outputs a stream of object-space processed primitive descriptors to the work distribution crossbar interface 330 in order to redistribute the object-space processed primitive descriptors via the work distribution crossbar fabric 334 to one or more GPCs 208 for screen-space

processing. A primitive descriptor includes the primitive type (triangle strip, triangle mesh, line, and the like), flags, and indices of vertices. The object-space processing includes one or more of vertex shading, tessellation shading, and geometry shading. The screen-space processing is rasterization of the primitives, and may include one or more of scan conversion, shading, depth/stencil operations, and blending. TPC 310 may also output the object-space processed primitive data, i.e., vertex attributes, for storage in an L2 cache, parallel processing memory 204, or system memory 104 via crossbar unit 210.

[0043] A preROP (pre-raster operations) 324 is configured to receive data (screen- space processed primitives) from TPC 310, direct data to ROP units within partition units 215, and perform optimizations for color blending, organize pixel color data, and perform address translations.

[0044] It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units, e.g., TPCs 310, setup units 321 , rasterizers 322, or preROPs 324 may be included within a GPC 208. Further, while only one GPC 208 is shown, a PPU 202 may include any number of GPCs 208 that are advantageously functionally similar to one another so that execution behavior does not depend on which GPC 208 receives a particular processing task. Further, each GPC 208 advantageously operates independently of other GPCs 208 using separate and distinct processing units, L1 caches, and so on. Distributed Object-space Processing

[0045] The application program presents graphics primitives to the parallel processing subsystem 1 12 serially via the host interface 206. The graphics primitives may be in the form of indexed lists, stored in memory. A rendering "drawcall" is sent serially over the host interface 206 and each drawcall may reference a large list of primitives to be rendered. An important design consideration is the granularity of distributing the primitives to the TPCs 310 for object-space processing. For best load balancing, a fine-grained distribution of individual primitives to the TPCs 310 is desired. However, since primitives are generally encoded as indexed triangle meshes or triangle strips, with vertices shared among multiple triangles, it is advantageous to distribute primitives in multiple-primitive batches, such that triangles that share a vertex are generally in the same batch.

[0046] In some embodiments the primitive distribution unit 200 reads a buffer containing indices of vertices in an associated vertex buffer. The indices implicitly define primitives and point to vertex data stored in the vertex buffer. The primitive distribution unit 200 groups the primitives represented by the indices of vertices into batches for distribution to the TPCs 310. The batch encodes a number of sequential primitives represented as a set of vertex indices and primitive topology information, e.g., a list of primitives (either points, lines, triangles, or patches) that reference indices in the set of vertex indices. Batches may include 32 vertex pointers, which is large enough to benefit from vertex reuse, but small enough to balance the parallel geometry processing workload across the TPCs 310 while minimizing buffering needed to store the primitives for processing. The batches may be assigned to the TPCs 310 in the system in a round-robin fashion, e.g., TPCs 310 in a first GPC 208, TPCs 310 in a second GPC 208, and so on or a first TPC 310 in each of the GPCs 208, a second TPC 310 in each of the GPCs 208, and so on, or based on the current loading conditions for object-space primitive processing. The object-space primitive processing comprises geometry processing, including world-to-screen-space transformation, clipping, culling, and vertex shading operations. The result of the parallel object-space primitive processing performed by the TPCs 310 is batches of graphics primitive descriptors that encode transformed vertices defining points, lines, and triangles. The primitive descriptor contains information about the geometric primitive necessary for rendering the pixels covered by the primitives: type of primitive (point, line, triangle), vertex indices that point to buffers storing the vertex attributes, control flags.

[0047] The vertex attributes are transferred from the TPCs 310 to the distributed L2 cache via the network interface 328. The vertex attributes may then be read by any of the TPCs 310 that are configured to perform rasterization of the object-space processed primitives.

Distributed Screen-Space Processing

[0048] Primitive setup and rasterization are also parallelized over the GPCs 208. Each GPC 208 includes a setup 321 , rasterizer 322, and preROP 324. Each GPC 208 is responsible for processing a portion of the screen-space. It is desirable to distribute rasterization in screen-space portions so that shading, texturing, and frame buffer accesses have locality and rasterization of the primitives in each portion may be performed in parallel and independently.

[0049] The object-space processed primitive descriptors are routed through the work distribution crossbar fabric to GPCs 208 by the work distribution crossbar interface 330 based on the portion of the image that each object-space processed primitive affects. To make this assignment, the image, called the render target, is subdivided into small "screen tiles," and the screen tiles are partitioned into non- overlapping sets that cover the image. A different GPC 208 is assigned to each screen tile set. In some embodiments each screen tile set includes statically mapped 16x16-pixel regions and GPC 208 performs setup and rasterization for up to one triangle per clock. A given GPC 208 is configured to rasterize each primitive that covers at least one pixel within the portion of the screen-space assigned to the given GPC 208. Large primitives may be rasterized by every GPC 208 while a small primitive may only be rasterized by one GPC 208.

[0050] Setup 321 forwards the edge and depth plane equations for object-space processed primitives to the rasterizer 322. Setup 321 stores partial plane equations in a buffer for subsequent retrieval by the fragment shader, when interpolating other attributes. The rasterizer 322 associated with each setup 321 iterates within the primitive bounding box, guided by the edge equations, to identify tiles with sample coverage. The rasterizer 322 contains a coarse stage, which identifies large tiles that are likely to contain sample coverage and a fine stage, which tests sample locations against edge equations. The rasterizer 322 uses knowledge of the GPC screen tile mapping to skip over tiles assigned for processing by other GPCs 208 in zero time. In some embodiments, a hierarchical Z unit which can rapidly reject tiles that are known to lie behind occluding geometry is included between the two rasterizer stages.

[0051] The combination of the work distribution crossbar interface 330 and work distribution crossbar fabric 334 implements a distributed sorting structure that routes primitive data between the GPCs 208. The work distribution crossbar interface 330 routes the parallel streams of object-space processed primitive descriptors from the TPCs 310 performing object-space processing into parallel, ordered streams of primitive descriptors for the GPCs 208 performing screen-space processing via the work distribution crossbar fabric 334. Multiple work distribution crossbar interfaces 330 are coupled together through the work distribution crossbar fabric 334 in order to support multiple GPCs 208. Each work distribution crossbar interface 330 receives a stream of object-space processed primitive descriptors from each TPC 310 that performs object-space processing and routes each object-space processed primitive descriptor to one or more GPCs 208 for screen-space primitive processing via the work distribution crossbar fabric 334. Each work distribution crossbar interface 330 then reorders the primitive descriptors received by each GPC 208 that will perform the screen-space processing to match the API primitive ordering. Since each GPC 208 does not process every primitive, some of the primitive descriptor streams reordered by the GPCs 208 will not include every primitive descriptor that is present in the API primitive ordering. A reordered stream is considered to match the API primitive ordering when the primitive descriptors that are present in the reordered stream are in the same order that the same primitive descriptors appear in the API primitive ordering.

[0052] Although the object-space processed primitives are reordered by the work distribution crossbar interface 330 into the API primitive order going to each rasterizer 322, the actual processing of the primitives is physically distributed. That is, there is no single point after primitives pass through the primitive distribution unit 200 through which all primitives flow. Importantly, this distributed implementation of primitive distribution permits the system to distribute multiple primitives per clock, up to a peak rate of a primitive per clock at each rasterizer 322 within a GPC 208. Each setup 321 receives a stream of processed primitives that possibly can affect one or more of its screen tiles. The rasterizers 322 proceed to generate pixel or sample data for their assigned tile sets. Each rasterizer 322 operates independently of the others. There is no need for the rasterizers 322 to stay synchronized with each other, since each one operates on its own separate subset of the image, and thus they are non-interfering.

[0053] The rasterized and then shaded fragment data produced by a rasterizer 322 and TPC 310 is collected by the pipeline manager 305 and output to the preROP 324. PreROP 324 is configured to receive the shaded fragment data (screen-space processed primitives) from TPC 310, direct the shaded fragment data to the ROP units within partition units 215, and perform optimizations for color blending, organize pixel color data, and perform address translations.

[0054] The overall primitive processing rate may reach up to C triangles per clock, where C is the number of GPCs 208. Therefore the primitive descriptors need to be conveyed to the GPCs 208 through the work distribution crossbar fabric 334 by the work distribution crossbar interface 330 at an aggregate rate of C triangles per clock— C ^* the input rate of an individual GPC 208. Because the parallel processing subsystem 1 12 is scalable, systems with higher performance may be built by increasing the number of GPCs 208 and/or TPCs 310 in the parallel processing subsystem 1 12.

[0055] Figure 3B is a block diagram of a partition unit 215 within one of the PPUs 202 of Figure 2, according to one embodiment of the present invention. As shown, partition unit 215 includes a L2 cache 350, a frame buffer (FB) DRAM interface 355, and a raster operations unit (ROP) 360. L2 cache 350 is a read/write cache that is configured to perform load and store operations received from crossbar unit 210 and ROP 360. Read misses and urgent writeback requests are output by L2 cache 350 to FB DRAM interface 355 for processing. Dirty updates are also sent to FB 355 for opportunistic processing. FB 355 interfaces directly with DRAM 220, outputting read and write requests and receiving data read from DRAM 220.

[0056] In graphics applications, ROP 360 is a processing unit that performs raster operations, such as stencil, z test, blending, and the like, and outputs pixel data as processed graphics data for storage in graphics memory. In some embodiments of the present invention, ROP 360 is included within each GPC 208 instead of partition unit 215, and pixel read and write requests are transmitted over crossbar unit 210 instead of pixel fragment data.

[0057] The processed graphics data may be displayed on display device 1 10 or routed for further processing by CPU 102 or by one of the processing entities within parallel processing subsystem 1 12. Each partition unit 215 includes a ROP 360 in order to distribute processing of the raster operations. In some embodiments, ROP 360 may be configured to compress z or color data that is written to memory and decompress z or color data that is read from memory.

[0058] Persons skilled in the art will understand that the architecture described in Figures 1 , 2, 3A, and 3B in no way limits the scope of the present invention and that the techniques taught herein may be implemented on any properly configured processing unit, including, without limitation, one or more CPUs, one or more multi- core CPUs, one or more PPUs 202, one or more GPCs 208, one or more graphics or special purpose processing units, or the like, without departing the scope of the present invention.

[0059] Figure 3C is a block diagram of portions of the GPCs 208 including the work distribution crossbar interface 330 of Figure 3A, according to one embodiment of the present invention. The work distribution unit 330 includes a set of WWDXes 340 which each are coupled to one of the TPCs 310 to receive the object-space primitive descriptors, primitive bounding boxes, attribute buffer addresses, and end of batch flags from the TPCs 310 within a GPC 208. The TPC 310 computes a primitive bounding box for each primitive descriptor and the WWDX 340 receiving the bounding box compares it with the screen-space tiled mapping of the GPCs 208. A primitive bounding box contains the minimum and maximum X and Y screen-space dimensions for the smallest rectangle that completely contains the primitive. Based on the bounding box size and position, the WWDX 340 determines which GPCs 208 might need to process the primitive by intersecting the screen tile set for each GPC 208 with the bounding box. The WWDX 340 sets bits corresponding to the particular GPCs 208 that should receive the primitive in a GPC (distribution) mask. Small primitives (i.e., primitives that affect only one or a few pixels) will generally affect only one screen tile, and thus will be sent to a single GPC 208. Larger primitives, which affect several screen tiles, will be sent to multiple GPCs 208. In the limit, with small primitives, when there are C GPCs 208, the system can process C different primitives concurrently.

[0060] The primitive descriptors for a single batch that is processed by a particular TPC 310 are processed and output by the TPC 310 in the API primitive order.

However, the different TPCs 310 may process the batches at different rates so that the batches are output from the TPCs 310 in an order that does not match the API primitive order at a batch level. Therefore, an aggregation unit 345 reorders each batch that is received from the WWDXes 340 to match the API primitive order.

[0061] The aggregation unit 345 is configured to merge two or more primitive descriptor streams output by the WWDXes 340 and produce a single primitive descriptor stream that is routed by the work distribution crossbar fabric 334 to the GPCs 208 for object-space processing. In some embodiments, the aggregation unit 345 is omitted and the multiple streams of primitive descriptors are combined and output to the work distribution crossbar fabric 334 by the WWDXes 340 or the multiple streams of primitive descriptors are output directly (combined or not) to the work distribution crossbar fabric 334. The combining of the multiple streams may be performed in a variety of ways without regard to matching the API primitive order.

[0062] API primitive order information is provided to the aggregation unit 345 by the pipeline manager 305. When the primitive distribution unit 200 sends batches of primitives to TPCs 310 via the pipeline manager 305, the pipeline manager 305 outputs a sequential order of TPCs 310 that received the batches, so that the aggregation unit 345 within each work distribution crossbar interface 330 can reorder the object-space primitives to match the API primitive order and produce an ordered primitive stream for output to the GPCs 208 for screen-space processing. The pipeline manager 305 may also receive a sequential order of GPCs 208 that received the batches from the primitive distribution unit 200 and output the sequential order of GPCs 208 to the primitive order unit 342, so that the aggregation unit 345 and/or SWDX 346 within each work distribution crossbar interface 330 can reorder the object-space primitives that are received by each GPC 208 to match the API primitive order and produce an ordered primitive stream for output to the setup 321 for screen- space processing. [0063] The aggregation unit 345 performs the reordering on outgoing primitive descriptors by accepting primitive descriptors from the TPC 310 corresponding to a current TPC identifier (based on the sequential order provided by the pipeline manager 305) until an end of batch flag is detected in the primitive descriptor stream. The end of batch flag may be a single bit that is set in the last primitive descriptor in each batch and cleared in any other primitive descriptors in the batch. When an end of batch flag is detected, the next TPC identifier in the sequential order becomes the current TPC identifier. The aggregation unit 345 outputs a stream of object-space processed primitive descriptors that is reordered based on the TPC identifiers. The stream output by each individual GPC 208 matches the API primitive order. However, each receiving GPC 208 (configured to perform screen-space processing) may receive primitive descriptors from one or more outgoing streams transmitted by GPCs 208 (configured to perform object-space processing). On the receiving side of the work distribution crossbar fabric 334, the sequence of GPC identifiers may be used by each SWDX 346 to reorder the batches received from different GPCs 208 so that each setup 321 receives an ordered list of the object-space processed primitive descriptors for rasterization.

[0064] The outgoing ordered stream of object-space processed primitives output by an aggregation unit 345 over the dedicated work distribution crossbar fabric 334 includes the following primitive data for each primitive: an attribute buffer address, a primitive descriptor, a GPC identifier, a TPC identifier, and an end of batch flag. The GPC identifier indicates the GPC 208 that performed the object-space processing. Likewise, the TPC identifier indicates the TPC 310 that performed the object-space processing. The attribute buffer address is a pointer to a location in memory where the attribute data for the primitive is stored. When many attributes are associated with each primitive, it is advantageous to carry a pointer to the attribute data through the work distribution crossbar interface 330 and work distribution crossbar 334 rather than carrying the actual attribute data. When the WWDXes 340 output multiple primitive streams directly to the work distribution crossbar fabric 334, i.e., the aggregation unit 345 is omitted, the primitive stream includes the GPC mask, a TPC identifier, a GPC identifier, an attribute buffer address, a primitive descriptor, and an end of batch flag. [0065] The work distribution crossbar fabric 334 routes primitive data for one primitive from a GPC 208 configured to perform object-space processing to one or more GPCs 208 configured to perform screen-space processing based on the GPC mask. In some embodiments each primitive is broadcast to each GPC 208 according to the GPC mask in a single clock cycle. In other embodiments, a primitive is output to only one GPC 208 in a clock cycle so that a primitive that is routed to multiple GPCs 208 is output to each one of the different GPCs 208 in a separate clock cycle. The work distribution crossbar fabric 334 may be configured to use a credit/debit scheme to transmit primitive data between the GPCs 208. A receiving GPC 208 outputs credits indicating the amount of primitive data that can be accepted. The work distribution crossbar fabric 334 may also be configured to arbitrate between two or more primitives that are routed to the same GPC 208 in a clock cycle when a GPC 208 can only accept one primitive per clock cycle.

[0066] Each screen-space unit 336 has a GPC reorder buffer 344 that receives and stores the primitive data (excluding the GPC mask) output by the work distribution crossbar fabric 334. The GPC reorder buffer may be implemented as a multithreaded FIFO for storing the primitive data with one thread per object-space GPC 208. In other embodiments separate FIFOs may be used for each object-space GPC 208. Primitive data are placed in the appropriate thread, based on the GPC identifier, as the primitives are received via the work distribution crossbar fabric 334. In embodiments that omit the aggregation unit 345, primitive data are placed in the appropriate thread, based on the TPC identifier (and the GPC identifier if the TPC identifiers are not unique across the different GPCs 208), as the primitive data are received via the work distribution crossbar fabric 334.

[0067] The SWDX 346 removes the primitive descriptors, attribute buffer addresses, and end of batch flags from the multithreaded FIFO in the order specified by the sequential GPC identifier order provided by the pipeline manager 305 and pushes the primitive descriptors and attribute buffer addresses into an output FIFO. The SWDX 346 starts reading primitive descriptors, attribute buffer addresses, and end of batch flags from the FIFO thread for the first GPC that received a batch of primitive data. When the SWDX 346 sees the end of batch flag set in that FIFO thread, the SWDX 346 starts reading from the FIFO thread of the next GPC 208 that received a batch of primitives for object-space processing, and so forth. Thus, the SWDX 346 pulls primitive descriptors and attribute buffer addresses out of the multithreaded FIFO in the API primitive order, and pushes them into the output FIFO within the SWDX 346 in the API primitive order. The setup unit 321 in the respective GPC 208 pops the primitive descriptors and attribute buffer addresses from the output FIFO for screen-space processing. The output FIFO should be deep enough so that the setups 321 are not starved when many primitives are sent to the same setup 321 . In some embodiments each rasterizer 322 can process up to a primitive per clock, matching the rate at which primitive descriptors are output by the setup unit 321 .

[0068] The assignment of screen tile sets to the rasterizers distributes the rasterization workload. The screen tiles are NxM rectangles of samples within the render target. The choice of tile size is a tradeoff between load balancing, which improves with smaller screen tiles, and overhead, which improves with larger screen tiles. Overhead can take the form of primitives that need to be processed by multiple GPCs 208 because the tile size is too small or reduced texture locality. In one embodiment, the tile size is 16x16 pixels. The screen tiles are assigned to rasterizers 322 in an interleaved fashion to balance the workload across the rasterizers 322. For example, the upper-left corner tiles of the render target might be assigned to four rasterizers 322 corresponding to digits 0, 1 , 2, and 3, in the following fashion:

First tile row: 0 1 2 3 0 1 2 3 0 1 2 3 ...

Second tile row: 1 2 3 0 1 2 3 0 1 2 3 0 ...

Third tile row: 2 3 0 1 2 3 0 1 2 3 0 1 ...

Fourth tile row: 3 0 1 2 3 0 1 2 3 0 1 2 ...

The exact pattern of tile assignments may be specified by a table or calculated algorithmically, and may vary between different systems. One embodiment uses a skewed, interleaved arrangement, as shown above, with the property that if a primitive bounding box is at least C (C = number of rasterizers 322) screen tiles wide or tall, the primitive must necessarily be distributed to all rasterizers 322. This characteristic may be used to simplify the calculation of the GPC mask.

Graphics Pipeline Architecture

[0069] Figure 4 is a conceptual diagram of a graphics processing pipeline 400, that one or more of the PPUs 202 of Figure 2 can be configured to implement, according to one embodiment of the present invention. For example, one of the TPCs 310 may be configured to perform the functions of one or more of a geometry processing unit 425, and a fragment processing unit 460. The functions of primitive distributer 420, rasterizer 455, and raster operations unit 465 may also be performed by other processing engines within a GPC 208 and a corresponding partition unit 215.

Alternately, graphics processing pipeline 400 may be implemented using dedicated processing units for one or more functions.

[0070] Vertex data for high-order surfaces, primitives, and the like may be stored in in L1 cache 335, parallel processing memory 204, or system memory 104 and accessed as needed to render the primitives. The functions of the primitive distributer 420 may be performed by the primitive distribution unit 200. Primitive distributer 420 receives pointers to primitive index lists stored in memory. The entries in these index lists point into lists of vertex attributes (vertex buffers), also stored in memory.

Because primitives are stored compactly and many primitives can be passed to the primitive distributer 420 in a single draw call, indexed primitive lists and vertex buffers are the most efficient way to convey geometry to the graphics pipeline 400. The front end 212 may be configured to store legacy inline and immediate mode vertices in vertex buffers, so the primitive assembler 420 only has to deal with this one, efficient type of primitive input data, namely primitive index lists. In other embodiments the primitive distributer 420 may receive the vertex data instead of pointers to primitive index lists.

[0071] In some embodiments, the GPCs 208 are configured to perform tessellation processing prior to geometry processing. In those embodiments the primitive distributer 420 distributes batches of primitives for tessellation processing to multiple TPCs 310 and streams of tessellated primitive batches are produced. The API primitive ordering may be restored prior to object-space processing of the primitives by either using the same TPCs 208 to perform the object-space processing as was used to perform the tessellation. Alternatively, the primitive batches may be reordered to match the API primitive order after tessellation so that batches of primitives for object-space processing are generated and distributed in API primitive order.

[0072] Primitive distributer 420 dices the index list into self-contained batches of indices specifying up to J vertices and K primitives, such that each vertex in a strip, after the first two, specifies a new triangle. In some embodiments, J is 32, K is 30, and batches may occupy from one to four 32B data packets, depending on the number and type of primitive and contain the following information: indices of vertices in the vertex buffer and topology information (which vertices in the batch comprise each primitive). Importantly, the primitive distributer 420 works entirely with primitive indices— it does not touch the vertex data itself. The vertex data is later fetched by the TPC 310 assigned for vertex shading.

[0073] The bulk of the data transferred (via indices) between geometry processing and rasterization is vertex attributes. These are the parameters calculated for each vertex, such as x, y, z position, texture coordinates, vertex colors, and other shader parameters. Some parameters, such as x,y, z (position) are needed by the rasterizer to determine primitive coverage and depth values. Other attributes are needed, as interpolated values, by the fragment shader. The number and type of attributes depends on the vertex and fragment shaders.

[0074] Vertex attributes need to be buffered from the time they are calculated by the TPCs 310 doing object-space processing until they are needed by setup 322 or the fragment processing unit 460. The amount of data that needs to be buffered is highly variable, depending on the number and type of attributes per vertex. The amount of data may be near zero for full-screen primitives and the amount of data may be extremely high in high primitive rate cases. The amount of data may also be highly variable per GPC 208 when a large number of small primitives fall onto a single screen tile.

[0075] Because of these potentially large and highly variable buffering

requirements, it may be advantageous to store vertex attributes in the L2 cache 350. The L2 cache 350 is a large, pooled resource that is used for many purposes:

caching textures, caching rendered pixels, and caching primitive attributes. In high triangle rate cases a greater amount of attribute buffering is needed, so the bulk of the L2 cache 350 may be used to cache attribute data instead of texture data. When requirements for attribute buffering are low, the L2 cache 350 may be used primarily for caching texture data.

[0076] Each TPC 310 performing object-space processing is provided with a fixed size linear buffer that is virtually addressed and cacheable. The addresses used to access these linear buffers wrap, so the linear buffers are actually circular FIFO (first- in, first-out) buffers. As TPCs 310 stream vertex attributes into the circular buffers, the TPCs 310 provide indices for entries written to the work distribution crossbar interface 330, which are conveyed to the GPCs 208 performing the screen-space processing. GPCs 208 that need to read circular buffer entries (CBEs) do so at two points: setup and fragment shader interpolation. Entries that are unneeded by a GPC 208 are skipped— not read by the GPC 208, while other entries may be read by multiple GPCs 208.

[0077] Because virtual addressing is used for the circular buffers, the full circular buffer may always be allocated, but only cache lines storing valid data need be resident in the L2 cache 350. When CBEs are written to the L2 cache 350, the cache line may be marked with "no-evict" status, so the cache line storing attribute data will not be flushed from the L2 cache 350. The work distribution crossbar interface 330 also has the task of freeing CBEs when the GPCs 208 are finished with them. To achieve this, the rasterizers 322 track the CBEs through the screen-space processing and signals the work distribution crossbar interface 330 when a CBE may be released. The work distribution crossbar interface 330 keeps a count per CBE of how many screen-space pipelines (where a screen-space pipeline includes the setup 321 , rasterizer 322, PreROP 324, and TPCs 310) are using the CBE. When this count for a particular CBE goes to zero, the work distribution crossbar interface 330 may release that CBE.

[0078] Geometry processing unit 425 is a programmable execution unit that is configured to execute geometry shader programs, transforming graphics primitives received from primitive assembler 420 as specified by the geometry shader programs. For example, geometry processing unit 425 may be programmed to subdivide the graphics primitives into one or more new graphics primitives and calculate

parameters, such as plane equation coefficients, that are used to rasterize the new graphics primitives.

[0079] In some embodiments, geometry processing unit 425 may also add or delete elements in the geometry stream. Geometry processing unit 425 outputs the parameters and vertices specifying new graphics primitives to a viewport scale, cull, and clip unit 450. Geometry processing unit 425 may read data that is stored in parallel processing memory 204 or system memory 104 for use in processing the geometry data. Viewport scale, cull, and clip unit 450 performs clipping, culling, and viewport scaling and outputs processed graphics primitives to a rasterizer 455.

[0080] Rasterizer 455 scan converts the new graphics primitives and outputs fragments and coverage data to fragment processing unit 460. Additionally, rasterizer 455 may be configured to perform z culling and other z-based optimizations.

[0081] Fragment processing unit 460 is a programmable execution unit that is configured to execute fragment shader programs, transforming fragments received from rasterizer 455, as specified by the fragment shader programs. For example, fragment processing unit 460 may be programmed to perform operations such as perspective correction, texture mapping, shading, blending, and the like, to produce shaded fragments that are output to raster operations unit 465. Fragment processing unit 460 may read data that is stored in parallel processing memory 204 or system memory 104 for use in processing the fragment data. Fragments may be shaded at pixel, sample, or other granularity, depending on the programmed sampling rate.

[0082] Raster operations unit 465 is a processing unit that performs raster operations, such as stencil, z test, blending, and the like, and outputs pixel data as processed graphics data for storage in graphics memory.

[0083] The processed graphics data may be stored in graphics memory, e.g., parallel processing memory 204, and/or system memory 104, for display on display device 1 10 or for further processing by CPU 102 or parallel processing subsystem 1 12. In some embodiments of the present invention, raster operations unit 465 is configured to compress z or color data that is written to memory and decompress z or color data that is read from memory.

[0084] Figure 5 is a flow diagram of method steps for rendering primitives while maintaining API primitive ordering, according to one embodiment of the present invention. Although the method steps of Figure 5 are described in conjunction with the systems of Figures 1 , 2, 3A, 3B, and 3C, persons skilled in the art will understand that any system configured to perform the method steps, in any order, is within the scope of the inventions. [0085] At step 500 the primitives are received by the primitive distribution unit 200 in an API primitive order. At step 505 the primitive distribution unit 200 generates primitive batches of the primitives for parallel object-space (geometry) processing by the TPCs 310. For each primitive batch a TPC 310 receives attribute buffer addresses of vertex buffers and the primitive descriptors that each include the primitive type (triangle strip, triangle mesh, line, and the like), flags, and indices of vertices. The TPC 310 uses the attribute buffer addresses and indices to calculate the addresses of the vertex attributes. The TPC 310 loads vertex attributes from external memory via the L2 cache 350 and crossbar unit 210. A TPC 310 only fetches attributes once per batch, regardless of the number of primitives in the batch that refer to the vertex. Some vertices may be referenced by primitives in multiple batches processed on different TPCs 310. The vertex data will be fetched separately by each TPC 310 over the crossbar unit 210, but the L2 cache 350 will usually retain the vertex data from the first reference, so vertex data is typically fetched from the external memory only once.

[0086] At step 510 the primitive distribution unit 200 distributes batches of the primitives for parallel geometry processing by the TPCs 310. At step 515 the TPCs 310 perform object-space processing on the primitives to produce streams of object- space processed primitives. The time to process one vertex is independent of how large the primitive appears on the screen. By distributing geometry processing in vertex batches, the processing load is distributed across the GPCs 208.

[0087] At step 520 the TPCs 310 write the vertex attributes that are produced by the object-space processing of the primitives into a circular buffer of the L2 cache 350 via the network interface 328. In some embodiments, the TPC 310 also computes the bounding box of each non-culled primitive and outputs the bounding box with the primitive descriptor and attribute buffer address to the corresponding WWDX 340 within the work distribution crossbar interface 330.

[0088] At step 525 a GPC mask is computed for each primitive to classify each primitive based on the screen tile mapping to the GPCs 208. At step 530 each primitive is routed by the work distribution crossbar interface 330 through the work distribution crossbar fabric 334 to the GPC(s) 208 that are indicated by the GPC mask for screen-space processing. Note that multiple streams of object-space processed primitives within a single GPC 208 may be merged by the aggregation unit 345 before being output by the GPC 208. In that case, the primitives are reordered by the aggregation unit 345 to match the API primitive order.

[0089] At step 535 the primitives are reordered by SWDX 346 in the GPC 208 to match the API primitive order. At step 540 the vertex attributes needed for screen- space processing of the primitives are read by the setup 321 and TPCs 310 using the attribute buffer address received with each primitive descriptor.

[0090] At step 545 parallel sceen-space processing of the reordered primitives is performed by the GPCs 208. The setup units 321 convert vertex attributes into plane equations describing polygon edges, depth values, and other parameters to be interpolated. Setup 321 also computes the primitive bounding box and initialization parameters for the rasterizer 322, and performs various culling operations such as back-face and zero-area culling. Setup 321 receives primitive descriptors in API primitive order from the SWDX 346 within the work distribution crossbar interface 330. Each primitive descriptor is associated with an attribute buffer address, i.e., a pointer to the processed vertex attribute data stored in circular buffers in the L2 cache 350. Setup 321 requests x, y, z position attributes, which are common for all primitives a given type, regardless of the number of additional vertex attributes. When these are returned from the L2 cache 350 via the crossbar 330, setup 321 computes edge and partial plane equations for the primitive. Final plane equations for each attribute are computed by an engine (not shown) using the partial plane equations produced by setup 321 . The engine loads the computed final plane equations into a plane- equation RAM that is readable by a fragment shader program that is executed by the streaming multiprocessors within each TPC 310. At step 545 the rasterizer 322 iterates within the primitive bounding box, guided by the edge equations, to identify screen tiles with sample coverage. Rasterizer 322 rasterizes the primitive pixels that lie within the screen-space tile(s) for which the GPC 208 is responsible. The rasterizer 322 advantageously skips over screen tiles that are assigned to other rasterizers 322. In some embodiments the rasterizer 322 is configured to skip over screen tiles in zero time.

[0091] The TPCs 310 also execute parallel fragment shaders at step 545. In some embodiments, attributes are only evaluated when requested by the fragment shader allowing interpolation to be performed at any desired x,y location within the pixel, and need not be the same location for each pixel. When an interpolation instruction is executed by the fragment shader, the corresponding plane equation is read from the plane-equation RAM, evaluated at the designated (x,y) location, and division by w performed. A given attribute can be referenced any number of times within a fragment shader program at any desired (x,y) sample location. Attributes that are not requested are not evaluated.

[0092] The fragment shader may perform texture, math, or other operations, read or write registers, and read or write global memory. The fragment shader stores its results in color (and optionally z) output registers. Shader output logic pulls final colors from the shader output registers and sends them to ROPs 360 associated with the frame-buffer partitions over the crossbar unit 210. At step 550 the rasterized pixels of an image are output and stored.

[0093] The crossbar unit 210 need not maintain ordering among all data packets. The crossbar unit 210 does need to ensure that all data from a particular GPC 208 to a particular ROP 360 is conveyed in order, which it may do using deterministic routing or other methods known to those skilled in the art.

[0094] Parallel rendering enables the rendering of multiple primitives per system clock. Object-space primitive processing workload (geometry processing) is distributed across multiple processing cores in order to enable the rendering of multiple primitives per system clock. The object-space processed primitives are distributed across a work distribution crossbar for parallel rasterization. The object- space processed primitives are reordered by the parallel rasterizers to restore the API primitive order before the primitives are rasterized.

[0095] One embodiment of the invention may be implemented as a program product for use with a computer system. The program(s) of the program product define functions of the embodiments (including the methods described herein) and can be contained on a variety of computer-readable storage media. Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g., read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips or any type of solid- state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writable storage media (e.g., floppy disks within a diskette drive or hard-disk drive or any type of solid-state random-access semiconductor memory) on which alterable information is stored.

[0096] The invention has been described above with reference to specific embodiments. Persons skilled in the art, however, will understand that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The foregoing description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.