Title:
OSCILLATION CIRCUIT, OSCILLATION METHOD, AND PLL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/195614
Kind Code:
A1
Abstract:
The present invention relates to an oscillation circuit, an oscillation method, and a PLL circuit, whereby reduced power consumption and suppression of jitter (phase noise) degradation can be achieved at the same time. The oscillation circuit according to a first aspect of the present invention is provided with an electric current control oscillator, a synthesis circuit for supplying a synthetic electric current to the electric current control oscillator, a bias circuit for imparting a bias to the synthesis circuit, and a conversion circuit for supplying a control electric current to the synthesis circuit, the synthesis circuit generating the synthetic electric current on the basis of the control electric current and a bias electric current occurring in conjunction with the bias from the bias circuit. The present invention can be applied to a digital PLL circuit and to an analog PLL circuit.
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Inventors:
FUJIWARA TETSUYA (JP)
FUJITA HIROAKI (JP)
SHINOHE YUSUKE (JP)
SHOJI NORIO (JP)
FUJITA HIROAKI (JP)
SHINOHE YUSUKE (JP)
SHOJI NORIO (JP)
Application Number:
PCT/JP2017/016664
Publication Date:
November 16, 2017
Filing Date:
April 27, 2017
Export Citation:
Assignee:
SONY CORP (JP)
International Classes:
H03K3/03; H03L7/099
Foreign References:
| JP2008283333A | 2008-11-20 | |||
| JPH1084278A | 1998-03-31 | |||
| JP2005020704A | 2005-01-20 |
Attorney, Agent or Firm:
NISHIKAWA Takashi et al. (JP)
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