TECHNICAL FIELD OF THE DISCLOSURE

The present disclosure is in the field of oscillator circuits, and relates in particular to a delay and offset-voltage compensated relaxation oscillator circuit.

BACKGROUND

Oscillators may be used to generate clock signals that are fundamental to the operation of both analogue and digital circuitry. Increasingly, integrated oscillators, e.g. oscillators formed in silicon-based integrated circuits, are replacing known crystal oscillators.

Advantageously, such integrated oscillators may require less power-up time, consume less power, and be relatively cheap to implement in comparison to crystal oscillators.

Such integrated oscillators may commonly be implemented as relaxation oscillators. In an example, a prior art relaxation oscillator may generally operate by charging and discharging a capacitor to a predefined reference voltage, wherein the reference voltage may be provided to a comparator as input to detect if the capacitor has been charged or discharged beyond a/the respective reference voltage. An output of the comparator may be used to indicate whether the capacitor is to be charged or discharged.

Relaxation oscillators may offer a good compromise of fast start-up, low power consumption, compact area, and other parameters critical for modern consumer applications. However, an accuracy and stability of the output frequency of such relaxation oscillators may be limited by non-ideal characteristics of the comparator. For example, comparators typically exhibit offset voltages and at least some propagation delay, which can directly impact an output of the oscillator.

Furthermore, such detrimental effects due to the non-ideal characteristics of the comparators may become more pronounced at relatively low-voltage technology nodes, e.g. 1.2 volts, 1.0 volts, 0.8 volts or even lower voltages, as may typically be found in CMOS technology nodes below approximately 100 nanometres.

It is therefore desirable to provide a relaxation oscillator circuit wherein performance is optimised by cancelling or at least limiting any offset voltage and propagation delay incurred by the comparator stage. Furthermore, it is desirable that such a relaxation oscillator circuit is suitable for reuse in relatively low-voltage circuits, such as 1.2 volts and below.

It is therefore an aim of at least one embodiment of at least one aspect of the present disclosure to obviate or at least mitigate at least one of the above identified shortcomings of the prior art.

SUMMARY

The present disclosure is in the field of oscillator circuits, and relates in particular to a delay and offset-voltage compensated relaxation oscillator circuit suitable for use in integrated devices and sensor front-ends.

According to a first aspect of the disclosure, there is provided an oscillator circuit, comprising: a first integrator unit configured to charge a first capacitor at a first integration node; a second integrator unit configured to charge a second capacitor at a second integration node; and a third integrator unit configured to charge a third capacitor at a third integration node.

The oscillator circuit also comprises a chopped comparator unit comprising: a first switching unit configurable to couple a first reference voltage and one of the first integration node and the second integration node to a first comparator; a second switching unit configurable to couple a second reference voltage and one of the first integration node or the second integration node to a second comparator; and a third switching unit configured to couple the third integration node and the second reference voltage to a third comparator.

The oscillator circuit also comprises a logic unit configured to: receive a first output from the first comparator, a second output from the second comparator and a third output from the third comparator; and use the first, second and third outputs to generate input clock signals and measurement signals for controlling the integrator units and the switching units.

Advantageously, the disclosed circuit, may effectively compensate for delay and offset induced by the comparators. Furthermore, the disclosed circuit may be particularly suitable for use in low voltage applications, as described in more detail below.

The second reference voltage may be half of the voltage level of the first reference voltage. The first switching unit and the second switching unit may be configurable to enable a simultaneous comparison of the first integration node with the first reference voltage and the second reference.

The first switching unit and the second switching unit may be configurable to enable a simultaneous comparison of the second integration node with the first reference voltage and the second reference voltage.

The third integrator unit may be configured as a replica integrator for replicating the first integrator unit and/or the second integrator unit.

That is, the third integrator unit may be formed from the same components and configured to operate is a substantially similar way to the first integrator unit and/or the second integrator unit, as described in more detail below.

The first capacitor, the second capacitor and the third capacitor may have the same storage capacity. The first switching unit, second switching unit and the third switching unit may be substantially identical. The first comparator, the second comparator and the third comparator may be substantially identical.

As such, variations in electrical characteristics of the first, second and third integrator unit will behave substantially the same way over a full range of voltage and temperate operating conditions.

The logic unit may be configured to generate a first input clock signal. The logic unit may be configured to generate a second input clock signal. The logic unit may be configured to generate a third input clock signal. The logic unit may be configured to generate a fourth input clock signal. The logic unit may be configured to generate a first measurement signal. The logic unit may be configured to generate a second measurement signal.

The first integrator unit may comprise a first current source coupled to a supply reference, and a first switch for coupling the first current source to the first capacitor, the first switch controlled by an inverse of the first input clock signal generated by the logic unit.

The first integrator unit may comprise a second switch configurable to discharge the first capacitor to a ground reference, the second switch controlled by the first input clock signal.

The first integrator unit may comprise a second current source coupled to the supply reference and having a third switch for coupling the second current source to the first capacitor, the third switch controlled by the second measurement signal. The second integrator unit may comprise a third current source coupled to the supply reference, and a fourth switch for coupling the third current source to the second capacitor, the fourth switch controlled by the first input clock signal.

The second integrator unit may comprise a fifth switch configurable to discharge the second capacitor to the ground reference, the fifth switch controlled by an inverse of the first input clock signal.

The second integrator unit may comprise a fourth current source coupled to the supply reference and having a sixth switch for coupling the fourth current source to the second capacitor, the sixth switch controlled by the first measurement signal.

The third integrator unit may comprise a fifth current source coupled to the supply reference, and a seventh switch for coupling the fifth current source to the third capacitor, the seventh switch controlled by the fourth input clock signal.

The third integrator unit may comprise an eighth switch configurable to discharge the third capacitor to the ground reference, the eighth switch controlled by an inverse of the fourth input clock signal .

Compared to prior art integrator units implemented in relaxation oscillators, the above described first, second and third integrator units do not have current sources implemented between the respective integration nodes and a ground reference. That is, only switches are implemented between the respective integration nodes and the ground references. This makes the disclosed oscillator circuit particularly well suited to low-voltage applications, because the switches are suited to operating in such conditions. This may enable any reference voltage to which integration nodes are compared (as described below) to be particularly low, for example 100mV, 250mV, or the like. In prior art circuits, such low voltage operation would not have been possible, because any current source operating between the integration modes and the ground reference would have insufficient voltage to operate, e.g. would not even meet its saturation requirements.

When the first input clock signal is low, the first switching unit may operate such that a first voltage at the first integration node is received at a non-inverting input of the first comparator and the reference voltage is received at an inverting input of the first comparator.

When the first input clock signal is high, the first switching unit may operate such that the reference voltage is received at the non-inverting input of the first comparator and a second voltage at the second integration node is received at an inverting input of the first comparator. When the second input clock signal is low, the second switching unit may operate such that the first voltage at the first integration node is received at a noninverting input of the second comparator and the second reference voltage is received at an inverting input of the second comparator.

When the second input clock signal is high, the second switching unit may operate such that the second reference voltage is received at the non-inverting input of the second comparator and the second voltage at the second integration node is received at an inverting input of the second comparator.

When a third input clock signal is low, the third switching unit may operate such that a third voltage at the third integration node is received at a non-inverting input of the third comparator and the second reference voltage is received at an inverting input of the second comparator.

When the third input clock signal is high, the third switching unit may operate such that the second reference voltage is received at the non-inverting input of the third comparator and the third voltage is received at an inverting input of the third comparator.

Advantageously, the above-described configuration may effectively cancel any effects of offset voltage of the comparators. This is because each comparator may be configured such that in a first half-cycle in which an integrating node is at the noninverting input and a reference voltage is at the inverting input, and then in a second half-cycle the inputs to the comparator are swapped such that an integrating node is at the inverting input and a reference voltage is at the non-inverting input. As such, although there may be a difference between each half-cycle, when summed together any offset voltage is effectively cancelled.

The logic unit may be configured to generate a further clock signal having a frequency twice that of the first input clock signal.

Advantageously, the disclosed oscillator circuit, which is described in more detail below with reference to the example embodiment of Figure 1, may provide a high frequency output that is twice a frequency of the highest frequency input clock signal used to control the integrator units and/or switching units. That is, the disclosed circuit may provide a relatively high frequency output without incurring substantial power consumption.

The logic unit may be configured such that a logical value of the first input clock signal is equal to a logical value of the first output. In some examples, the first input clock signal may be provided as a clock signal to a device in which the oscillator circuit is implemented.

The logic unit may be configured such that a logical value of the second input clock signal is equal to a logical value of the second output.

In some examples, the second input clock signal may additionally or alternatively be provided as a clock signal to a device in which the oscillator circuit is implemented.

The logic unit may be configured such that a logical value of the third input clock signal is equal to a logical value of the third output.

The logic unit may be configured such that a logical value of the fourth input clock signal is equal to a logical NAND of: a logical NAND of the first, second and third input clock signals; and a logical NAND of the inverse of each of the first, second and third input clock signals.

The logic unit may be configured such that a logical value of the further clock signal is equal to a logical XNOR of the first input clock signal and the second input clock signal.

The logic unit may be configured such that a logical value of the first measurement signal is equal to a logical AND of the first input clock signal and an inverse of the third input clock signal.

The logic unit may be configured such that a logical value of the second measurement signal is equal to a logical AND of an inverse of the first input clock signal and the third input clock signal.

According to a second aspect of the disclosure, there is provided a device comprising the oscillator circuit according to the first aspect. The oscillator circuit may typically be configured to provide a clock signal having a frequency of at least 1 MHz. In some embodiments, the oscillator circuit may be configured to provide a clock signal having a frequency of less than 1 MHz. In some examples, the oscillator circuit may be provided with a supply voltage of 1.2 volts, 1.0 volts or less.

That is, the disclosed oscillator circuit is suitable for implementation in advanced technology nodes, wherein a supply voltage may be relatively low, such as at 1 volt or even less. Furthermore, the disclosed oscillator circuit is capable of simultaneously operating at such low voltages while also operating in a MHz frequency range. The device may be, or may be component of, an integrated circuit, such as a system-on-chip, a processor, a microcontroller, and ASIC, a sensor, or a sensor frontend.

The above summary is intended to be merely exemplary and non-limiting. The disclosure includes one or more corresponding aspects, embodiments or features in isolation or in various combinations whether or not specifically stated (including claimed) in that combination or in isolation. It should be understood that features defined above in accordance with any aspect of the present disclosure or below relating to any specific embodiment of the disclosure may be utilized, either alone or in combination with any other defined feature, in any other aspect or embodiment or to form a further aspect or embodiment of the disclosure.

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS

These and other aspects of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, wherein:

Figure 1 depicts an example of a relaxation oscillator circuit, according to an embodiment of the disclosure;

Figure 2 depicts first, second and third integrator units of the relaxation oscillator circuit of Figure 1 ;

Figure 3 depicts a chopped comparator unit of the relaxation oscillator circuit of Figure 1 ;

Figure 4 depicts a logic unit of the relaxation oscillator circuit of Figure 1 ; and

Figure 5 depicts signal waveforms corresponding to operation of the relaxation oscillator circuits of Figures 1 to 4; and

Figure 6 depicts a device comprising an oscillator circuit according to an example of an embodiment of the disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Figure 1 depicts an example of an oscillator circuit, according to an embodiment of the disclosure. The oscillator circuit comprises a first integrator unit 100, a second integrator unit 200 and a third integrator unit 300. The oscillator circuit also comprises a chopped comparator unit 400 and a logic unit 500. Figure 2 depicts a magnified view of the first, second and third integrator units 100, 200, 300 of the oscillator circuit of Figure 1.

The first integrator unit 100 comprises a first capacitor Cci, and an arrangement of current sources and switches for charging and discharging the first capacitor Cci, to control a first voltage VC1 at a first integration node 105.

The first integrator unit 100 comprises a first current source IREFU . The first current source IREFU is coupled to a supply reference VDD. A first switch Sn is provided for selectively coupling the first current source IRE U to the first capacitor Cci.

In some embodiments, the supply reference VDD may be a relatively low voltage that may be associated with an advanced semiconductor fabrication node, e.g. 90nm, 40nm, 22nm or beyond. The supply reference DD may, for example, be 1.2V, 1.0V, 0.8V, or even lower.

The first switch controlled by an inverse of a first input clock signal C1, generation of which will be described in more detail below.

The first integrator unit 100 also comprises a second switch S12 configurable to discharge the first capacitor Cci to a ground reference Vss. The ground reference may be at 0 volts relative to the supply reference VDD. The second switch is controlled by the first input clock signal C1.

The first integrator unit 100 also comprises a second current source IRE I2 coupled to the supply reference VDD. A third switch S13 is provided for selectively coupling the second current source to the first capacitor Cci, e.g. to charge the first capacitor Cci. The third switch S13 is controlled by a second measurement signal D2, generation of which will be described in more detail below.

As such, by controlling the first input clock signal C1 and the second measurement signal D2, the first integrator unit 100 may be configured to charge and discharge the first capacitor Cci thereby defining the first voltage VC1 at the first integration node 105.

The second integrator unit 200 comprises a second capacitor Cc2, and an arrangement of current sources and switches for charging and discharging the second capacitor Cc2, to control a second voltage VC2 at a second integration node 205.

The second integrator unit 200 comprises a third current source IREF2I . The third current source IRE 2I is coupled to the supply reference VDD. A fourth switch S21 is provided for selectively coupling the third current source IRE 2I to the second capacitor Cc2.

The fourth switch is controlled by the first input clock signal C1. The second integrator unit 200 also comprises a fifth switch S22 configurable to discharge the second capacitor Cc2 to the ground reference Vss. The fifth switch is controlled by an inverse of the first input clock signal C1 .

The second integrator unit 200 also comprises a fourth current source IREF22 coupled to the supply reference VDD. A sixth switch S23 is provided for selectively coupling the third current source to the second capacitor Cc2, e.g. to charge the second capacitor Cc2. The sixth switch S13 is controlled by a first measurement signal D1 , generation of which will be described in more detail below.

As such, by controlling the first input clock signal C1 and the first measurement signal D1 , the second integrator unit 200 may be configured to charge and discharge the second capacitor Cc2 thereby defining the second voltage VC2 at the second integration node 205.

The third integrator unit 300 comprises a third capacitor Ccs, and an arrangement of a current source and switches for charging and discharging the third capacitor Cc3, to control a voltage VC3 at a third integration node 305.

The third integrator unit 300 comprises a fifth current source IREFSI . The fifth current source IREFSI is coupled to the supply reference VDD. A seventh switch S31 is provided for selectively coupling the fifth current source IREFSI to the third capacitor Cc3.

The seventh switch is controlled by a fourth input clock signal C4, generation of which will be described in more detail below.

The second integrator unit 200 also comprises an eighth switch S32 configurable to discharge the third capacitor Cc3 to the ground reference Vss. The eighth switch S32 is controlled by an inverse of the fourth input clock signal C4.

As such, by controlling the fourth input clock signal C4, the third integrator unit 300 may be configured to charge and discharge the third capacitor Cc3 thereby defining the voltage VC3 at the third integration node 305.

The third integrator unit 300 may be effectively configured as a “replica integrator”, e.g. an integrator configured as a replica of the first integrator unit 100 and the second integrator unit 200.

For example, components of the third integrator unit 300 may be substantially identical to components of the first integrator unit 100 and the second integrator unit 200. For example, third capacitor Cc3 has a same storage capacity as the first capacitor Cci and the second capacitor Cc2.

Figure 3 depicts a magnified view of the chopped comparator unit 400 of the oscillator circuit of Figure 1 . The chopped comparator unit 400 comprises a first switching unit 410.

The chopped comparator unit 400 comprises a first comparator 415.

The first switching unit 410 has an input coupled to the first integration node 105, an input coupled to a first reference voltage VREF, and an input coupled to the second integration node 205.

The first switching unit 410 has a first switch output A1 , which is coupled to a non-inverting input of the first comparator 415.

The first switching unit 410 has a second switch output A2, which is coupled to an inverting input of the first comparator 415.

The first switching unit 410 has control inputs 445, 450. A control input 445 corresponds to a first input clock signal C1 , generation of which is described in more detail below. A control input 450 corresponds to an inverse of the first input clock signal C1.

The first switching unit 410 can be configured to either: connect the first integration node 105 to the first switch output A1 and the reference voltage VREF at the second input to the second switch output A2 when the first input clock signal C1 is low, e.g. a logical low or ‘O’; or connect the reference voltage REF to the first switch output A1 and the second integration node 205 to the second switch output A2.

As such, when the first input clock signal C1 is low, the first switching unit 410 operates such that the first voltage VC1 at the first integration node 105 is received at the non-inverting input of the first comparator (415) and the reference voltage VREF is received at an inverting input of the first comparator 415, and when the first input clock signal C1 is high, the first switching unit 410 operates such that the reference voltage VREF is received at the non-inverting input of the first comparator 415 and the second voltage VC2 at the second integration node 205 is received at an inverting input of the first comparator 415.

A first comparator output B1 from the first comparator 415 is provided to the logic unit 500.

Also depicted in Figures 1 and 3 for purposes of illustration only is a first voltage offset VOFFI at the inverting input to the first comparator 415. The first voltage offset VOFFI is depicted to represent an inherent offset that the first comparator 415 may exhibit, and is not an actual component of the circuit per se.

The chopped comparator unit 400 comprises a second switching unit 420.

The chopped comparator unit 400 comprises a second comparator 425. The second switching unit 420 has an input coupled to the first integration node 105, an input coupled to a second reference voltage VREF/2, and an input coupled to the second integration node 205.

The second switching unit 420 has a third switch output A3, which is coupled to a non-inverting input of the second comparator 425.

The second switching unit 420 has a fourth switch output A4, which is coupled to an inverting input of the second comparator 425.

The second switching unit 420 has control inputs 455, 460. A control input 455 corresponds to a second input clock signal C2, generation of which is described in more detail below. A control input 460 corresponds to an inverse of the second input clock signal C2.

The second switching unit 420 can be configured to either: connect the first integration node 105 to the third switch output A3 and the second reference voltage VREF/2 to the fourth switch output A4 when the second input clock signal C2 is low, e.g. a logical low or ‘O’; or connect the second reference voltage REF/2 to the third switch output A3 and the second integration node 205 to the fourth switch output A4.

As such, when the second input clock signal C2 is low, the second switching unit 420 operates such that the first voltage VC1 at the first integration node 105 is received at the non-inverting input of the second comparator 425 and the second reference voltage VREF/2 is received at an inverting input of the second comparator 425, and when the second input clock signal C2 is high, the second switching unit 420 operates such that the second reference voltage VREF/2 is received at the non-inverting input of the second comparator 425 and the second voltage VC2 at the second integration node 205 is received at the inverting input of the second comparator 425.

A second comparator output B2 from the second comparator 425 is provided to the logic unit 500.

Also depicted in Figures 1 and 3 for purposes of illustration only is a second voltage offset VOFF at the inverting input to the first comparator 415. The second voltage offset VOFF2 is depicted to represent an inherent offset that the second comparator 425 may exhibit, and is not an actual component of the circuit per se.

Based on the state of the first input clock signal C1 and the second input clock signal C2, the first switching unit 410 and the second switching unit 420 are configurable to enable a simultaneous comparison of the first integration node 105 with the first reference voltage VREF and the second reference VREF/2, and also a simultaneous comparison of the second integration node 205 with the first reference voltage VREF and the second reference voltage VREF/2.

The chopped comparator unit 400 comprises a third switching unit 430.

The first switching unit 410, the second switching unit 420 and the third switching unit 430 are substantially identical.

The chopped comparator unit 400 comprises a third comparator 435.

The first comparator 415, the second comparator 425 and the third comparator 435 are also substantially identical, e.g. formed from the same circuits and exhibiting substantially the same electrical characteristics.

The third switching unit 430 has an input coupled to the third integration node 305, an input coupled to a second reference voltage VREF/2, and another input coupled to the third integration node 305.

In example embodiments, the second reference voltage REF/2 is half of the voltage level of the first reference voltage VREF. The reference voltage VREF and the second reference voltage VREF/2 may be provided to the oscillator circuit by a further reference supply (not shown). For example, a known power supply, regulator, or bandgap reference may be provided to generate reference voltage VREF and the second reference voltage VREF/2.

The third switching unit 430 has a fifth switch output A5, which is coupled to a non-inverting input of the third comparator 435.

The third switching unit 430 has a sixth switch output A6, which is coupled to an inverting input of the third comparator 435.

The third switching unit 430 has control inputs 465, 470. A control input 465 corresponds to a third input clock signal C3, generation of which is described in more detail below. A control input 470 corresponds to an inverse of the third input clock signal C3.

The third switching unit 430 can be configured to either: connect the third integration node 305 to the fifth switch output A5 and the second reference voltage VREF/2 to the sixth switch output A6 when the third input clock signal C3 is low, e.g. a logical low or ‘O’; or connect the second reference voltage VREF/2 to the fifth switch output A5 and the third integration node 305 to the sixth switch output A6.

As such, when the third input clock signal C3 is low, the third switching unit 430 operates such that the third voltage VC3 at the third integration node 305 is received at the non-inverting input of the third comparator 435 and the second reference voltage VREF/2 is received at an inverting input of the third comparator 435, and when the third input clock signal C3 is high, the third switching unit 430 operates such that the second reference voltage VREF/2 is received at the non-inverting input of the third comparator 435 and the third voltage VC3 at the third integration node 305 is received at the inverting input of the third comparator 435.

A third comparator output B3 from the third comparator 435 is provided to the logic unit 500.

Again, also depicted in Figures 1 and 3 for purposes of illustration only is a third voltage offset VOFFS at the inverting input to the third comparator 435. The third voltage offset VOFFS is depicted to represent an inherent offset that the third comparator 435 may exhibit, and is not an actual component of the circuit per se.

The oscillator circuit comprises a logic unit 500. In the example embodiment, the logic unit is depicted as combinational logic, e.g. Boolean circuitry comprising a variety of NOT (inverter), AND, NAND, and XNOR (exclusive NOR) gates.

The logic unit receives the first comparator output B1 from the first comparator 415. The first comparator output B1 is connected to an input of a first NOT gate 510. An output of the first NOT gate 510 is connected to an input of a second NOT gate 515. An output of the second NOT gate 515 is the first input clock signal C1 , for controlling the first switch Sn, the second switch S12, the third switch S21 and the first switching unit 410. As such, a logical value of the first input clock signal C1 is equal to a logical value of the first comparator output B1.

The logic unit receives the second comparator output B2 from the second comparator 425. The second comparator output B2 is connected to an input of a third NOT gate 520. An output of the third NOT gate 520 is connected to an input of a fourth NOT gate 525. An output of the fourth NOT gate 525 is the second input clock signal 02, for controlling the second switching unit 420. As such, a logical value of the second input clock signal 02 is equal to a logical value of the second comparator output B2.

The logic unit receives the third comparator output B3 from the third comparator 435. The third comparator output B3 is connected to an input of a fifth NOT gate 530. An output of the fifth NOT gate 530 is connected to an input of a sixth NOT gate 535. An output of the sixth NOT gate 535 is the third input clock signal 03, for controlling the third switching unit 430. As such, a logical value of the third input clock signal 03 is equal to a logical value of the third comparator output B3.

The outputs of the second and fifth NOT gates 515, 530 are connected to inputs of a first AND gate 540. An output of the first AND gate 540 is the first measurement signal D1 for controlling the sixth switch S13. As such, a logical value of the first measurement signal D1 is equal to a logical AND of the first input clock signal C1 and an inverse of the third input clock signal C3.

The outputs of the first and sixth NOT gates 510, 535 are connected to inputs of a second AND gate 545. An output of the second AND gate 545 is the second measurement signal D2 for controlling the third switch S13. As such, a logical value of the second measurement signal D2 is equal to a logical AND of the first input clock signal C1 and the third input clock signal C3.

The outputs of the second and fourth NOT gates 515, 525 are connected to inputs of a first XNOR gate 550. An output of the first XNOR gate 550 is a further clock signal CO. The further clock signal CO exhibits a frequency twice that of the first input clock signal C1.

Finally, outputs of the first, third and fifth NOT gates 510, 520, 530 are connected to inputs of a first three-input NAND gate 555. Outputs of the second, fourth and sixth NOT gates 515, 525, 535 are connected to inputs of a second three-input NAND gate 560.

Outputs of the first and second three-input NAND gates 555, 560 are connected to inputs of a first two-input NAND gate 565. An output of the first two-input NAND gate 565 is the fourth input clock signal C4 for controlling the seventh switch S31., and where in an inverse of the fourth input clock signal C4 controls the eighth switch S32

In example embodiments described above, the current sources, e.g. IREFH , IREFI2, IREF2I , IRE 22, IRE SI may be provided to the oscillator circuit by a further reference supply (not shown). For example, a known power supply, regulator, band-gap reference or voltage-to-current converter may be provided to generate the current sources. Further examples are described in more detail below with reference to Figure 6.

Operation of the relaxation oscillator of Figures 1 to 4 described with reference to the signal waveforms of Figure 5.

At an initial time (t=to), it is presumed that all the signals are forced to the initial state by a start-up circuit (not shown).

Initially, integration takes place within the first integrator unit 100 in a time interval from to to t2. As such, the first voltage VC1 at the first integration node 105 rises linearly, a rate of increase having the nominal slope AV/At=lRE /CRE . As described above, the first, second and third capacitors Cci, Cc2, Cc3 all have substantially the same capacity, hereafter referred to as CRE . Similar, the first, second, third, fourth and fifth current sources IREFH , IREFI2, IREF2I , IRE 22, IRE SI are substantially the same, and therefore a current from each source is hereafter referred to as I _RE F.

Due to the initial configuration of the first switching unit 410 and the second switching unit 420 (e.g. while C1 is low and C2 are low), the first voltage VC1 is present at the first switch output A1 and the third switch output A3.

Meanwhile, the second and third integrator blocks remain idle as the second integration node 205 is shorted to ground by the sixth switch S22 and the third integration node 305 is shorted to ground by the eighth switch S32, e.g. the second voltage VC2 and the third voltage VC3 correspond to the ground reference Vss.

At a subsequent first time (t=ti) the first voltage VC1 at the first integration node 105 signal which is present at the third switch output A3 becomes equal to the second reference voltage VREF/2 which is present at the fourth switch output A4.

Nevertheless, the second comparator output B2 from the second comparator 425 changes state at t=t2 as a result of the non-ideal characteristics of the second comparator, namely a propagation delay td2 and a voltage-offset, e.g. the second voltage offset VOFF2. The timing can be expressed as:

Following the change of the of the second comparator output B2, after t=t2, the second switching unit 420 changes state, such that the second reference voltage VREF/2 is present at the third switch output A3 and the voltage VC2 at the second integration node 205 is present at the fourth switch output A4. Meanwhile, the integrating signal, e.g. the voltage VC1 at the first integration node 105 that is present at the first switch output A1 continues to rise linearly having the same slope as prior to t=t ₂ .

Also, at time t=t2 the fourth input clock signal C4 transitions from low to high, starting integration within the third integrator unit 300 such that the third voltage VC3 present at the fifth switch output A5 also rises linearly having the nominal slope A /At=lREF/CREF. That is, at time t=t2 the third integrator unit 300 replicates the integration behaviour of the first integrator unit 100, with a phase delay corresponding tO t2.

At a subsequent time t=ts, the first voltage VC1 which is present at the first switch output A1 becomes equal to the reference voltage REF that is present at the second switch output A2. Nevertheless, the first comparator output B1 changes state at t=t4 as a result of the non-ideal characteristics of the first comparator 415, namely the propagation delay tdi and a voltage-offset, e.g. the first voltage offset VOFFI . Therefore, the following expression is valid:

After the change of the first comparator output B1 to high, the first switching unit 410 changes state, resulting in the first reference voltage RE being present at the first switch output A1 and the second voltage VC2 at the second integration node 205 being present at the second switch output A2. As a result, integration starts to take place within the second integrator block 200.

Due to the state of the first output signal B1 and the third output signal B3, the measurement signal D1 is set to high. As such, the second voltage VC2 at the second integration node 205 and present as the second switch output A2 rises linearly having the slope A /At ⁼ 2lREF/CREF.

Meanwhile, at t=t4 , the third voltage VC3 at the third integration node 305, e.g the “replica integrating voltage”, which is present at the fifth switch output A5 becomes equal to RE /2 which is present at the sixth switch output A6.

Note that time instance t4' is same as t4 in the case that the first comparator 415, the second comparator 425 and the third comparator 435 are presumed identical. However, a timing of the first, second and third comparators may differ slightly due to variations in properties of the comparators.

Due to the offset-voltage, e.g. VO S, and a propagation delay of the third comparator, the third comparator output B3 changes state from low to high at t=ts. Therefore, the following is valid:

Following the change of the third comparator output B3, the third switching unit 430 changes state, such that the third voltage VC3 is present at the sixth output and the second reference voltage VRE /2 is present at the fifth switch output A5. Also, the fourth output C4 transitions from high to low, meaning that the third integration node 305 is shorted to ground, e.g. the third integration voltage VC3 corresponds to the ground reference VSS, and the third integrator 300 is idle. At this stage, the first measurement signal D1 transitions from high to low, making the duration of the measurement signal equal to: to) ^— ( ^— t ₀ ) (4) toi can therefore be represented as follows.

The second voltage VC2 at a time t=ts, hereafter denoted VC2(ts), can be calculated as a function of the slope of the integrating signal and the duration of the measurement signal, and can be represented as follows

Also, after time t=ts, the second voltage VC2 at the second integration node 205 which is present at the second switch output A2 continues to rise having the nominal slope A /A^IREF/CREF.

At a subsequent time t=te, the second voltage VC2 present at the fourth switch output A4 becomes equal to REF/2 which is present at the third switch output A3.

At a subsequent time t=t?, the second comparator output B2 changes state from high to low as a result of the non-ideal characteristics of the second comparator 425, namely a propagation delay td2 and a voltage-offset, e.g. the second voltage offset VOFF2. The timing can be expressed as

Following the change of the second comparator output B2, after t=t? the second switching unit 420 changes the state, such that the second reference voltage VREF/2 is present at the fourth switch output A4 and the first voltage VC1 at the first integration node 105 is present at the third switch output A3. Meanwhile, the second voltage VC2 which is present at the second switch output A2 continues to rise linearly having the same slope as prior to t=t?. Also, the fourth input clock signal C4 transitions goes from low to high, starting the integration on the third integrator unit 300, such that the third voltage VC3 present at the sixth switch output A6 rises linearly having the nominal slope AV/At=lREF/CREF.

At a subsequent time t=ts, the second voltage VC2 which is present at the second switch output A2 becomes equal to the reference voltage VREF which is present at the first switch output A1. As such, the first comparator output B1 from the first comparator 420 transitions from high to low at t=tg as a result of the non-ideal characteristics of the first comparator, namely a propagation delay tdi and a voltageoffset, e.g. the first voltage offset VOFFI . Therefore, the following expression is valid:

After the transition of the first comparator output B1 to low, the first switching unit 410 changes state, such that the first reference voltage VREF is present at the second switch output A2 and the first voltage VC1 is present at the third switch output A3. As such, the integration starts to take place within the first integrator unit 100.

As a result of the state of the first comparator output B1 and the third comparator output B3, the second measurement signal D2 is set to high. As such, the first voltage VC1 present at the first switch output A1 rises linearly having the slope AV/At=21 REF/CREF.

Meanwhile, at a time t=tg', the third voltage VC3, e.g. the replica integrating voltage, which is present at the sixth switch output A6 becomes equal to the second reference voltage VREF/2 present at the fifth switch output.

Again, note that time tg' is same as tg in case all comparators are presumed identical, but may in practice slightly differ due to variations in properties of the comparators, e.g. electrical and timing characteristics of the comparators. Due to the offset-voltage and propagation delay of the third comparator 435, the third comparator output B3 changes state from high to low at a time t=t . Therefore, the following is valid:

Following the transition of the third comparator output B3 from high to low, the third switching unit 430 changes the state. As such, the third voltage VC3 is present at the fifth switch output A5 and the second reference voltage REF/2 is present at the sixth switch output A6. Also, the fourth input clock signal C4 transitions from high to low, meaning the third integration node 305 is shorted to ground and the third integrator is idle, e.g. the voltage VC3 corresponds to the ground reference Vss.

With this, the second measurement signal D2 transitions from high to low, making the duration of the measurement signal equal to: tD2 can therefore be represented as follows.

The first voltage VC1 at a time t=t , hereafter denoted VC1(tw), can be calculated as a function of the slope of the integrating signal and the duration of the measurement signal, and can be represented as follows

Also, after time t=t , the first voltage VC1 present at the first switch output A1 continues to rise having the nominal slope AV/At=lREF/CREF.

At a subsequent time t=ti3, the first voltage VC1 present at the first switch output A1 becomes equal to the first reference voltage VREF present at the second switch output A2.

Nevertheless, the first comparator output B1 transitions from low to high at t=tu as a result of the non-ideal characteristics of the first comparator, namely the propagation delay tdi and the first offset voltage VOFFI . Therefore, the following expression is valid:

With this, a complete oscillation cycle is described from t4 to ti4- An oscillation period can be calculated by adding segments as follows: Tosc — (A ^— ) + ( ^f 9 ^— ^5) + (T10 ^— ^9) + A 4 ^{— f} io) (14) resulting in

According to Equation (15), the stability of oscillation period is dependent on the stability of the reference values (VREF, IREF, CREF), together with the relative matching of the three comparator delays (tdi, td2, tds). Moreover, the contribution of the offsetvoltage of the comparator is completely negated.

Figure 6 depicts a device 600 comprising an oscillator circuit 610 according to an example of an embodiment of the disclosure. For purposes of example, the device 600 is an integrated circuit. The oscillator 610 may be the oscillator of Figure 1

The example device 600 comprises further circuity 620. The further circuitry 620 may, for example, comprise processing circuitry, a peripheral or communications device, a sensor or a sensor front-end, or indeed any synchronous circuitry that may require one or more clock signals provided by the oscillator circuit 610 to operate.

As described above, the disclosed oscillator circuit provided generates various input clock signals C1, C2, C3, C4 and measurement signals D1 , D2. Any or all of these signals may be provided as a clock source to the further circuitry 620.

For example, in the embodiment of Figure 6 the first input clock signal C1 is provided as a clock signal to the further circuitry 620. Also, the further input clock signal CO is provided as a further clock signal to the further circuitry 620, wherein the further input clock signal CO has a frequency twice that of the first input clock signal C1.

In an example embodiment, the oscillator circuit 610 may be configured to provide one or more clock signals, e.g. CO, to the further circuitry 620, wherein the one or more clock signals has a frequency of 1MHz or greater. In other example embodiments, the oscillator circuit 610 may provide the one or more clock signals to the further circuitry 620 wherein at least one of the one or more clock signals has a frequency of less than 1MHz.

Also depicted is a first reference supply 630 configured to provide the first voltage reference VREF to the oscillator circuit 610. The first voltage reference REF may be generated by the first reference supply 630 using a regulator, a band-gap reference, or other means known to provide a relatively stable reference voltage. Also depicted is a second reference supply 640 configured to provide the second voltage reference VREF/2 to the oscillator circuit 610. In the example embodiment, the first voltage reference VREF is provided to the second reference supply 640, wherein the second reference supply 640 generates the second voltage reference VREF/2 from the first voltage reference VREF. In an example, the second reference supply 640 may comprise a regulator, a voltage divider, or the like.

In other examples, the second reference supply 640 may provide the second voltage reference REF/2 to the oscillator circuit 610 without receiving the first voltage reference VREF from the first reference supply 630. In yet further examples, the first voltage reference VREF and/or the second voltage reference VREF/2 may be provided to the device 600 by an external reference, e.g. an external voltage regulator or the like.

Also depicted is a third reference supply 650. For purposes of example only, the third reference supply 650 is a Voltage-to-Current (V2I) converter, and is configured to generate a reference current IREF from the voltage reference VREF provided by the first reference supply 630.

The third reference supply 650 is configured to provide the reference current IREF for use by the integrator units of the oscillator circuit 610. For example, referring again to the example oscillator circuit of Figure 1, IREF provided by the third reference supply 650 may provide the first current source IREFH , the second current source IREFI2, the third current source IREF2I , the fourth current source IREF22 and the fifth current source IREF31 , e.g. IREF = IREF11 = IREF12 = IREF21 = IREF22 = IREF31.

That is, in the example embodiment of Figure 6 the reference current IREF that is supplied to the corresponding integrator units within the oscillator core in form of IREFH , IREF2I , ... . IREF3I , is generated outside the “oscillator core”, e.g. outside the oscillator circuit of Figure 1. The reference current IREF may be generated by the third reference supply 650 e.g. the V2I converter, such that reference current IREF is related to the ratio of the reference voltage VREF and the reference resistance RREF

In this case, Equation 15 can be expressed as Equation 17 below:

T'osc ⁼ 2 RREFCREF + 4t _dl — 2t _d2 ~ 2t _d3 (17)

The device may be fabricated in an advanced CMOS technology node configured to operate with a relatively low voltage supply (not shown), e.g. 1.2V, 1.0V, 0.8V or even less. The first voltage reference VREF may be substantially lower than the low voltage supply for the device. For example, the first voltage reference VREF may be in the region of 250mV, 200mV, 100mV or even less.

Although the disclosure has been described in terms of particular embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure, which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in any embodiments, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

REFERENCE NUMERALS

Cci first Capacitor 415 first comparator

Cc2 second capacitor 35 420 second switching unit

VREF first reference voltage 425 second comparator

VREF/2 second reference voltage 430 third switching unit

VOFFI first voltage offset 435 third comparator

VOFF2 second voltage offset 445 control input

VOFF3 third voltage offset 40 450 control input

A1 first switch output 455 control input

A2 second switch output 460 control input

A3 third switch output 465 control input

A4 fourth switch output 470 control input

A5 fifth switch output 45 500 logic unit

A6 sixth switch output 510 first NOT gate

B1 first comparator output 515 second NOT gate

B2 second comparator output 520 third NOT gate

B3 third comparator output 525 fourth NOT gate

CO further clock signal 50 530 fifth NOT gate

C1 first input clock signal 535 sixth NOT gate

C2 second input clock signal 540 first AND gate

C3 third input clock signal 545 second AND gate

C4 fourth input clock signal 550 first XNOR gate

D1 first measurement signal 55 555 first three-input NAND gate

D2 second measurement signal 560 second three-input NAND gate

100 first integrator unit 565 first two-input NAND gate

105 first integration node 600 device

200 second integrator unit 610 oscillator circuit

205 second integration node 60 620 further circuitry

300 third integrator unit 630 first reference supply

305 first integration node 640 second reference supply

400 chopped comparator unit 650 third reference supply

410 first switching unit