Background of the Invention U.S. Patent No. 5,505,072 (hereinafter the '072 patent), which is assigned to the assignee of the current application, describes a scanning circuit for a pressure responsive array.

Such arrays typically utilize two layers, each of which has a parallel array of electrodes formed thereon with the electrodes for at least one of the arrays being covered with a variable resistance pressure sensitive ink or other pressure sensitive material, which arrays are secured together with the electrodes of one layer crossing the electrodes of the other layer to form pressure points. By sensing the current passing through each pressure point, and thus the resistance thereat, the pressure at the point may be determined.

The circuit of the '072 patent provides a number of improvements over prior art sensing circuitry for such arrays, and in particular provides a mechanism for controlling the sensitivity of the array, and thus its dynamic range, by both varying an applied test voltage and providing a reference voltage which varies depending on desired sensitivity to control the circuit output. While the circuit of the '072 patent functions very well to perform its sensitivity control and other functions, the circuit requires a fair amount of hardware to perform these functions and is therefore not suitable for some applications of such sensors, including some applications where the array consists of a single pressure point, where very inexpensive sensors are required. A need therefore exists for a pressure sensor output circuit which provides sensitivity control and dynamic range which is at least as good as that for the circuit of the '072 patent, but at significantly lower cost.

In accordance with the above, this invention provides a circuit for scanning/outputting a pressure sensor having at least one sensor point, which sensor point is formed at each intersection of at least one first electrode and at least one second electrode, there being a pressure sensitive resistance between the electrodes at each sensor point. In the circuit, a first potential source ) V, is connected to each first electrode when a sensor point intersected by such first electrode is to be scanned. A circuit is also provided for generating a reference potential, which potential is a function of the desired sensitivity for the sensing/outputting circuit, the reference potential being applied at an output end of each second electrode.

Finally, a ratiometric A/D converter is provided, which converter has as inputs a second potential source (V2), an output derived from the second electrode intersecting the sensor point being scanned (van), and the reference potential (Vret), the output from the converter being the output from the circuit for scanning/outputting. For one embodiment of the invention, the first potential source is ground and the second potential source is at a selected potential Vcc. For this embodiment of the invention, the output (Dout) from the converter may be Vin - V D = x (2 1 ) ont V - cc ref where N=number of bits (resolution) for converter.

Further, for this embodiment of the invention, the gain for the converter (G), which gain influences circuit sensitivity, is given by Therefore, for this embodiment of the invention, Vref is increased to increase sensitivity.

For a second embodiment of the invention, the first potential source is the selected potential Vcc and the second potential source is ground. For this embodiment of the invention, <BR> <BR> <BR> <BR> D out Vin x(2N -1) <BR> ref and the gain is given by

V <BR> <BR> <BR> G=- Vref Thus, for this embodiment of the invention, Vref is decreased to increase sensitivity.

For preferred embodiments, there is an operational amplifier for each second electrode having the reference potential connected to its positive input and having both the output and of the corresponding second electrode and a feedback resistor connected to its negative input.

For some embodiments of the invention, there is a single sensor point intersected by a single first electrode connected to the first potential source and a single second electrode. For other embodiments of the invention, there are a plurality of sensor points in an array, a plurality of first electrodes and a plurality of second electrodes. For these embodiments, there is also a first multiplexer for connecting the first electrode for a sensor point being scanned to the first potential source and a second multiplexer for connecting an output from the second electrode intersecting the sensor point being scanned to the input of the converter.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention as illustrated in the accompanying drawings.

In the Drawings Fig. 1 is a semi-block schematic diagram of a single sensor point circuit in accordance with a first embodiment of the invention; Fig. 2 is a semi-block schematic diagram of a single sensor point circuit in accordance with a second embodiment of the invention; Fig. 3 is a semi-block schematic diagram of a multisensor point circuit in accordance with the first embodiment; Fig. 4 is a flow diagram for a calibration procedure for the circuits of Figs. 1-3; and Fig. 5 is a graph illustrating the relationship between Vrcf and gain for the various embodiments of the invention.

Referring to Fig. 1, a circuit 10 is shown having a single sensor point 12 which is illustrated in the Figure as a variable resistance. Sensor point 12 is at the intersection of a first electrode 14 connected to ground and a second electrode 16 which is connected to the negative input of an operational amplifier 18. The output from the operational amplifier is connected through a feedback resistor 20 to its negative input. A control circuit 22 is provided, one function of which is to generate a sensitivity control signal on line 24 which is applied to the input of a digital-to-analog (D/A) converter 26. The reference input to converter 26 is connected to a source 28 of a fixed voltage Vcc. For preferred embodiments, Vcc is a positive potential and converter 26 generates an analog voltage on its output line 30 which is a function of the control signal on line 24 and is between the value of Vec and ground. A pulse width modulation (PWM) converter is one example of a circuit suitable for performing the D/A function of circuit 26, but many other D/A converters might also be utilized. The voltage on line 30 will be referred to as the reference voltage (Vre,) and is applied both as a positive input to op amp 18 and to the Vow input of ratiometric A/D converter 32. The Vhjgh input for converter 32 is connected to Vec source 28 and the output from op amp 18 is connected to the Vin input of the converter. The output from converter 32 is connected both as an input to control circuit 22 and as the output from circuit 10. The circuit of Fig. 2 is identical to that of Fig. 1 except that Vec source 22 is connected to electrode 14, Vref line 30 is connected to the high input of converter 32, and the low input of this converter is connected to ground.

Fig. 3 illustrates an embodiment of the invention shown in Fig. 1 being utilized with a sensor array 36 having four first electrodes 14A-14D, four second electrodes 16A-16D, and sixteen sensor points R1-R16 located at the intersections of these electrodes. For example, sensor point R1 is located at the intersection of electrodes 14A and 16A, while sensor point R10 is located at the intersection of electrodes 1 4C and 16C. First electrodes 1 4A- 1 4D are connected to ground through a first multiplexer 38 and the outputs from op amps 1 8A- 1 8D are connected to the Vjn input of converter 32 through a second multiplexer 40. Scanning is accomplished by control circuit 22 selectively operating multiplexers 38 and 40. Thus, to scan sensor point R1, switches S1 in multiplexer 38 and S5 in multiplexer 40 are closed, while to scan sensor point R10, switch S3 in multiplexer 38 and switch S7 in multiplexer 40 are closed.

For the embodiment shown in Fig. 1 and Fig. 3,

Vin = V ref + Vref # rf rs Eq. (1) where rf is the resistance of the feedback resistor 20 for the sensor point being scanned and rS is the resistance of this sensor point.

Since, rf/rS = K F, where F is the applied force and K is a constant which is a function of the circuit parameters, equation (1) can be rewritten as Vin = Vref+Vref#KF Eq. (2) Thus, Vin to the ratiometric A/D 32 is a function both of the reference voltage, which is itself a function of desired sensitivity, and of the force applied at the sensor point.

The output (Dout), for an eight bit (i.e. N=8) ratiometric A/D 32 is <BR> <BR> <BR> <BR> <BR> Vin-Vlow <BR> Dout = #255 Eq. (3) <BR> Vhigh-Vlow For the embodiment of the invention shown in Fig. 1, this converts into Vin-Vref Dout = #255 Eq. (4) Vcc-Vref Thus, Dout is a function of Vref both because Vin is a function of Vref and because this term also appears in the equation with the ratiometric A/D. Vref is thus capable of providing significant range for the sensitivity control, while still operating within a relatively small voltage range.

In particular, equation 4 can be rewritten as The first term of this equation is the adjustable gain for the circuit, which gain is a function of Vref. Assuming, for example, that Vcc = 5 volts, Rref might vary between 0.iv and 4.5-4.9v.

This would provide a gain variation of approximately 0.02 to approximately 9, resulting in a

dynamic range of approximately 450, gain, and thus sensitivity, increasing with increasing Vrcf for these circuits (see line 42, Fig. 6).

Similarly, Vjn for the circuit shown in Fig. 2 (or for a similar multisensor point circuit which would be the same as that shown in Fig. 3 except with the potentials of Fig. 2) would be given by (Vcc - Vref) Vin=Vref - rf = Vref - (Vcc -Vref)#K#F Eq. (6) <BR> rs Similarly, <BR> <BR> <BR> <BR> <BR> <BR> Vin Vcc - Vref Eq. (7)<BR> Dout = #255 = 255 - #255#K#F Vref Vref Equation (7) is preferably mathematically manipulated to obtain the more convenient value Vcc-Vref Eq. (7') Dout = #255#K#F<BR> Vref Vcc - Vref The gain for this circuit is thus given by , which equation provides the same Vref dynamic range for variations in Vref as for the circuit of Fig. 1, but unlike the circuit of Fig. 1, gain and sensitivity decrease with increasing Vref (see line 44, Fig. 6) rather than increasing as for the embodiments of Fig. 1 and 3. More generally, sensitivity increases with increasing Vrcf when the voltage applied to the converter 32 is greater than the voltage applied to electrode(s) 14 as for Fig. 1, and decreases with increasing Vref when the voltage applied to the electrodes(s) 14 is greater as for Fig. 2.

Operation Fig. 4 illustrates the operation for calibrating the circuits of Figs. 1-3. Referring to Fig.

4, after the calibration operation starts (step 50) a known load is applied to a sensor point rS (step 52). Control circuit 22 then sets the reference voltage Vref to an initial value (step 54) and

a digital output on line 34 is measured (step 56). Control circuit 22 then makes a determination as to whether the output on line 34 is equal to the desired value for a selected circuit sensitivity (step 58). A "NO" output during step 58 results in step 60 being performed, during which a determination is made as to whether the digital output exceeds the desired value. A "YES" output during step 60 results in step 62 being performed to lower the reference voltage by a selected increment. The operation then returns to step 56 and steps 56, 58 and 60 are repeated. If, during step 60 a "NO" output is obtained, the operation branches to step 64 to increase the reference voltage by a selected increment and the operation then also returns to step 56. The sequence of operations is repeated until, during step 58, a "YES" output is obtained, indicating that the circuit is calibrated. The operation then proceeds to step 66 to terminate the calibration operation.

Once calibration has been completed, the circuits of this invention, and particularly that of Fig. 3, may be operated to perform scanning in substantially the same way as such scanning is performed in the '072 patent and in earlier U.S. Patent No. 4,856,993, which is also assigned to the assignee of the current application. Both of these prior patents are incorporated herein by reference. While the circuit of Fig. 3 does not have many of the features shown in the '072 patent, these features could be added if required. For example, the floating of the second or sensor electrodes 16 to suppress spurious signals and isolate electrodes is performed by the op amps 18, and these op amps being tied to Vref permit this function to be performed in the same way it is performed for the '072 patent with the op amps tied to ground. The discharge resistors R27-R30 of the '072 patent for discharging trace capacitances are generally required with large sensor arrays having many sensor points. If the circuit of Fig. 3 is used with such an array, these discharge resistors could be added. Similarly, the threshold detection performed by op amp 48 of the '072 patent could also be added if desired, but again this is a feature which is normally employed with large sensor arrays. Further, while Vcc and ground are the voltages used for the preferred embodiments, and this is normally preferred since it minimizes required voltage sources, any available voltages V, and V2 may be used so long as they are sufficiently different to obtain the desired pressure range and sensitivity. Finally, while specific circuits have been employed, including op amps and ratiometric A/D converters, for the various functions, these circuits are being provided by way of example only and other circuits capable of performing the same or similar functions might also be utilized.

Thus, while the invention has been particularly shown and described above with respect to preferred embodiments, the foregoing and other changes in form and detail may be made therein by one skilled in the art without departing from the spirit and scope of the invention which is to be limited only by the following claims.

What is claimed is: