OVERLAY MARK, AND OVERLAY MEASUREMENT METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING SAME

WIPO Patent Application WO/2017/200159

A1

The present invention relates to an overlay mark, and an overlay measurement method and a semiconductor device manufacturing method using the same. The present invention provides an overlay mark for determining the relative shift between two successive pattern layers or between two or more patterns separately formed on a single layer, the overlay mark comprising: a first overlay structure that includes a pair of first bars facing one another and extending in a first direction, and a pair of second bars facing one another and extending in a second direction that is orthogonal to the first direction; and a second overlay structure that includes a plurality of pairs of third bars parallel to the first bars, and a plurality of pairs of fourth bars parallel to the second bars, wherein the gaps between neighbouring third bars are different from one another, and the gaps between neighbouring fourth bars are different from one another. The overlay mark according to the present invention has different gaps between bars, thereby being capable of minimising the occurrence of errors during image analysis.

JP2002319529	PERIPHERAL ALIGNER AND SUBSTRATE PROCESSING DEVICE
JP3306125	METHOD FOR OPTICALLY CURABLY MOLDING WITH IMPROVED STRAIN SUPPRESSING CAPACITY

CHANG HYUN JIN (KR)
HA HO CHEUL (KR)
LEE GHIL SOO (KR)

PCT/KR2016/011584

November 23, 2017

October 14, 2016

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AUROS TECH INC (KR)

G03F7/20; G03F1/42; G03F9/00; H01L23/544

KR20070098029A	2007-10-05
KR20140096331A	2014-08-05
KR20070038301A	2007-04-10
KR20130064680A	2013-06-18
KR20100072886A	2010-07-01

DYNE PATENT & LAW FIRM (KR)

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