Title:
OVERSAMPLING CIRCUIT AND DIGITAL/ANALOG CONVERTER
Document Type and Number:
WIPO Patent Application WO/2001/045267
Kind Code:
A1
Abstract:
An oversampling circuit and a digital/analog converter which have small circuit scales and the component costs of which are reduced. The oversampling circuit comprises four D flip-flops (10-1 to 10-4), four multipliers (12-1 to 12-4), three adders (14-1 to 14-3), and two integrating circuits (16-1, 16-2). Input data is fed sequentially to the four D flip-flops and held therein. The multipliers multiply the data held in the respective D flip-flops by different multiplicators in the first half and second half of one clock period, and the multiplication results are added by the three adders. Furthermore, two digital integrating operations corresponding to the sum are carried out by means of the two integrating circuit.
Inventors:
KOYANAGI YUKIO (JP)
Application Number:
PCT/JP2000/008900
Publication Date:
June 21, 2001
Filing Date:
December 15, 2000
Export Citation:
Assignee:
SAKAI YASUE (JP)
KOYANAGI YUKIO (JP)
KOYANAGI YUKIO (JP)
International Classes:
H03H17/00; H03H17/06; G11B20/10; H03M3/02; H03M3/04; (IPC1-7): H03M3/04
Foreign References:
| US4167731A | 1979-09-11 | |||
| JPS6447113A | 1989-02-21 | |||
| JPH0461509A | 1992-02-27 |
Other References:
See also references of EP 1187333A4
Attorney, Agent or Firm:
Amagai, Masahiko (2nd floor 8-15, Kitashinjuku 1-chome Shinjuku-ku Tokyo, JP)
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