FIELD

The disclosure generally relates to an

overvoltage protection circuit and an electric apparatus employing the overvoltage protection circuit.

BACKGROUND

An overvoltage projection circuit is known in which a Zener diode, for example, is used to prevent an output voltage from exceeding a predetermined protection voltage even when an input voltage is greater than expected. A Zener diode has a breakdown voltage and short-circuits when a voltage applied thereto exceeds the breakdown voltage. Thus, such an overvoltage protection circuit using a Zener diode is capable of controlling an output voltage to not exceed a predetermined protection voltage even when an input voltage is greater than expected.

However, such a Zener diode may be a bit expensive and may consume a lot of power. In fact, according to a data sheet of a manufacturer, a Zener diode supplied by Diodes Incorporated, the part number thereof being SMAZ15, for example, has the maximum Zener current of 67 mA and the maximum power dissipation of 1 W. Note that this product can clamp a voltage at 15 V.

SUMMARY

According to one aspect of the disclosure, an overvoltage protection circuit includes an input terminal receiving an input voltage; an output terminal outputting an output voltage; a switch coupled between the input terminal and the output terminal; a voltage detector including a plurality of shunt regulators connected in series, the voltage detector for detecting the input voltage by the plurality of shunt regulators; and a controller, coupled with the voltage detector, for controlling the switch according to the detected input voltage to change the state of the switch between a first state of allowing electricity to flow to the output terminal and a second state of breaking the flow of electricity .

According to another aspect of the disclosure, an electric apparatus includes a direct-current power supply part supplying a direct-current voltage; the above- mentioned overvoltage protection circuit coupled to the direct-current power supply part, the overvoltage

protection circuit receiving the direct-current voltage and supplying the output voltage; and a load circuit coupled to the overvoltage protection circuit, the load circuit receiving the output voltage of the overvoltage protection circuit for operating to provide a service.

According to another aspect of the disclosure, an electric apparatus includes the above-mentioned overvoltage protection circuit; and an load circuit coupled to the overvoltage protection circuit, the load circuit receiving the output voltage of the overvoltage protection circuit for operating to provide a service.

Other objects, features and advantages of the disclosure will become more apparent from the following detailed description when read in conjunction with the accompanying drawings .

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram showing one example of an overvoltage protection circuit according to a first embodiment of the invention;

FIG. 2 shows a symbol of a shunt regulator included in the circuit shown in FIG. 1;

FIGs. 3A and 3B illustrate operations of the overvoltage protection circuit shown in FIG. 1;

FIG. 4 shows a circuit diagram of a test circuit corresponding to FIG. 1 with which the inventor tested the overvoltage protection circuit according to the first embodiment;

FIG. 5 shows a circuit diagram of an overvoltage protection circuit in a first variant of the first embodiment shown in FIG. 1;

FIG. 6 shows a circuit diagram of an overvoltage protection circuit in a second variant of the first embodiment shown in FIG. 1;

FIG. 7 shows a block diagram of a signal processing apparatus according to a second embodiment of the invention; and

FIG. 8 shows a block diagram of a signal processing apparatus in a variant of the second embodiment shown in FIG. 7.

DESCRIPTION OF EMBODIMENTS

Preferred embodiments of the invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing one example of an overvoltage protection (OVP) circuit 12 according to a first embodiment of the invention.

In FIG. 1, the OVP circuit 12 includes

positive-side and negative-side input terminals Til, T12 and positive-side and negative-side output terminals T21, T22. The plus and minus output terminals of a direct- current (DC) power supply, for example, are connected to the positive-side and negative-side input terminals Til, T12, respectively. The plus and minus input terminals of a load circuit (not shown) such as a processing part are connected to the positive-side and negative-side output terminals T21, T22, respectively.

Then, if a power supply voltage (Vin) applied to the OVP circuit 12 by the DC power supply exceeds a predetermined protection voltage Vprt of the OVP circuit 12 for some reason, the OVP circuit 12 stops the power supply for the load circuit. Therefore, by previously setting the predetermined protection voltage Vprt of the OVP circuit 12 to be less than a maximum rated voltage of the load circuit, it is possible to protect the load circuit from a power supply voltage greater than the maximum rated voltage being directly applied to the load circuit. Note that the protection voltage Vprt of the OVP circuit 12 can be set using voltage divider resistance elements R2, R3 and R4 as will be described later. Note that the resistance elements shown in FIG. 1 and so forth can be, for example, resistors, respectively.

The OVP circuit 12 includes a P-channel Metal Oxide Semiconductor (PMOS) Field Effect Transistor (FET) Ql (hereinafter, simply referred to as an "FET Ql") , a Positive-Negative-Positive (PNP) bipolar transistor Q2 (hereinafter, simply referred to as a "transistor Q2") and shunt regulators Q3 and Q4. Note that the shunt

regulators Q3 and Q4 will be described later using FIG. 2.

The source electrode Ts and the drain electrode Td of the FET Ql are connected with the positive-side input terminal Til and the positive-side output terminal

T21, respectively. The gate electrode Tg of the FET Ql is connected to the negative-side output terminal T22 via a resistance element R6. The emitter Te of the transistor Q2 is

connected with the positive-side input terminal Til, the collector Tc of the transistor Q2 is connected with the gate electrode Tg of the FET Ql and the base Tb of the transistor Q2 is connected with the cathode Tic of the shunt regulator Q3 via a series resistance element R5.

The anode Tla of the shunt regulator Q3 is connected with the cathode T2c of the shunt regulator Q4 and the reference terminal Tlr of the shunt regulator Q3 is connected with a connection point between resistance elements R2 and R3.

The anode T2a of the shunt regulator Q4 is connected with a connection point between the negative- side input terminal T12 and the negative-side output terminal T22 and the reference terminal T2r of the shunt regulator Q4 is connected with a connection point between resistance elements R3 and R4.

The resistance elements R2, R3 and R4 are connected in series to function as a voltage divider.

These resistance elements R2, R3 and R4 may be referred to as voltage divider resistance elements R2, R3 and R4, hereinafter. An input voltage Vin of the OVP circuit 12 is divided by the voltage divider resistance elements R2, R3 and R4 and the voltage divider resistance elements R2, R3 and R4 supply divided voltages to the respective reference terminals Tlr and T2r of the shunt regulators Q2 and Q3 according to the ratio of the respective resistance values of the voltage divider resistance elements R2, R3 and R4.

FIG. 2 shows a symbol of the shunt regulators shown in FIG. 1.

The shunt regulator is a well-known commercial device and is available from, for example, Texas Instruments and the part number thereof is, for example, TL431C.

As shown in FIG. 2, the shunt regulator has three terminals (electrodes), i.e., the cathode (C) , the anode (A) and the other terminal (R) (referred to as the "reference terminal" in the specification) . When the voltage applied to the reference terminal of the shunt regulator is less than a predetermined voltage (It is called "reference voltage (Vref) " hereinafter, for example, 2.495 V in TL431C.) of the shunt regulator, the shunt regulator turns off, that is, a current from the cathode does not flow to the anode. When the voltage applied to the reference terminal of the shunt regulator is greater than or equal to the predetermined voltage (the reference voltage (Vref) ) of the shunt regulator, the shunt

regulator turns on, that is, a current from the cathode flows to the anode.

Returning to FIG. 1, the OVP circuit 12 further includes a pull-up resistance element R7 connected between the emitter Te and the base Tb of the transistor Q2, a voltage-drop resistance element Rl connected between the emitter Te and the collector Tc of the transistor Q2 and a current-through resistance element R6 connected between the gate electrode Tg of the FET Ql and the negative-side output terminal T22.

Here, it will be assumed in the embodiment that the respective resistance values of the voltage divider resistance elements R3 and R4 are equal to one another.

Further, circuit configurations around the two shunt regulators Q3 and Q4 are different in that the voltage divider resistance element R4 is connected between the anode T2a and the reference terminal T2r of the shunt regulator Q4, while the voltage divider resistance element R3 is not actually connected between the anode Tla and the reference terminal Tlr of the shunt regulator Q3. In fact, as for the shunt regulator Q3, the voltage divider

resistance element R3 is connected between the reference terminal Tlr and the reference terminal T2r of the shunt regulators Q3 and Q4, respectively. However, under the condition where the resistance values of the resistance elements R3 and R4 are equal to one another, when the reference voltage (Vref) is applied across the voltage divider resistance element R3, approximately the same voltage is applied between the anode Tla and the reference terminal Tlr of the shunt regulator Q3. This was proved in an actual experiment carried out by the inventor and will be described later using FIG. 4. As to the shunt regulator Q4, when the reference voltage (Vref) is applied across the voltage divider resistance element R4, the same voltage is applied between the anode T2a and the

reference terminal T2r according to the circuit

configuration .

Then, the above-mentioned protection voltage

Vprt can be set according to the following Formula (1) or (2) :

Vprt = Vref X (R2 + R3 + R4) / R3 ... Formula (1)

Vprt = Vref X (R2 + R3 + R4) / R4 ... Formula (2)

Note that "R2", "R3" and "R4" denote the respective resistance values of the voltage divider resistance elements R2, R3 and R4.

Further, the following Formulas (3) and (4) hold in the OVP circuit 12: V _R3 = Vin X R3 / (R2 + R3 + R4) ... Formula (3)

V _R4 = Vin X R4 / (R2 + R3 + R4) ... Formula (4) Note that "V _R3 " denotes the voltage across the voltage divider resistance element R3. Similarly, "V _R4 " denotes the voltage across the voltage divider resistance value R4.

According to the Formula (3) , Vin is divided by R2, R3 and R4, and thus, V _R3 is obtained. Similarly, according to the Formula (4) , Vin is divided by R2, R3 and R4, and thus, V _R4 is obtained. Then, the thus obtained V _R3 and V _R4 are applied to the reference terminals Tlr and T2r of Q2 and Q3, respectively. Therefore, the respective resistance values R2, R3 and R4 are determined so that Vin equal to Vprt results in V _R3 and V _R4 being equal to the reference voltages (Vref) of Q3 and Q4, respectively.

As a result, when the input Vin is less than the protection voltage Vprt, the voltage applied between the reference terminal Tlr and the anode Tla of the shunt regulator Q3 is less than the reference voltage (Vref) , and thus, the shunt regulator Q3 turns off. Similarly, when the input Vin is less than the protection voltage Vprt, the voltage applied between the reference terminal T2r and the anode T2a of the shunt regulator Q4 is less than the reference voltage (Vref) , and thus, the shunt regulator Q4 turns off.

On the other hand, when the input voltage Vin is greater than or equal to the protection voltage Vprt, the voltage applied between the reference terminal Tlr and the anode Tla of the shunt regulator Q3 is greater than or equal to the reference voltage (Vref) , and therefore, the shunt regulator Q3 turns on. Similarly, when the input Vin is greater than or equal to the protection voltage Vprt, the voltage applied between the reference terminal T2r and the anode T2a of the shunt regulator Q4 is greater than or equal to the reference voltage (Vref) , and

therefore, the shunt regulator Q4 also turns on.

FIGs. 3A and 3B illustrate operations of the OVP circuit 12 according to the first embodiment described above using FIGs. 1 and 2.

In FIG. 3A, when the input voltage Vin is less than the protection voltage Vprt, a voltage less than the reference voltage (Vref) is applied between the reference terminal Tlr and the anode Tla of the shunt regulator Q3 and also a voltage less than the reference voltage (Vref) is applied between the reference terminal T2r and the anode T2a of the shunt regulator Q4. Therefore, both the shunt regulators Q3 and Q4 turn off. As a result, no base current flows out from the base Tb of the transistor Q2, and as a result, the transistor Q2 also turns off.

In this state, a current flows through the voltage-drop resistance element Rl and the current-through resistance element R6. As a result, a voltage drop

appears across the voltage-drop resistance element Rl to be applied between the source electrode Ts and the gate electrode Tg of the FET Ql . As a result, the FET Ql turns on and the input voltage Vin is, as it is, applied between the output terminals T21 and T22 as an output voltage Vout .

On the other hand, in FIG. 3B, when the input voltage Vin is greater than or equal to the protection voltage Vprt, a voltage greater than or equal to the reference voltage (Vref) is applied between the reference terminal Tlr and the anode Tla of the shunt regulator Q3 and also a voltage greater than or equal to the reference voltage (Vref) is applied between the reference terminal T2r and the anode T2a of the shunt regulator Q4.

Therefore, both the shunt regulators Q3 and Q4 turn on. As a result, a certain base current flows out from the base Tb of the transistor Q2, and as a result, the transistor Q2 also turns on.

As a result, the voltage applied to the source electrode Ts of the FET Ql is approximately equal to the voltage applied to the gate electrode Tg of the FET Ql . Therefore, the FET Ql turns off and the input voltage Vin is prevented from being applied between the output terminals T21 and T22. Thus, no output voltage appears there .

The following tables summarize the above- described operations in the OVP circuit 12 according to the first embodiment :

When Vin < Vprt

(Note: "R6" and "Rl" denote the respective resistance values of the voltage-drop resistance element R6 and the current-through resistance element Rl)

When Vin >= Vprt

Thus, the OVP circuit 12 according to the first embodiment protects a load circuit to which power is supplied via the OVP circuit 12 by preventing even a power supply voltage greater than the maximum rated voltage of the load circuit from being directly applied to the load circuit . Note that, considering a specific application of the OVP circuit 12 according to the first embodiment, the OVP circuit 12 according the first embodiment has, for example, the maximum input voltage Vin as DC 70 V. For this purpose, TL431C of Texas Instruments mentioned above having the maximum cathode voltage of 37 V with respect to the anode can be used as the shunt regulators Q3 and Q4, for example. Since the two shunt regulators Q3 and Q4 are connected in series as shown in FIG. 1, the circuit is expected to endure DC 70 V. Also, the (PMOS) FET Ql has the maximum rated drain-source voltage (Vds) of 70 V or the assigned voltage less than 70 V, for example.

FIG. 4 shows a circuit diagram of a test circuit corresponding to FIG. 1 with which the inventor tested the OVP circuit 12 according to the first

embodiment .

FIG. 4 shows the details (specific examples) of the respective elements of the test circuit. The symbols inside the parentheses correspond to the symbols of the respective circuit elements shown in FIG. 1.

Specifically, in the test circuit of FIG. 4, the FET Ql is supplied by, for example, Diodes

Incorporated and the part number thereof is ZXMP6A17E6.

In the test circuit of FIG. 4, the transistor Q2 is supplied by, for example, NXP Semiconductors and the part number thereof is PMBT2907A.

In the test circuit of FIG. 4, the shunt regulators Q3 and Q4 are supplied by, for example, Texas Instruments and the part number thereof is TL431IDBZR.

In the test circuit of FIG. 4, the respective resistance elements Rl, R2, R3, R4, R5, R6 and R7 have resistance values of: 200 kQ (Rl) , 42.2 kQ±l%(R2), 11 k Ω ±1% (R3), 11 kQ±l% (R4), 2.2 kQ (R5) , 20 kQ (R6) and 680 Ω (R7) .

In the test circuit, the protection voltage Vprt is approximately 15 V. The transistor Q2 can be a normal transistor and has the maximum rated collector- emitter voltage Vce that should be greater than the protection voltage Vprt.

The (PMOS) FET Ql should endure a high voltage. Its maximum rated drain-source voltage Vds should be greater than the maximum applied voltage.

As mentioned above, the inventor carried out an experiment and measured the voltages at respective points in the circuit of FIG. 4 and the measurement result is shown below:

In the measurement result, V _Q3 _i denotes the voltage at the cathode (1) of the shunt regulator Q3; V _Q3 _ ₂ denotes the voltage at the reference terminal (2) of the shunt regulator Q3; V _Q4 _i denotes the voltage at the cathode (1) of the shunt regulator Q4; V _Q4 _ ₂ denotes the voltage at the reference terminal (2) of the shunt regulator Q4; V _R3 denotes the voltage across the voltage divider resistance element R3; and V _Q3 _ ₂ _3 denotes the voltage between the reference terminal (2) and the anode (3) of the shunt regulator Q3. Note that the unit of all the voltage values is voltage (V) .

From the measurement result, it is seen that when 2 V (V _Q4 _ ₂ ) is applied across the voltage divider resistance element R4, 2 V (V _Q4 _ ₂ ) is applied between the anode (3) and the reference terminal (2) of the shunt regulator Q4. Also, 2 V (V _Q3 _ ₂ _ ₃ ) is applied between the anode (3) and the reference terminal (2) of the shunt regulator Q3 (on the top line in the above-mentioned table) . Note that 2 V (V _Q3 _ ₂ _ ₃ ) is acquired by subtracting 2 V (V _Q4 _i) from 47 V (V _Q3 _ ₂ ) . Thus, it can be said that the voltage (2 V) across R3 is applied between the anode and the reference terminal of Q3. Note that 2 V (V _R3 ) across R3 is acquired by subtracting 2 V (V _Q4 _ ₂ ) from 4 V (V _Q3 _ ₂ ) .

When 2.478 V (V _Q4 _ ₂ ) is applied across the voltage divider resistance element R4, 2.478 V is applied between the anode (3) and the reference terminal (2) of the shunt regulator Q4. Also, 2.467 V is applied between the anode (3) and the reference terminal (2) of the shunt regulator Q3 (on the second line in the above-mentioned table) . Note that 2.467 V (V _Q3 _ ₂ _ ₃ ) is acquired by

subtracting 2.5 V (V _Q4 _i) from 4.967 V (V _Q3 _ ₂ ) . Thus, it can be said that the voltage (2.467 V) approximately equal to the voltage (2.489 V) across R3 is applied between the anode and the reference terminal of Q3. Note that 2.489 V (V _R3 ) across R3 is acquired by subtracting 2.478 V (V _Q4 _ ₂ ) from 4.967 V (V _Q3 _ ₂ ) .

When 2.495 V (V _Q4 _ ₂ ) (the reference voltage (Vref) of Q4 as mentioned above) is applied across the voltage divider resistance element R4, 2.495 V is applied between the anode (3) and the reference terminal (2) of the shunt regulator Q4. Also, 2.52 V is applied between the anode (3) and the reference terminal (2) of the shunt regulator Q3 (on the bottom line in the above-mentioned table) . Note that 2.52 V (V _Q3 _ ₂ _ ₃ ) is acquired by

subtracting 2.48 V (V _Q4 _i) from 5 V (V _Q3 _ ₂ ) . Thus, it can be said that the voltage (2.52 V) approximately equal to the voltage (2.505 V) across R3 is applied between the anode and the reference terminal of Q3. Note that 2.505 V (V _R3 ) across R3 is acquired by subtracting 2.495 V (V _Q4 _ ₂ ) from 5 V (V _Q3 _ ₂ ) .

Note that in the above-mentioned table of the measurement result, when Vin is 12 V (on the top line in the above-mentioned table), 2 V (< 2.495 V = the reference voltage (Vref) ) is applied between the anode (3) and the reference terminal (2) of the shunt regulator Q4, and also, 2 V (< 2.495 V = the reference voltage (Vref)) is applied between the anode (3) and the reference terminal (2) of the shunt regulator Q3. Therefore, the shunt regulators Q3 and Q4 are both turned off so that the output voltage is provided from the OVP circuit (see FIG. 3A) .

In contrast thereto, when Vin is 15 V (approximately equal to Vprt) (on the second line in the above-mentioned table), 2.478 V (approximately equal to 2.495 V) is applied between the anode (3) and the

reference terminal (2) of the shunt regulator Q4, and also, 2.467 V (approximately equal to 2.495 V) is applied between the anode (3) and the reference terminal (2) of the shunt regulator Q3. Therefore, the shunt regulators Q3 and Q4 are both turned on so that no output voltage is provided from the OVP circuit (see FIG. 3B) .

Similarly, when Vin is 20 V (on the bottom line in the above-mentioned table), 2.495 V (= 2.495 V) is applied between the anode (3) and the reference terminal (2) of the shunt regulator Q4, and also, 2.52 V ( > 2.495 V) is applied between the anode (3) and the reference terminal (2) of the shunt regulator Q3. Therefore, the shunt regulators Q3 and Q4 are both turned on so that no output voltage is provided from the OVP circuit (see FIG. 3B) .

According to the first embodiment of the invention, since the two shunt regulators Q3 and Q4 are connected in series, the higher protection voltage (for example, 15 Volt to 70 Volt) can be set than that of a Zener diode.

As a variation of the first embodiment, the resistance values of the voltage divider resistance elements R3 and R4 may be different each other. One of the voltage divider resistance elements R3 and R4 should be set so that the corresponding shunt regulator turns on when the input voltage reaches the protection voltage Vprt and the other can be set so that the corresponding shunt regulator turns on when the input voltage is less the protection voltage Vprt. For example, R4 is set so that the voltage applied to R4 should be same as the reference voltage of the shunt regulator Q4. R3 is set to be greater than R4 which results in the greater voltage. This can make it easy to design the voltage divider resistance elements R3 and R4. As a variant, the resistance value of R3 may be that of R4 and the resistance value of R4 may be that of R3 in the above variation.

As a further variation of the embodiment, the shunt regulators Q3 and Q4 which have different reference voltage each other may be adopted.

FIG. 5 shows a circuit diagram showing an OVP circuit in a first variant of the first embodiment shown in FIG. 1.

In the OVP circuit 12 _\ of the first variant, a shunt regulator Q5 and a voltage divider resistance element R9, corresponding to the shunt regulator Q3 and the voltage divider resistance element R3, respectively, are added to the OVP circuit 12 of the first embodiment.

In other words, the number of shunt regulators connected in series is increased from two (2) to three (3) , and along therewith, the number of voltage divider resistance elements is increased from three (3) to four (4) . The other parts are not changed, and also, the operation principle is basically the same. Therefore, description of operations of the OVP circuit 12 _\ according to the first variant will be omitted.

Concerning the first variant of FIG. 5, in the same manner as the first embodiment of FIG. 1, the protection voltage Vprt can be set, for example, according to the following Formula (5), (6) or (7) :

Vprt = Vref X (R2 + R9 + R3 + R4) / R3 ... Formula (5)

Vprt = Vref X (R2 + R9 + R3 + R4) / R4 ... Formula (6)

Vprt = Vref X (R2 + R9 + R3 + R4) / R9 ... Formula (7)

According to the OVP circuit 12i of the first variant, since the number of shunt regulators connected in series is increased from two (2) to three (3) as mentioned above, it possible to increase the maximum rated voltage of the OVP circuit 12i in comparison to the OVP circuit 12 according to the first embodiment.

FIG. 6 shows a circuit diagram showing an OVP circuit in a second variant of the first embodiment shown in FIG. 1.

In the OVP circuit 12 ₂ of the second variant, the shunt regulator Q3 and the voltage divider resistance element R3 are removed from the OVP circuit 12 of the first embodiment.

In other words, the number of shunt regulators connected in series is reduced from two (2) to one (1) , and along therewith, the number of voltage divider resistance elements is reduced from three (3) to two (2) . The other parts are not changed, and also, the operation principle is basically the same. Therefore, description of operations of the OVP circuit 12 ₂ according to the second variant will also be omitted.

In the same manner as the first embodiment of FIG. 1, the protection voltage Vprt can be set, for example, according to the following Formula (8) : Vprt = Vref X (R2 + R4) / R4 ... Formula (8)

According to the OVP circuit 12 ₂ of the second variant, since the number of shunt regulators connected in series is reduced from two (2) to one (1) as mentioned above, it possible to reduce the cost of the OVP circuit 12 ₂ in comparison to the OVP circuit 12 of the first embodiment .

FIG. 7 shows a block diagram of a signal processing apparatus, as one example of an electric apparatus , according to a second embodiment of the invention .

The signal processing apparatus 10 (A) includes a DC power supply part 11 that receives AC power

(commercial power) and supplies DC power, the OVP circuit 12 according to the first embodiment and a processing part 13 (load circuit) that includes a video signal processing circuit (not shown) , a control unit (not shown) and so forth .

The control unit includes a processor and, for example, descrambles a video signal that is supplied from a CATV station 50 via a cable in a scrambled state. The video signal processing circuit processes the descrambled video signal to convert it into a video signal suitable for a display device such as a TV set 30 to display a video .

Note that, as for the DC power supply part 11, a known technology can be used as long as it converts commercial AC power into DC power of a desired voltage such as DC 70 V mentioned above.

It is also possible to apply a known technology of a commercially available set-top box to the processing part 13.

FIG. 8 shows a block diagram of a signal processing apparatus in a variant of the second embodiment shown in FIG. 7.

A signal processing apparatus 10 (D) according to the variant of the second embodiment is the same as the signal processing apparatus 10 (A) according to the second embodiment except that the signal processing apparatus 10 (D) does not include the DC power supply part 11 since the signal processing apparatus 10 (D) directly receives DC power supply assuming to use a DC power feeding system such as a solar cell power supply system.

Although the overvoltage protection circuits and the electric apparatuses have been described above in the specific embodiments, the invention is not limited to these embodiments, and variations and/or replacements can be made within the scope of the claimed invention.

For example, electric apparatuses according to the invention can be any type of electric apparatuses including various home electric appliances driven by AC power or DC power.