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Title:
PACKAGE FORMATION METHOD AND MEMS PACKAGE
Document Type and Number:
WIPO Patent Application WO/2015/111753
Kind Code:
A1
Abstract:
 To provide: a package suitable for housing a precision mechanism such as a micro-electrical-mechanical system (MEMS) in a hollow-sealed interior space; and a method for forming the package. This invention includes a sacrificial thin film formation step for chemical-mechanical polishing a temporary substrate made of a readily polishable material and sputtering a metal thin film along the smoothly polished surface, and a first bonding step for forming a sealing frame obtained by bringing at least a noble metal on the metal thin film and bonding a substrate on the sealing frame. This invention also includes: a temporary substrate removal step for then removing the metal thin film along with the temporary substrate and exposing a new surface at the tip of the sealing frame; and a second bonding step for sputtering a noble metal thin film around a precision machine element on the machine substrate, bringing the new surface of the sealing frame into contact onto the noble metal thin film and bonding the new surface of the sealing frame onto the noble metal thin film at room temperature. A package obtained using this method can maintain an internal vacuum state of at least 10-4 Pa for six months.

Inventors:
KURASHIMA YUUICHI (JP)
TAKAGI HIDEKI (JP)
MAEDA ATSUHIKO (JP)
Application Number:
PCT/JP2015/052181
Publication Date:
July 30, 2015
Filing Date:
January 27, 2015
Export Citation:
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Assignee:
NAT INST OF ADVANCED IND SCIEN (JP)
International Classes:
H01L23/02; B81C3/00; H01L21/02
Domestic Patent References:
WO2005122217A12005-12-22
Foreign References:
JP2009170445A2009-07-30
JP2005276910A2005-10-06
JPH0964544A1997-03-07
JPH0910963A1997-01-14
JP2012009862A2012-01-12
Other References:
H. ISHIDA ET AL.: "Low-temperature, surface- compliant wafer bonding using sub-micron gold particles for wafer-level MEMS packaging", ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC, 29 May 2012 (2012-05-29), pages 1140 - 1145, XP032210732
Y. KURASHIMA ET AL.: "Room temperature wafer bonding of metal films using flattening by thermal imprint process", MICROELECTRONIC ENGINEERING, vol. 112, pages 52 - 56, XP028727948
See also references of EP 3101687A4
S.ISHIZUKA; N.AKIYAMA; T.OGASHIWA; T.NISHIMORI; H.ISHIDA; S.SHOJI; J.MIZUNO: "Low-temperature wafer bonding for MEMS packaging utilizing screen-printed sub-micron size Au particle patterns", MICROELECTRONIC ENGINEERING, vol. 88, no. 8, August 2011 (2011-08-01), pages 2275 - 2277, XP028098109, DOI: doi:10.1016/j.mee.2011.02.083
MICHITAKA YAMAMOTO; EIJI HIGURASHI; TADATOMO SUGA; RENSHI SAWADA: "Low-temperature bonding of laser diode chips using N atmospheric-pressure plasma activation", PROCEEDINGS OF JSPE SEMESTRIAL MEETING 2013 JSPE SPRING CONFERENCE, 2013
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