Title:
PACKAGE METHOD FOR INTEGRATED POWER SUPPLY SYSTEM PACKAGING PIECE
Document Type and Number:
WIPO Patent Application WO/2018/129906
Kind Code:
A1
Abstract:
A packaging method for an integrated power supply system, comprising the following steps: providing a carrier; forming a re-wiring layer on the carrier; forming a columnar metal lead on the re-wiring layer; respectively soldering an active module and a passive module of a power supply system bare core onto the re-wiring layer; packaging and shaping the active module, the passive module, and the columnar metal lead on the re-wiring layer, and removing, by means of grinding, a redundant packaging and shaping material covering the active module, the passive module, and the columnar metal lead; forming a base solder protrusion connected to the columnar metal lead, and removing the carrier; and soldering a power consumption system bare core onto the re-wiring layer, and then packaging and fixing the power consumption system bare core onto the re-wiring layer by mean of bottom filling. By means of the three-dimensional chip stacking technology, a power supply system is directly integrated below a power consumption system bare core, so that the power transmission efficiency is improved, and the number of different available voltage rails is increased.
Inventors:
LIN JOHNSON (CN)
LIN ALAN (CN)
HO PATRICK (CN)
CAI QIFENG (CN)
LIN ALAN (CN)
HO PATRICK (CN)
CAI QIFENG (CN)
Application Number:
PCT/CN2017/095426
Publication Date:
July 19, 2018
Filing Date:
August 01, 2017
Export Citation:
Assignee:
SJ SEMICONDUCTOR JIANGYIN CORP (CN)
International Classes:
H01L21/60
Foreign References:
| CN105225965A | 2016-01-06 | |||
| CN106783649A | 2017-05-31 |
Attorney, Agent or Firm:
J.Z.M.C. PATENT AND TRADEMARK LAW OFFICE (CN)
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