Title:
PACKAGE
Document Type and Number:
WIPO Patent Application WO/2023/135929
Kind Code:
A1
Abstract:
The present invention is to enable individual design of heat dissipation properties of a plurality of chips mounted in a single package. A package (100) comprises: a substrate (101); a plurality of plate members (111, 112); and a plurality of chips (121, 122). The substrate (101) is provided with a plurality of openings (181, 182). The plurality of plate members (111, 112) have higher thermal conductivity than the substrate (101) and are provided at positions where the openings (181, 182) are blocked. The plurality of chips (121, 122) are located at least partially in the openings (181, 182), respectively, and mounted on the plurality of plate members (111, 112), respectively. The chips (121, 122) may include optical chips having optical elements formed thereon. The plates (111, 112) may have a coefficient of thermal expansion closer to the chips (121, 122) than the substrate (101). The material of the plate members (111, 112) may be metal, or resin mixed with a filler.
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Inventors:
OKA SHUICHI (JP)
Application Number:
PCT/JP2022/042698
Publication Date:
July 20, 2023
Filing Date:
November 17, 2022
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L31/02; H01L23/02; H01S5/024
Domestic Patent References:
| WO2021131833A1 | 2021-07-01 |
Foreign References:
| JP2018061238A | 2018-04-12 | |||
| JP2006186122A | 2006-07-13 | |||
| JP2015023154A | 2015-02-02 | |||
| US20160056128A1 | 2016-02-25 | |||
| JP2018197843A | 2018-12-13 | |||
| JP2012238687A | 2012-12-06 | |||
| JP2008251868A | 2008-10-16 | |||
| JP2000349344A | 2000-12-15 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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