Title:
PACKAGE
Document Type and Number:
WIPO Patent Application WO/2023/136235
Kind Code:
A1
Abstract:
The present invention makes it possible to design the heat dissipation property of each of a plurality of chips, mounted in a single package, individually. A package (100) is provided with a substrate (101), a plurality of heat-dissipating members (111, 112), and a plurality of chips (121, 122). The substrate (101) has a plurality of openings (181, 182). The plurality of heat-dissipating members (111, 112) have a higher heat conductivity compared to the substrate (101), and are respectively provided in positions to close the openings (181, 182). The plurality of chips (121, 122) are respectively at least partly positioned within the openings (181, 182), and are respectively mounted on the plurality of heat-dissipating members (111, 112). The chips (121, 122) may include an optical chip having an optical element formed therein. The heat-dissipating members (111, 112) may have a thermal expansion rate closer to that of the chips (121, 122) compared to the substrate (101). The material of the heat-dissipating members (111, 112) may be a metal or a resin having a filler mixed therein.
Inventors:
OKA SHUICHI (JP)
Application Number:
PCT/JP2023/000273
Publication Date:
July 20, 2023
Filing Date:
January 10, 2023
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L31/02; H01L23/02; H01S5/024
Domestic Patent References:
| WO2021131833A1 | 2021-07-01 |
Foreign References:
| JP2003152225A | 2003-05-23 | |||
| JP2018061238A | 2018-04-12 | |||
| JP2006186122A | 2006-07-13 | |||
| JP2015023154A | 2015-02-02 | |||
| US20160056128A1 | 2016-02-25 | |||
| JP2020126948A | 2020-08-20 | |||
| CN109361834A | 2019-02-19 | |||
| JP2018197843A | 2018-12-13 | |||
| JP2012238687A | 2012-12-06 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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