The invention relates to packing a variable number of bits from an input bit stream into an output bit stream. The invention further relates to unpacking a variable number of bits from a bit stream.

The task of a packer is to pack a variable number of bits into a bit stream. The document EP 0 390 310 A2 discloses a data packer which receives n-bit wide parallel data words and outputs m-bit wide parallel data words, where n is a variable and may change during the operation, and m is a fixed integer.

US 5 079 548 discloses a data packer intended to successively packing the coats having variable length with no gaps in to successive units of bits having a predetermined length.

US 4 667 305 discloses a data processing system including a variable width data bus for the parallel transmission of data in variable width fields or blocks between units in the data processing system where the data is described by a start position and a length and an alignment is performed in case the data field is greater than the number of bit positions available on the data bus.

It is an object of the invention to provide advantageous packing or unpacking a variable number of bits to or from a bit-stream. To this end, the invention provides a method of packing, a method of unpacking, a packer, an unpacker, a computer program product, a transmitter and a receiver as defined by the independent claims. Advantageous embodiments are defined by the dependent claims.

A method of packing a variable number of bits from an input stream into an output bit stream according to a first aspect of the invention starts by defining a maximum number n of bits which are to be packed into the output bit stream within a clock cycle and further comprises providing a validation bit stream which defines positions of those bits in said input bit stream as output bits which are to be selected for packing, selecting the output bits and adding only the output bits to said output bit stream. The bits which have not been

selected are not packed into the output bit stream because they do not contain relevant information.

The unpacking method corresponds to the packing method, but removes a number of bits from a bit string. Again a validation bit stream is used to define positions of those bits in said bit stream as remove a bit which are selected for unpacking. Only the selected removal bits are then removed from the bit stream.

In a preferred embodiment the packing and unpacking methods can be performed in a modular way. For the example, in the case of a n bit packer, it consists of n rows of shift units which can be shifted over a single bit position.

The packer and unpacker, respectively, comprise control means for defining a maximum number n of bits which are to be packed or unpacked within a clock cycle and means for providing a validation bit streams having the characteristics outlined above. A selector selects the desired bits and adds them to an existing output bit stream in the case of packing or removes them from a bit stream in the case of unpacking.

The methods of packing and unpacking a variable number of bits can be implemented by a computer program.

New mobile multi-media applications are emerging. Among them are cellular phones with video facilities, personal computers with video cameras and information technology terminals. These kinds of applications can successfully be addressed only when they are low in power consumption and low in cost. Both can be obtained by reducing the number of components to an absolute minimum. This however requires that both the compression core as the memory which is used to store a reference image for compression should be on the same integrated circuit. The packing and unpacking according to embodiments of the present invention are advantageously applied in such applications.

The invention is advantageous in the context of embedded compression, in particular in scalable compression in front of a loop memory, such as described in WO01/17268-A1.

The invention will now be further explained with reference to the accompanying drawings in which Fig. 1 shows a schematic diagram showing the packing process according to an embodiment of the invention; Fig. 2 shows an illustration explaining the process of Fig. 1 further by way of examples,

Fig. 3 is an illustration for an unpacking process according to an embodiment of the invention; and Fig. 4 is a schematic block diagram of an application of the present invention.

Fig. 1 uses a total block of e. g. 8 x 8 pixels which is converted in a string form. A second string is provided carrying the validation bit or valid bits, where values of 1 indicate the positions in the input bit stream which shall be packed into the output bit stream.

For example, pixels nr. 0, 5 and 64 are selected by the respective validation bits. Thereby, the packing behaviour is regularised, and data dependencies are reduced. Even though the embodiment has been described with a conversion of the block in a string, this conversion is not a requirement. Instead, the block structure can be directly processed by using a packer having n bits units in its validation string.

Fig. 2 illustrates by way of examples the selection of output bits. The input bit stream already consists of a string"abcdefgh". It is assumed that a maximum of 4 bits can be packed per block cycle. Which bits have to be packed is indicated by the validation bits wxyz. In this case, there is no coincidence between the validation bits and the new bits, so that the output bit stream consists of"ABCDEFGH". Whenever new bits arrive, the inputs present in the input bit stream are shifted left in order to create the required space for the new bits.

In a first specific example, the new bits are 1 *0*, and the validation bits are 1010. Accordingly, only the first and third bit from the new bits are selected and added to the input stream as 10 at the end thereof. In the second specific example, since only the third of the new bits is selected according to the validation sequence, 1 is added to the previous input bit stream resulting in 101 as final three bits. Similarly, in the third specific example, the first three new bits are added to the previous input data stream.

Fig. 3 illustrates the unpacking process by examples. If there is coincidence of a bit string to be processed with the validation string wxyz, jklh are removed from the bit stream. In the first specific example, according to the validation string, the last three bits are removed from the string, in the second example, the last bit is removed, in the third specific example those digits at the first and third position at the end of the bit string are removed.

Fig. 4 is a block diagram illustrating an application of the present invention. A video camera 1 for a personal computer (PC camera) inputs a video signal Ivideo into a packer 2 of the present invention, where the data are compressed. The compressed data stream packed in then transmitted to the personal computer 3, where it is decompressed in unpacker

4. Finally, the unpacked data stream Ounpacked is used to show the video sequence on a display 5. In figure 4, all other components of a video camera or a personal computer which are known in the art are not shown.

Current PC cameras contain at most only limited video compression functionality. This requires a direct connection between the camera and the PC in order to transmit the video sequence. However, the available band width of this connection is not large enough to handle large image sizes at high frame rates, e. g. uncompressed VGA at 30 frames per second in 4: 2: 0 format requires a band width of 105 Mbit per second. High compression ratios are therefore essential. A PC camera having a wireless connection with the personal computer requires mandatorily high compression ratios due to the even more limited band width of this connection. A detachable PC camera can capture video sequences when detached from the personal computer. The video sequences are stored on a storage medium, e. g. a hard disc or solid state memory. In order to be able to store longer sequences on this internal storage medium or to reduce its capacity, a high compression ratio is essential. Embodiments of the invention provide fast and small solutions to (un) pack bits in variable length coding, which is especially advantageous in this kind of applications.

Further applications can be seen in hand-held multimedia terminals incorporating video phone functionality or in surveillance cameras which are based on a number of detachable cameras connected to an existing low band width network. Each camera records a video sequence on its local storage medium using the method of the invention. The security operator then connects to the required camera and downloads its recorded video sequence. The invention can also been applied to smart cameras with more sophisticated functionality, for example in the field of object recognition, object tracking and character recognition.

Below, computer programs are given to define the packing and unpacking process.

Packer: LIBRARY ieee ; USE ieee. std logic-1164. ALL ; USE ieee. numeric std. ALL ; ENTITY packer IS

GENERIC (bits: INTEGER: = 257; shifts : INTEGER : = 32); PORT (clk : IN std_logic); data in : IN signed (0 TO bits + shifts-1) ; valid in IN signed (bits TO bits + shifts - 1) ; data_out : OUT signed (0 TO bits - 1)); END; ARCHITECTURE rtl OF packer IS BEGIN pack: PROCESS (data_in, valid_in) VARIABLE tmp_bits : signed (0 TO bits + shifts - 1); BEGIN <BR> BEGIN<BR> ; FOR i IN bits TO bits + shifts-I LOOP IF valid in (i) ='I'AND tmp bits tmp_bits (0 TO TO bits-1) & tmp_bits (i); END IF ; END LOOP ; data out < = tmp_bits (0 TO bits - 1) ; END PROCESS ; END ; Unpacker: LIBRARY ieee ; USE ieee. std_logic_1164. ALL ; USE ieee. numeric std. ALL; ENTITY unpacker IS GENERIC (bits : INTEGER: = 256 ; shifts : INTEGER : = 32) ; PORT (clk: INstdlogic ; data_in : IN signed (0 TO bits - 1) ; valid_in : IN signed (0 TO shifts - 1) ; data_out : OUT signed (0 TO bits + shifts - 1)); END ;

ARCHITECTUR rtl OF unpacker IS BEGIN unpack : PROCESS (data in, valid in) VARIABLE tmp_bits : signed (0 to bits + shifts-1) ; BEGIN tmp-bits data-in (0 TO bits-1) & data-in (0 TO shifts- FOR i IN 0 TO shifts-I loop IF valid_in (i) ='0'THEN tmp_bits (i + 1 TO bits + shifts - 1) : = tmp_bits (i to bits + shifts-2) ; END IF ; data_out (i) < = tmp_bits (i); END LOOP ; data-out (shifts TO bits + shifts-1) < = tmp_bits (shifts TO bits + shifts - 1) ; END PROCESS ; END ; It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word'comprising'does not exclude the presence of other elements or steps than those listed in a claim. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.