PARALLEL CONTENT ADDRESSABLE MEMORY

Title:

PARALLEL CONTENT ADDRESSABLE MEMORY

Document Type and Number:

WIPO Patent Application WO/2010/050282

Kind Code:

A1

Abstract:

Provided is a parallel CAM capable of performing a parity check at high speed during search. A CAM (10) searches through all the addresses at the same time and determines if the same data as inputted data is stored, and comprises a write/search parity generator (12) for generating respective parities (WP, SP) of n-bit write data (WD) and n-bit search data (SD), a plurality of memory locations (14) corresponding to a plurality of addresses, and a NAND circuit (16) for activating a parity error signal (PE) when at least one of valid parity coincidence signals (PMV) outputted from the memory locations (14) is inactive. Each of the memory locations (14) includes n data memory cells (2), a parity memory cell (3), an exclusive OR circuit (20) for determining if the parity (SP) and a parity (RP) coincide with each other and activating a parity coincidence signal (/PM) when the parities coincide, and a NAND circuit (22) for validating the parity coincidence signal (/PM) in response to a data coincidence signal (DML).

Inventors:

MIYATAKE HISATADA (JP)

Application Number:

PCT/JP2009/063784

Publication Date:

May 06, 2010

Filing Date:

August 04, 2009

Export Citation:

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Assignee:

IBM (US)
MIYATAKE HISATADA (JP)

International Classes:

G11C15/04

Foreign References:

JPH0922595A	1997-01-21
US7010741B2	2006-03-07
US7350137B2	2008-03-25
JPH0922595A	1997-01-21
JPS63177242A	1988-07-21

Other References: